*** empty log message ***

diff --git a/basics/ram_16x16_dp.vhd b/basics/ram_16x16_dp.vhd
index 54ef2fdf3429166e884106e163fd134509e4106e..4f93d70495039758d238e840e544cb524887e1cb 100644 (file)
--- a/basics/ram_16x16_dp.vhd
+++ b/basics/ram_16x16_dp.vhd
@@ -3,9 +3,6 @@ USE IEEE.std_logic_1164.ALL;
 USE IEEE.std_logic_ARITH.ALL;
 USE IEEE.std_logic_UNSIGNED.ALL;
 
-library work;
-use work.trb_net_std.all;
-
 entity ram_16x16_dp is
   generic(
     INIT0 : std_logic_vector(15 downto 0) := x"0000";
@@ -41,7 +38,7 @@ architecture ram_16x16_dp_arch of ram_16x16_dp is
   SIGNAL ram : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7,
                          INIT8, INIT9, INITA, INITB, INITC, INITD, INITE, INITF);
   attribute syn_ramstyle : string;
-  attribute syn_ramstyle of ram : signal is "block_ram";
+--   attribute syn_ramstyle of ram : signal is "block_ram";
 begin
   process(CLK)
     begin
@@ -52,7 +49,6 @@ begin
           ram((conv_integer(a1))) <= din1;
           dout1 <= din1;
         end if;
-
       end if;
   end process;
 

diff --git a/media_interfaces/scm_sfp/serdes_gbe_0_200.txt b/media_interfaces/scm_sfp/serdes_gbe_0_200.txt
index 1df7bc290407aaebb7a65eeb1b642f5e3ec2d008..5a6794d0ba9f15308931701707865ed7475bf6f1 100755 (executable)
--- a/media_interfaces/scm_sfp/serdes_gbe_0_200.txt
+++ b/media_interfaces/scm_sfp/serdes_gbe_0_200.txt
@@ -13,7 +13,8 @@ ch0  00 01  # link state machine enabled
 quad 00 00  # some standard settings?\r
 quad 01 E4  # RX clock select\r
 quad 28 50  # Reference clock multiplier\r
-quad 29 01  # set to 01\r
+quad 29 11  # JM101203 core clock as reference # set to 01\r
+quad 30 04  # JM101203 TX sync enable\r
 quad 02 00  # ref_pclk source is ch0, rxa_pclk is ch0, rxb_pclk is ch0\r
 quad 04 00  # MCA enable 4 channels\r
 \r
@@ -25,14 +26,14 @@ quad 16 7c  # -ve K [7:0] -> COMMA_B = 00_1111_1010 - its inverted !
 quad 17 36  # upper bits of CA,CB,CM\r
 \r
 quad 0D 97  # Watermark level on CTC: 9 high, 7 low\r
-quad 0E 0B  # insertion/deletion control of CTC: two char matching\r
+quad 0E 08  # JM101203 was 0B # insertion/deletion control of CTC: two char matching\r
 quad 11 BC  # /I2/ pattern for CTC match (K28.5)\r
 quad 12 50  # (D16.2)\r
 quad 13 04  # (use comma)\r
 \r
 quad 19 0C  # Disable word_align_en port, FPGA bus width is 16-bit/20-bit\r
 ch0  14 90  # 16% pre-emphasis\r
-ch0  15 10  # +6dB equalization\r
+ch0  15 18  # JM101203 was 10 # +6dB equalization\r
 \r
 # These lines must appear last in the autoconfig file.  These lines apply the correct\r
 # reset sequence to the PCS block upon bitstream configuration\r

diff --git a/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd b/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd
index 5e1e546d7c26d0da72b202cab3324015e7d351a4..b8732dee0a4b44c2fc1a158308f2353a1b5499b9 100755 (executable)
--- a/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd
+++ b/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd
@@ -101,7 +101,50 @@ port(
        serdes_rst           : in  std_logic;
        ref_pclk             : out std_logic
 );
-end component serdes_gbe_0_200; 
+end component serdes_gbe_0_200;
+
+component serdes_100_ext is
+generic(
+  USER_CONFIG_FILE    :  String := "serdes_100_ext.txt"
+);
+port(
+  refclkp              : in  std_logic;
+  refclkn              : in  std_logic;
+  rxrefclk             : in  std_logic;
+  refclk               : in  std_logic;
+  rxa_pclk             : out std_logic;
+  rxb_pclk             : out std_logic;
+  hdinp_0              : in  std_logic;
+  hdinn_0              : in  std_logic;
+  hdoutp_0             : out std_logic;
+  hdoutn_0             : out std_logic;
+  tclk_0               : in  std_logic;
+  rclk_0               : in  std_logic;
+  tx_rst_0             : in  std_logic;
+  rx_rst_0             : in  std_logic;
+  ref_0_sclk           : out std_logic;
+  rx_0_sclk            : out std_logic;
+  txd_0                : in  std_logic_vector(15 downto 0);
+  tx_k_0               : in  std_logic_vector(1 downto 0);
+  tx_force_disp_0      : in  std_logic_vector(1 downto 0);
+  tx_disp_sel_0        : in  std_logic_vector(1 downto 0);
+  rxd_0                : out std_logic_vector(15 downto 0);
+  rx_k_0               : out std_logic_vector(1 downto 0);
+  rx_disp_err_detect_0 : out std_logic_vector(1 downto 0);
+  rx_cv_detect_0       : out std_logic_vector(1 downto 0);
+  tx_crc_init_0        : in  std_logic_vector(1 downto 0);
+  rx_crc_eop_0         : out std_logic_vector(1 downto 0);
+  word_align_en_0      : in  std_logic;
+  mca_align_en_0       : in  std_logic;
+  felb_0               : in  std_logic;
+  lsm_en_0             : in  std_logic;
+  lsm_status_0         : out std_logic;
+  mca_resync_01        : in  std_logic;
+  quad_rst             : in  std_logic;
+  serdes_rst           : in  std_logic;
+  ref_pclk             : out std_logic
+);
+end component serdes_100_ext;
 
 -- LSM state machine signals
 signal swap_bytes             : std_logic; -- sysclk
@@ -273,8 +316,8 @@ port map(
        SD_LOS_IN         => link_error(8), -- unknown sync
        SD_TXCLK_BAD_IN   => link_error(5), -- unknown sync
        SD_RXCLK_BAD_IN   => link_error(4), -- unknown sync
-       SD_RETRY_IN       => '0', -- OK fixed 
-       SD_ALIGNMENT_IN   => rx_k_q, -- OK 
+       SD_RETRY_IN       => '0', -- OK fixed
+       SD_ALIGNMENT_IN   => rx_k_q, -- OK
        SD_CV_IN          => link_error(7 downto 6), -- unknown sync
        FULL_RESET_OUT    => quad_rst, -- sysclk sync'ed
        LANE_RESET_OUT    => lane_rst, -- sysclk sync'ed
@@ -286,6 +329,9 @@ port map(
        STAT_DEBUG        => buf_stat_debug
 );
 
+link_error(4 downto 0) <= (others => '0');
+link_error(5) <= not link_ok(0);
+link_error(8) <= '0';
 SD_TXDIS_OUT <= quad_rst;
 
 -- receive komma character status bits for LSM
@@ -340,7 +386,7 @@ gen_serdes_0_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YE
                refclkn              => SD_REFCLK_N_IN, -- not used here
                rxrefclk             => CLK, -- raw 200MHz clock
                refclk               => CLK, -- raw 200MHz clock
-               rxa_pclk             => rx_halfclk, -- clock multiplier set by data bus width
+               rxa_pclk             => open, --rx_halfclk, -- clock multiplier set by data bus width
                rxb_pclk             => open,
                hdinp_0              => SD_RXD_P_IN, -- SerDes I/O
                hdinn_0              => SD_RXD_N_IN, -- SerDes I/O
@@ -348,10 +394,10 @@ gen_serdes_0_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YE
                hdoutn_0             => SD_TXD_N_OUT, -- SerDes I/O
                tclk_0               => tx_halfclk, -- 100MHz
                rclk_0               => rx_halfclk, -- 100MHz
-               tx_rst_0             => lane_rst, -- async reset
-               rx_rst_0             => lane_rst, -- async reset
-               ref_0_sclk           => open,
-               rx_0_sclk            => open, 
+               tx_rst_0             => '0', --JM101206 lane_rst, -- async reset
+               rx_rst_0             => '0', --JM101206 lane_rst, -- async reset  --reset when sd_los=0 and disp_err=1 or cv=1
+               ref_0_sclk           => tx_halfclk,
+               rx_0_sclk            => rx_halfclk,
                txd_0                => tx_data,
                tx_k_0               => tx_k,
                tx_force_disp_0      => b"00", -- BUGBUG
@@ -369,11 +415,51 @@ gen_serdes_0_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YE
                lsm_status_0         => link_ok(0), -- link synchronisation successfull
                mca_resync_01        => '0', -- not needed
                quad_rst             => '0', -- hands off - kills registers!
-               serdes_rst           => quad_rst, -- unknown if will work
-               ref_pclk             => tx_halfclk -- clock multiplier set by data bus width
+               serdes_rst           => '0', --JM101203 quad_rst, -- unknown if will work
+               ref_pclk             => open --tx_halfclk -- clock multiplier set by data bus width
        );
 end generate;
 
+gen_serdes_0_100_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES and USE_200_MHZ = c_NO generate
+  THE_SERDES: serdes_100_ext
+  port map(
+    refclkp              => SD_REFCLK_P_IN, -- not used here
+    refclkn              => SD_REFCLK_N_IN, -- not used here
+    rxrefclk             => CLK, -- raw 200MHz clock
+    refclk               => CLK, -- raw 200MHz clock
+    rxa_pclk             => open, --rx_halfclk, -- clock multiplier set by data bus width
+    rxb_pclk             => open,
+    hdinp_0              => SD_RXD_P_IN, -- SerDes I/O
+    hdinn_0              => SD_RXD_N_IN, -- SerDes I/O
+    hdoutp_0             => SD_TXD_P_OUT, -- SerDes I/O
+    hdoutn_0             => SD_TXD_N_OUT, -- SerDes I/O
+    tclk_0               => tx_halfclk, -- 100MHz
+    rclk_0               => rx_halfclk, -- 100MHz
+    tx_rst_0             => '0', --JM101206 lane_rst, -- async reset
+    rx_rst_0             => lane_rst, -- async reset  --SM: reset when sd_los=0 and disp_err=1 or cv=1
+    ref_0_sclk           => tx_halfclk,
+    rx_0_sclk            => rx_halfclk,
+    txd_0                => tx_data,
+    tx_k_0               => tx_k,
+    tx_force_disp_0      => b"00", -- BUGBUG
+    tx_disp_sel_0        => b"00", -- BUGBUG
+    rxd_0                => rx_data,
+    rx_k_0               => rx_k,
+    rx_disp_err_detect_0 => open,
+    rx_cv_detect_0       => link_error(7 downto 6),
+    tx_crc_init_0        => b"00", -- CRC init (not needed)
+    rx_crc_eop_0         => open, -- (not needed)
+    word_align_en_0      => '1', -- word alignment
+    mca_align_en_0       => '0', -- (not needed)
+    felb_0               => '0', -- far end loopback disable
+    lsm_en_0             => '1', -- enable LinkStateMachine
+    lsm_status_0         => link_ok(0), -- link synchronisation successfull
+    mca_resync_01        => '0', -- not needed
+    quad_rst             => '0', -- hands off - kills registers!
+    serdes_rst           => '0', --JM101203 quad_rst, -- unknown if will work
+    ref_pclk             => open --tx_halfclk -- clock multiplier set by data bus width
+  );
+end generate;
 
 -------------------------------------------------------------------------
 -------------------------------------------------------------------------
@@ -401,7 +487,7 @@ THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
 generic map(
        USE_STATUS_FLAGS => c_NO
 )
-port map( 
+port map(
        fifo_gsr_in        => fifo_rx_reset, -- async reset
        read_clock_in      => SYSCLK,
        read_enable_in     => fifo_rx_rd_en, -- OK
@@ -474,7 +560,7 @@ THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
 generic map(
        USE_STATUS_FLAGS => c_NO
 )
-port map( 
+port map(
        fifo_gsr_in       => fifo_tx_reset, -- async signal, does not matter
        read_clock_in     => tx_halfclk,
        read_enable_in    => fifo_tx_rd_en, -- OK
@@ -545,19 +631,19 @@ THE_LED_PROC: process( SYSCLK )
 begin
        if( rising_edge(SYSCLK) ) then
                led_counter <= led_counter + 1;
-               
+
                if   ( buf_med_dataready_out = '1' ) then
                        rx_led <= '1';
                elsif( led_counter = 0 ) then
                        rx_led <= '0';
                end if;
-               
+
                if   ( tx_k(0) = '0' ) then
                        tx_led <= '1';
                elsif( led_counter = 0 ) then
                        tx_led <= '0';
                end if;
-       
+
        end if;
 end process THE_LED_PROC;
 
@@ -572,7 +658,8 @@ stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
 -- Debug output
 stat_debug(15 downto 0)  <= rx_data;
 stat_debug(17 downto 16) <= rx_k;
-stat_debug(19 downto 18) <= (others => '0');
+stat_debug(18)           <= link_ok(0);
+stat_debug(19)           <= quad_rst;
 stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
 stat_debug(24)           <= fifo_rx_rd_en;
 stat_debug(25)           <= fifo_rx_wr_en;
@@ -581,10 +668,13 @@ stat_debug(27)           <= fifo_rx_empty;
 stat_debug(28)           <= fifo_rx_full;
 stat_debug(29)           <= last_rx(8);
 stat_debug(30)           <= rx_allow_delay;
-stat_debug(41 downto 31) <= (others => '0');
+stat_debug(31)           <= lane_rst;
+stat_debug(41 downto 32) <= (others => '0');
 stat_debug(42)           <= sysclk;
-stat_debug(43)           <= sysclk;
-stat_debug(59 downto 44) <= (others => '0');
+stat_debug(43)           <= tx_halfclk;
+stat_debug(44)           <= rx_halfclk;
+stat_debug(46 downto 45) <= tx_k;
+stat_debug(59 downto 47) <= (others => '0');
 stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
 
 end architecture;
\ No newline at end of file

diff --git a/pinout/cts_fpga1.lpf b/pinout/cts_fpga1.lpf
index 60782a6fe7fea23d6b224f24cbc8c57c2fdb0e26..c9aef2b0cd1ed03387616e52cda3e0da0e06cb61 100644 (file)
--- a/pinout/cts_fpga1.lpf
+++ b/pinout/cts_fpga1.lpf
@@ -77,7 +77,7 @@ LOCATE COMP  "ADO_TTL_44"       SITE "AM9";
 LOCATE COMP  "ADO_TTL_45"        SITE "AM8";
 LOCATE COMP  "ADO_TTL_46"        SITE "AF13";
 DEFINE PORT GROUP "ADOTTL_group" "ADO_TTL*" ;
-IOBUF GROUP "ADOTTL_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16;  #should be LVTTL33
+IOBUF GROUP "ADOTTL_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16;
 
 LOCATE COMP  "FS_PE_5"    SITE "AE13";
 LOCATE COMP  "FS_PE_6"    SITE "AL9";
@@ -87,45 +87,45 @@ LOCATE COMP  "FS_PE_9"    SITE "AK9";
 LOCATE COMP  "FS_PE_10"   SITE "AJ9";
 LOCATE COMP  "FS_PE_11"   SITE "AG10";
 DEFINE PORT GROUP "FSPE_group" "FS_PE*" ;
-IOBUF GROUP "FSPE_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16;  #should be LVTTL33
+IOBUF GROUP "FSPE_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16;
 
 #################################################################
 # Debug
 #################################################################
-# LOCATE COMP  "TEST_LINE_0"    SITE "AL6";
-# LOCATE COMP  "TEST_LINE_1"    SITE "AL5";
-# LOCATE COMP  "TEST_LINE_2"    SITE "AG7";
-# LOCATE COMP  "TEST_LINE_3"    SITE "AG8";
-# LOCATE COMP  "TEST_LINE_4"    SITE "AK6";
-# LOCATE COMP  "TEST_LINE_5"    SITE "AJ6";
-# LOCATE COMP  "TEST_LINE_6"    SITE "AF10";
-# LOCATE COMP  "TEST_LINE_7"    SITE "AE11";
-# LOCATE COMP  "TEST_LINE_8"    SITE "AM4";
-# LOCATE COMP  "TEST_LINE_9"    SITE "AM3";
-# LOCATE COMP  "TEST_LINE_10"   SITE "AH5";
-# LOCATE COMP  "TEST_LINE_11"   SITE "AH4";
-# LOCATE COMP  "TEST_LINE_12"   SITE "AK5";
-# LOCATE COMP  "TEST_LINE_13"   SITE "AJ5";
-# LOCATE COMP  "TEST_LINE_14"   SITE "AF8";
-# LOCATE COMP  "TEST_LINE_15"   SITE "AF7";
-# LOCATE COMP  "TEST_LINE_16"   SITE "AL4";
-# LOCATE COMP  "TEST_LINE_17"   SITE "AL3";
-# LOCATE COMP  "TEST_LINE_18"   SITE "AG5";
-# LOCATE COMP  "TEST_LINE_19"   SITE "AF6";
-# LOCATE COMP  "TEST_LINE_20"   SITE "AK3";
-# LOCATE COMP  "TEST_LINE_21"   SITE "AJ3";
-# LOCATE COMP  "TEST_LINE_22"   SITE "AE10";
-# LOCATE COMP  "TEST_LINE_23"   SITE "AD10";
-# LOCATE COMP  "TEST_LINE_24"   SITE "AL2";
-# LOCATE COMP  "TEST_LINE_25"   SITE "AK2";
-# LOCATE COMP  "TEST_LINE_26"   SITE "AE9";
-# LOCATE COMP  "TEST_LINE_27"   SITE "AE8";
-# LOCATE COMP  "TEST_LINE_28"   SITE "AJ1";
-# LOCATE COMP  "TEST_LINE_29"   SITE "AK1";
-# LOCATE COMP  "TEST_LINE_30"   SITE "AJ2";
-# LOCATE COMP  "TEST_LINE_31"   SITE "AH3";
-# DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-# IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=16;
+LOCATE COMP  "TEST_LINE_0"    SITE "AL6";
+LOCATE COMP  "TEST_LINE_1"    SITE "AL5";
+LOCATE COMP  "TEST_LINE_2"    SITE "AG7";
+LOCATE COMP  "TEST_LINE_3"    SITE "AG8";
+LOCATE COMP  "TEST_LINE_4"    SITE "AK6";
+LOCATE COMP  "TEST_LINE_5"    SITE "AJ6";
+LOCATE COMP  "TEST_LINE_6"    SITE "AF10";
+LOCATE COMP  "TEST_LINE_7"    SITE "AE11";
+LOCATE COMP  "TEST_LINE_8"    SITE "AM4";
+LOCATE COMP  "TEST_LINE_9"    SITE "AM3";
+LOCATE COMP  "TEST_LINE_10"   SITE "AH5";
+LOCATE COMP  "TEST_LINE_11"   SITE "AH4";
+LOCATE COMP  "TEST_LINE_12"   SITE "AK5";
+LOCATE COMP  "TEST_LINE_13"   SITE "AJ5";
+LOCATE COMP  "TEST_LINE_14"   SITE "AF8";
+LOCATE COMP  "TEST_LINE_15"   SITE "AF7";
+LOCATE COMP  "TEST_LINE_16"   SITE "AL4";
+LOCATE COMP  "TEST_LINE_17"   SITE "AL3";
+LOCATE COMP  "TEST_LINE_18"   SITE "AG5";
+LOCATE COMP  "TEST_LINE_19"   SITE "AF6";
+LOCATE COMP  "TEST_LINE_20"   SITE "AK3";
+LOCATE COMP  "TEST_LINE_21"   SITE "AJ3";
+LOCATE COMP  "TEST_LINE_22"   SITE "AE10";
+LOCATE COMP  "TEST_LINE_23"   SITE "AD10";
+LOCATE COMP  "TEST_LINE_24"   SITE "AL2";
+LOCATE COMP  "TEST_LINE_25"   SITE "AK2";
+LOCATE COMP  "TEST_LINE_26"   SITE "AE9";
+LOCATE COMP  "TEST_LINE_27"   SITE "AE8";
+LOCATE COMP  "TEST_LINE_28"   SITE "AJ1";
+LOCATE COMP  "TEST_LINE_29"   SITE "AK1";
+LOCATE COMP  "TEST_LINE_30"   SITE "AJ2";
+LOCATE COMP  "TEST_LINE_31"   SITE "AH3";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=16;
 
 #################################################################
 # To second FPGA
@@ -243,7 +243,7 @@ LOCATE COMP  "RS2_1"   SITE "AF11";
 LOCATE COMP  "RS2_2"   SITE "AD12";
 LOCATE COMP  "RS2_3"   SITE "AE12";
 DEFINE PORT GROUP "RS_group" "RS*" ;
-IOBUF GROUP "RS_group"       IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=16; #should be LVTTL33
+IOBUF GROUP "RS_group"       IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;
 
 #################################################################
 # SFP