#define SHORT_TRANSFER 0x0100
/* Other */
-#define MAX_TIME_OUT 500
+#define MAX_TIME_OUT 1500000
#define DATA_BUFFER_SIZE 8192
unsigned int dataCtr = 0;
int packageCtr = -1;
unsigned int endPointCtr = 0;
-
+
unsigned int timeout = 0;
/* Determin FIFO-Address */
do {
read32_from_FPGA(fifoBuffer, tmp);
} while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIME_OUT));
-
+
if (timeout >= MAX_TIME_OUT) {
trb_fifo_flush(channel);
trb_errno = TRB_FIFO_TIMEOUT;
}
}
}
-
+
/* Copy StatusBits and Sequenze of TerminationPackage */
trb_term.status_common = package.F2;
trb_term.status_channel = package.F1;