*** empty log message ***

diff --git a/constraints_pexor.lpf b/constraints_pexor.lpf
index dc15853c5ef74b9f3fc0ef2fbd57bdb89cb05094..e51feffceb3a4c333b921590e6762a95d8e41283 100644 (file)
--- a/constraints_pexor.lpf
+++ b/constraints_pexor.lpf
@@ -3,6 +3,8 @@ BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
 BLOCK RD_DURING_WR_PATHS ;
 
+SYSCONFIG MCCLK_FREQ=33 ;
+
 #########################################
 # Clock Constraints
 #########################################

diff --git a/design/cores/fifo_dc_32x1024.ipx b/design/cores/fifo_dc_32x1024.ipx
new file mode 100644 (file)
index 0000000..437abfb
--- /dev/null
+++ b/design/cores/fifo_dc_32x1024.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="fifo_dc_32x1024" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 06 03 15:46:32.689" version="5.4" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+               <File name="fifo_dc_32x1024.lpc" type="lpc" modified="2011 06 03 15:46:26.000"/>
+               <File name="fifo_dc_32x1024.vhd" type="top_level_vhdl" modified="2011 06 03 15:46:26.000"/>
+               <File name="fifo_dc_32x1024_tmpl.vhd" type="template_vhdl" modified="2011 06 03 15:46:26.000"/>
+               <File name="tb_fifo_dc_32x1024_tmpl.vhd" type="testbench_vhdl" modified="2011 06 03 15:46:26.000"/>
+  </Package>
+</DiamondModule>

diff --git a/design/cores/fifo_dc_32x1024.lpc b/design/cores/fifo_dc_32x1024.lpc
new file mode 100644 (file)
index 0000000..4c78bed
--- /dev/null
+++ b/design/cores/fifo_dc_32x1024.lpc
@@ -0,0 +1,48 @@
+[Device]
+Family=latticescm
+PartType=LFSCM3GA115EP1
+PartName=LFSCM3GA115EP1-5FC1152C
+SpeedGrade=5
+Package=FCBGA1152
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.4
+ModuleName=fifo_dc_32x1024
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=06/03/2011
+Time=15:46:26
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=1024
+RWidth=32
+WDepth=1024
+WWidth=32
+regout=0
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=1015
+PfDeassert=506
+Reset=Async
+RDataCount=0
+WDataCount=0
+EnECC=0

diff --git a/design/cores/fifo_dc_32x1024.vhd b/design/cores/fifo_dc_32x1024.vhd
new file mode 100644 (file)
index 0000000..ede62ed
--- /dev/null
+++ b/design/cores/fifo_dc_32x1024.vhd
@@ -0,0 +1,225 @@
+-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517)
+-- Module  Version: 5.4
+--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_dc_32x1024 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 32 -rwidth 32 -no_enable -pe 10 -pf 1015 -e 
+
+-- Fri Jun  3 15:46:26 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_dc_32x1024 is
+    port (
+        Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostEmpty: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_dc_32x1024;
+
+architecture Structure of fifo_dc_32x1024 is
+
+    -- internal signal declarations
+    signal scuba_vhi: std_logic;
+    signal Empty_int: std_logic;
+    signal Full_int: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component FIFO16KA
+    -- synopsys translate_off
+        generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); 
+                FULLPOINTER : in std_logic_vector(14 downto 0); 
+                AFPOINTER1 : in std_logic_vector(14 downto 0); 
+                AEPOINTER1 : in std_logic_vector(14 downto 0); 
+                AFPOINTER : in std_logic_vector(14 downto 0); 
+                AEPOINTER : in std_logic_vector(14 downto 0); 
+                CSDECODE_R : in std_logic_vector(1 downto 0); 
+                CSDECODE_W : in std_logic_vector(1 downto 0); 
+                RESETMODE : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+    -- synopsys translate_on
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            FULLI: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; EMPTYI: in  std_logic; 
+            CSR0: in  std_logic; CSR1: in  std_logic; WE: in  std_logic; 
+            RE: in  std_logic; CLKW: in  std_logic; CLKR: in  std_logic; 
+            RST: in  std_logic; RPRST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic; 
+            EF: out  std_logic; AEF: out  std_logic; AFF: out  std_logic; 
+            FF: out  std_logic);
+    end component;
+    attribute FULLPOINTER1 : string; 
+    attribute FULLPOINTER : string; 
+    attribute AFPOINTER1 : string; 
+    attribute AFPOINTER : string; 
+    attribute AEPOINTER1 : string; 
+    attribute AEPOINTER : string; 
+    attribute RESETMODE : string; 
+    attribute REGMODE : string; 
+    attribute CSDECODE_R : string; 
+    attribute CSDECODE_W : string; 
+    attribute DATA_WIDTH_R : string; 
+    attribute DATA_WIDTH_W : string; 
+    attribute FULLPOINTER1 of fifo_dc_32x1024_0_1 : label is "0b011111111100001";
+    attribute FULLPOINTER of fifo_dc_32x1024_0_1 : label is "0b011111111110001";
+    attribute AFPOINTER1 of fifo_dc_32x1024_0_1 : label is "0b011111101010001";
+    attribute AFPOINTER of fifo_dc_32x1024_0_1 : label is "0b011111101100001";
+    attribute AEPOINTER1 of fifo_dc_32x1024_0_1 : label is "0b000000010111111";
+    attribute AEPOINTER of fifo_dc_32x1024_0_1 : label is "0b000000010101111";
+    attribute RESETMODE of fifo_dc_32x1024_0_1 : label is "ASYNC";
+    attribute REGMODE of fifo_dc_32x1024_0_1 : label is "NOREG";
+    attribute CSDECODE_R of fifo_dc_32x1024_0_1 : label is "0b11";
+    attribute CSDECODE_W of fifo_dc_32x1024_0_1 : label is "0b11";
+    attribute DATA_WIDTH_R of fifo_dc_32x1024_0_1 : label is "18";
+    attribute DATA_WIDTH_W of fifo_dc_32x1024_0_1 : label is "18";
+    attribute FULLPOINTER1 of fifo_dc_32x1024_1_0 : label is "0b000000000000000";
+    attribute FULLPOINTER of fifo_dc_32x1024_1_0 : label is "0b111111111111111";
+    attribute AFPOINTER1 of fifo_dc_32x1024_1_0 : label is "0b000000000000000";
+    attribute AFPOINTER of fifo_dc_32x1024_1_0 : label is "0b111111111111111";
+    attribute AEPOINTER1 of fifo_dc_32x1024_1_0 : label is "0b000000000000000";
+    attribute AEPOINTER of fifo_dc_32x1024_1_0 : label is "0b111111111111111";
+    attribute RESETMODE of fifo_dc_32x1024_1_0 : label is "ASYNC";
+    attribute REGMODE of fifo_dc_32x1024_1_0 : label is "NOREG";
+    attribute CSDECODE_R of fifo_dc_32x1024_1_0 : label is "0b11";
+    attribute CSDECODE_W of fifo_dc_32x1024_1_0 : label is "0b11";
+    attribute DATA_WIDTH_R of fifo_dc_32x1024_1_0 : label is "18";
+    attribute DATA_WIDTH_W of fifo_dc_32x1024_1_0 : label is "18";
+    attribute syn_keep : boolean;
+
+begin
+    -- component instantiation statements
+    fifo_dc_32x1024_0_1: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "011111111100001", FULLPOINTER=> "011111111110001", 
+        AFPOINTER1=> "011111101010001", AFPOINTER=> "011111101100001", 
+        AEPOINTER1=> "000000010111111", AEPOINTER=> "000000010101111", 
+        RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  18, DATA_WIDTH_W=>  18)
+        -- synopsys translate_on
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo, 
+            DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo, 
+            DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo, 
+            DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, 
+            DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, 
+            DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, 
+            FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, 
+            EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, 
+            WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, 
+            RPRST=>RPReset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), 
+            DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), 
+            DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), 
+            DO13=>Q(13), DO14=>Q(14), DO15=>Q(15), DO16=>Q(16), 
+            DO17=>Q(17), DO18=>open, DO19=>open, DO20=>open, DO21=>open, 
+            DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open, 
+            DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open, 
+            DO32=>open, DO33=>open, DO34=>open, DO35=>open, 
+            EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull, 
+            FF=>Full_int);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    fifo_dc_32x1024_1_0: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111", 
+        AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111", 
+        AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111", 
+        RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  18, DATA_WIDTH_W=>  18)
+        -- synopsys translate_on
+        port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20), 
+            DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24), 
+            DI7=>Data(25), DI8=>Data(26), DI9=>Data(27), DI10=>Data(28), 
+            DI11=>Data(29), DI12=>Data(30), DI13=>Data(31), 
+            DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo, 
+            DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo, 
+            DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo, 
+            DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo, 
+            DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo, 
+            DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo, 
+            DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, 
+            DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi, 
+            CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock, 
+            CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>Q(18), 
+            DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), 
+            DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), 
+            DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>open, 
+            DO15=>open, DO16=>open, DO17=>open, DO18=>open, DO19=>open, 
+            DO20=>open, DO21=>open, DO22=>open, DO23=>open, DO24=>open, 
+            DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open, 
+            DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open, 
+            DO35=>open, EF=>open, AEF=>open, AFF=>open, FF=>open);
+
+    Empty <= Empty_int;
+    Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_dc_32x1024 is
+    for Structure
+        for all:VHI use entity SCM.VHI(V); end for;
+        for all:VLO use entity SCM.VLO(V); end for;
+        for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on

diff --git a/pcie_components.vhd b/pcie_components.vhd
index 546aab1b3a66e9a0f5841f1fb8ab36e4e516636e..91593e26eb5de7604f2ee322dc3ea573b40d76aa 100644 (file)
--- a/pcie_components.vhd
+++ b/pcie_components.vhd
@@ -6,6 +6,15 @@ use work.trb_net_std.all;
 
 package pcie_components is
 
+component fifo_dc_32x1024
+    port (Data: in  std_logic_vector(31 downto 0);
+        WrClock: in  std_logic; RdClock: in  std_logic;
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic;
+        RPReset: in  std_logic; Q: out  std_logic_vector(31 downto 0);
+        Empty: out  std_logic; Full: out  std_logic;
+        AlmostEmpty: out  std_logic; AlmostFull: out  std_logic);
+end component;
+
 component pci_core is
   port(
     CLK_PCIE_IN      : in  std_logic;
@@ -131,6 +140,10 @@ component dma_core is
     RX_DWEN_IN           : in  std_logic;
     RX_DATA_IN           : in  std_logic_vector(63 downto 0);
 
+    DEBUG_FIFO_DATA_OUT  : out std_logic_vector(63 downto 0);
+    DEBUG_FIFO_EMPTY_OUT : out std_logic_vector(1 downto 0);
+    DEBUG_FIFO_READ_IN   : in  std_logic_vector(1 downto 0);
+    
     STATUS_REG_OUT       : out std_logic_vector(159 downto 0);
     DEBUG_OUT            : out std_logic_vector(31 downto 0)
 

diff --git a/pexor.prj b/pexor.prj
index dbbee051724816f28cf0364057a3910ae15bcc34..523f55a9aad22a1a83304e76709c4746647ef854 100644 (file)
--- a/pexor.prj
+++ b/pexor.prj
@@ -57,6 +57,7 @@ add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
 add_file -vhdl -lib work "../trbnet/trb_net16_hub_base.vhd"
 add_file -vhdl -lib work "../trbnet/trb_net16_hub_logic.vhd"
 add_file -vhdl -lib work "../trbnet/trb_net16_hub_ipu_logic.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_hub_streaming_port_sctrl.vhd"
 # add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
 add_file -vhdl -lib work "../trbnet/special/trb_net_bridge_pcie_endpoint_hub.vhd"
 # add_file -vhdl -lib work "../trbnet/special/trb_net_bridge_pcie_endpoint.vhd"
@@ -110,6 +111,7 @@ add_file -vhdl -lib work "design/cores/fifo_32to64x512_dualclock.vhd"
 add_file -vhdl -lib work "design/cores/fifo_16x512_dualclock.vhd"
 add_file -vhdl -lib work "design/cores/fifo_9x512_dualclock.vhd"
 add_file -vhdl -lib work "design/cores/fifo_8x512_dualclock.vhd"
+add_file -vhdl -lib work "design/cores/fifo_dc_32x1024.vhd"
 add_file -vhdl -lib work "design/pci_core.vhd"
 add_file -verilog "vcode/pci_exp_ddefines.v"
 add_file -verilog "vcode/pci_exp_params.v"