added new control reg for SPI fifo

diff --git a/xml-db/database/CbController.xml b/xml-db/database/CbController.xml
index 060ede84c2ac4d3f6a19ff827af7b069da728613..f88ad525db5c30c8d8e10fa81e76cf0fa2c05531 100644 (file)
--- a/xml-db/database/CbController.xml
+++ b/xml-db/database/CbController.xml
@@ -94,6 +94,12 @@
               start="0" bits="32"  mode="r"  purpose="status"  format="integer" rate="1">
       </field>
     </register>
+    <register  name="SpiFifoSelect"
+              address="0053" purpose="config" mode="rw" >
+      <description>Select a SPI channel to monitor in the Fifo</description>
+      <field name="SpiFifoSelect" start="0" bits="8" format="hex" >
+      </field>
+    </register>
     <register  name="UcReset"
               address="0060" purpose="config" mode="rw" >
       <description>Brings the uC to reset, when set Lo.</description>