--- /dev/null
+\begin{itemize}
+\item The SFPs are missing LEDs - so no information about link status
+\item The outputs of the CLK5410 chips are not independent: Two outputs share some settings - regarding this the connection is far from optimal, e.g. the clock to the serdes from FPGA1 is not independent from clock to GPLL input on FPGA4 etc.
+\item SFP cages could have been distributed differently. Now, all TrbNet links (SFP1-4) are on one side and all GbE capable links on the other two (SFP5-8). Usually only few ports are in use, so a mix would be better.
+\item TRB\_TO\_ADDON\_CLOCK is located on a port that does not support LVDS output
+\item All pins connected to a DLL and PLL are Input only and can not be used as outputs! On the central FPGA, these are pins FS\_PE 4,5,7,8 and ADO\_TTL 23,26,30,46
+\item SPARE\_LINE between FPGA and AddOn-Connector are connected to Feedback input of PLL, not the normal input to PLL
+\item On peripheral FPGA lines 8 and 9 of DQUR0 are input only - they are removed from the LPF for now.
+\item Both GPLL inputs to peripheral FPGA are not usable - they are connected to Feedback input instead of normal input of PLL. They can still be used through normal routing, but source synchronous operation is not possible.
+\item The JTAG Connector is wrong. The line labeled TDI is TDO and vice versa.
+\item The 48V-to-6V converter gets quite hot without air-flow. When AddOns are mounted, the fan must be installed on the short side of the TRB, not on the long one.
+\end{itemize}
+
--- /dev/null
+\documentclass[11pt,a4paper,twoside]{scrartcl} %twoside
+
+%Einstellungen der Seitenr?nder
+\usepackage[left=3.5cm,right=3cm,top=2.5cm,bottom=2.5cm,includeheadfoot]{geometry}
+
+\usepackage[utf8]{inputenc}
+\usepackage{amsfonts}
+\usepackage[american]{babel}
+\usepackage[T1]{fontenc}
+\usepackage[pdftex]{graphicx}
+\usepackage{pslatex}
+\usepackage{xcolor}
+\usepackage{array}
+\usepackage{rotating}
+\usepackage{multirow}
+\usepackage{tabularx}
+\usepackage{url}
+\linespread{1.15}
+\usepackage{booktabs}
+\usepackage{longtable}
+\usepackage{ltxtable}
+\usepackage{upgreek}
+\usepackage{listings}
+\usepackage{scrtime}
+\usepackage{lscape}
+\usepackage{enumerate}
+
+
+\definecolor{darkblue}{rgb}{.1,.1,.6}
+\usepackage[linkbordercolor={0 0 0},
+ pdfborder={0 0 0},
+ bookmarks,
+ citecolor=blue,
+ linkcolor=darkblue,
+ colorlinks=true,
+ urlcolor=darkblue]{hyperref}
+\usepackage{cite}
+
+
+\newcolumntype{C}{>{\centering\arraybackslash}X}
+
+\usepackage{fancyhdr}
+\pagestyle{headings}%{fancy}
+\fancyhf{}
+\fancyhead[R]{\nouppercase{\leftmark}}
+\renewcommand{\headrulewidth}{0.5pt}
+\fancyfoot[C]{\thepage}
+%\renewcommand{\footrulewidth}{0}
+%\usepackage[sort,square]{natbib}
+%\usepackage{mathptmx}
+%\usepackage{pslatex}
+
+\title{A Users Guide\\to the TRB3 \\and FPGA-TDC Based Platforms}
+\date{\today ~-~\thistime}
+\author{Grzegorz Korcyl, Ludwig Maier, Jan Michel, Marek Palka, \\Pawel Strzempek, Michael Traxler, Cahit Ugur}
+
+
+\newcommand{\filename}[1]{\textit{#1}}
+\newcommand{\portname}[1]{\textsc{#1}}
+\newcommand{\genericname}[1]{\textsc{#1}}
+\newcommand{\constname}[1]{\textsc{#1}}
+\newcommand{\netname}[1]{\textsc{#1}}
+\newcommand{\cmdname}[1]{\texttt{#1}}
+\bibliographystyle{alpha}
+
+\usepackage{remreset}
+\makeatletter\@removefromreset{footnote}{chapter}\makeatother
+
+% \lstset{ language = VHDL,
+% numbers =left,
+% stepnumber =1,
+% frame =single,
+% captionpos=b,
+% breaklines=true
+% basicstyle=\small,
+% identifierstyle=\small,
+% stringstyle=\small,
+% numberstyle=\small,
+% fontadjust=false}
+
+\begin{document}
+\newcounter{line}
+\newcounter{ct}
+
+\maketitle
+\clearpage
+\tableofcontents
+
+
+\cleardoublepage
+\part{Hardware}
+ \section{Measurements}
+ \subsection{FPGA I/O Performance}
+
+ \section{TRB3 Platform}
+ \subsection{Known Bugs and Limitations}
+ \input{Trb3KnownBugs}
+ \subsection{Clock and Trigger Distribution}
+ \input{Trb3ClockTriggerDistribution}
+
+ \clearpage
+ \section{AddOns}
+ \subsection{TDC AddOn}
+ \input{TdcAddOn}
+ \subsection{Multi-Test-AddOn}
+ \input{MultiTestAddOn}
+ \subsection{Hub AddOn}
+ \input{SfpAddOn}
+ \subsection{MVD AddOn}
+ \input{MvdAddOn}
+ \cleardoublepage
+
+\part{Design Components}
+ \input{DesignComponents}
+ \clearpage
+ \section{TDC}
+ \subsection{Features}
+ \input{TdcFeatures}
+ \subsection{Building Blocks}
+ \input{TdcBuildingBlocks}
+ \subsection{Data Format}
+ \input{TdcDataFormat}
+ \subsection{Slow Control Registers}
+ \input{TdcSlowControl}
+
+ \clearpage
+ \section{GbE Data Read-out}
+ \subsection{Building Blocks}
+ \subsection{Slow Control Registers}
+
+ \clearpage
+ \section{GbE Slow-Control}
+ \subsection{Building Blocks}
+ \subsection{Slow Control Registers}
+
+ \clearpage
+ \section{uCTS}
+ \subsection{Features}
+ \subsection{Building Blocks}
+ \subsection{Slow Control Registers}
+ \cleardoublepage
+
+
+\part{Experimental Setups and Configurations}
+
+
+
+
+ \cleardoublepage
+
+\bibliography{biblio}
+
+\end{document}