ENCODER_START_NUMBER : out std_logic_vector(23 downto 0) := (others => '0');
ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0) := (others => '0');
FIFO_WRITE_NUMBER : out std_logic_vector(23 downto 0) := (others => '0');
---
+ CHANNEL_ENABLE_IN : in std_logic;
+
Channel_200_DEBUG_OUT : out std_logic_vector(31 downto 0);
Channel_DEBUG_OUT : out std_logic_vector(31 downto 0)
);
ENCODER_START_OUT => encoder_start,
ENCODER_FINISHED_OUT => encoder_finished,
FIFO_WRITE_OUT => fifo_write,
+ CHANNEL_ENABLE_IN => CHANNEL_ENABLE_IN,
CHANNEL_200_DEBUG_OUT => channel_200_debug);
Buffer_128 : if RING_BUFFER_SIZE = 3 or RING_BUFFER_SIZE = 7 generate
ENCODER_START_OUT : out std_logic;
ENCODER_FINISHED_OUT : out std_logic;
FIFO_WRITE_OUT : out std_logic;
+ CHANNEL_ENABLE_IN : in std_logic;
CHANNEL_200_DEBUG_OUT : out std_logic_vector(31 downto 0)
);
rd_ptr <= rd_ptr + 1;
end if;
end if;
+ if CHANNEL_ENABLE_IN = '0' then
+ rd_ptr <= 0;
+ wr_ptr <= 0;
+ end if;
end if;
end process EdgeTypeCapture;
end generate isChannelEdge;
The_Stretcher : entity work.Stretcher
generic map (
CHANNEL => CHANNEL_NUMBER-1,
- DEPTH => 4+(FPGA_TYPE/4)) --4 for ECP3, 5 for ECP5
+ DEPTH => 4+1*(FPGA_TYPE/4)) --3 for ECP3, 5 for ECP5
port map (
PULSE_IN => edge_falling(CHANNEL_NUMBER-1 downto 1),
PULSE_OUT => edge_falling_d(CHANNEL_NUMBER-1 downto 1));
end generate GEN_HitBlock;
GEN_hit_mux : for i in 1 to CHANNEL_NUMBER-1 generate
+ signal real_enable : std_logic_vector(CHANNEL_NUMBER downto 0);
+ begin
+ real_enable(i) <= ch_en(i);-- or calibration_on;
hit_mux_ch : hit_mux
port map (
- CH_EN_IN => ch_en(i),
+ CH_EN_IN => real_enable(i),
CALIBRATION_EN_IN => '0',
HIT_CALIBRATION_IN => '0',
HIT_PHYSICAL_IN => hit_latch(i),
ENCODER_START_NUMBER => ch_encoder_start_number(0),
ENCODER_FINISHED_NUMBER => ch_encoder_finished_number(0),
FIFO_WRITE_NUMBER => ch_fifo_write_number(0),
+ CHANNEL_ENABLE_IN => '1',
Channel_200_DEBUG_OUT => ch_200_debug(0),
- Channel_DEBUG_OUT => ch_debug(0));
+ Channel_DEBUG_OUT => ch_debug(0)
+ );
-- TDC Channels
GEN_Channels : for i in 1 to CHANNEL_NUMBER-1 generate
ENCODER_START_NUMBER => ch_encoder_start_number(i),
ENCODER_FINISHED_NUMBER => ch_encoder_finished_number(i),
FIFO_WRITE_NUMBER => ch_fifo_write_number(i),
+ CHANNEL_ENABLE_IN => ch_en(i),
Channel_200_DEBUG_OUT => ch_200_debug(i),
- Channel_DEBUG_OUT => ch_debug(i));
+ Channel_DEBUG_OUT => ch_debug(i)
+ );
end generate GEN_Channels;
-- ch_data(CHANNEL_NUMBER) <= (others => '1');
ENCODER_START_NUMBER : out std_logic_vector(23 downto 0);
ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0);
FIFO_WRITE_NUMBER : out std_logic_vector(23 downto 0);
+ CHANNEL_ENABLE_IN : in std_logic;
Channel_200_DEBUG_OUT : out std_logic_vector(31 downto 0);
Channel_DEBUG_OUT : out std_logic_vector(31 downto 0));
end component;
ENCODER_START_OUT : out std_logic;
ENCODER_FINISHED_OUT : out std_logic;
FIFO_WRITE_OUT : out std_logic;
+ CHANNEL_ENABLE_IN : in std_logic;
CHANNEL_200_DEBUG_OUT : out std_logic_vector(31 downto 0));
end component Channel_200;
-tdc_constraints_64_orig.lpf
\ No newline at end of file
+tdc_constraints_64_rearranged.lpf
\ No newline at end of file
UGROUP "Stretcher_A" BBOX 6 8\r
BLKNAME THE_TDC/gen_double_withStretcher.The_Stretcher/Stretcher_A_1\r
;\r
-LOCATE UGROUP "Stretcher_A" SITE "R2C174D";\r
+LOCATE UGROUP "Stretcher_A" SITE "R2C154D";\r
\r
UGROUP "Stretcher_B" BBOX 6 8\r
BLKNAME THE_TDC/gen_double_withStretcher.The_Stretcher/Stretcher_B_1\r
;\r
-LOCATE UGROUP "Stretcher_B" SITE "R2C2D";\r
+LOCATE UGROUP "Stretcher_B" SITE "R2C22D";\r
\r
\r
--Bit 2/3 output, serial link TX active
--Connection to ADA AddOn
-- SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only
- INP : in std_logic_vector(63 downto 0);
+ ADDON_TEST : out std_logic_vector(4 downto 1);
+ ADDON_TEMP : inout std_logic_vector(2 downto 1);
+ INP : in std_logic_vector(63 downto 0);
--DAC
DAC_IN_L_SDI : in std_logic;
DAC_OUT_L_SDO : out std_logic;
--Slow Control channel
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal ctrlbus_rx, bustdc_rx, bustools_rx, bus_master_out, bustrigger_rx : CTRLBUS_RX;
- signal ctrlbus_tx, bustdc_tx, bustools_tx, bus_master_in, bustrigger_tx : CTRLBUS_TX;
+ signal ctrlbus_rx, bustdc_rx, bustools_rx, bus_master_out, busfee_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bustdc_tx, bustools_tx, bus_master_in, busfee_tx : CTRLBUS_TX;
signal bus_master_active : std_logic;
signal timer : TIMERS;
signal lcd_data : std_logic_vector(511 downto 0);
generic map(
PORT_NUMBER => 3,
PORT_ADDRESSES => (0 => x"d000", 1 => x"c000", 2 => x"e000", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 12, 2 => 12, others => 0),
+ PORT_ADDR_MASK => (0 => 12, 1 => 12, 2 => 5, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
BUS_RX(1) => bustdc_rx, --TDC config
- BUS_RX(2) => bustrigger_rx,
+ BUS_RX(2) => busfee_rx,
BUS_TX(0) => bustools_tx,
BUS_TX(1) => bustdc_tx,
- BUS_TX(2) => bustrigger_tx,
+ BUS_TX(2) => busfee_tx,
STAT_DEBUG => open
);
);
-THE_TRIGGER_LOGIC : entity work.trigger_logic
- generic map(
- INPUTS => 24,
- OUTPUTS => 8
- )
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
+--THE_TRIGGER_LOGIC : entity work.trigger_logic
+ --generic map(
+ --INPUTS => 24,
+ --OUTPUTS => 8
+ --)
+ --port map(
+ --CLK => clk_100_i,
+ --RESET => reset_i,
- --Slowcontrol
- BUS_RX => bustrigger_rx,
- BUS_TX => bustrigger_tx,
+ ----Slowcontrol
+ --BUS_RX => bustrigger_rx,
+ --BUS_TX => bustrigger_tx,
- --Inputs and Outputs
- INPUT => hit_in_i(24 downto 1),
- OUTPUT => triggerlogic_out(7 downto 0)
- );
- FPGA5_COMM(10 downto 7) <= trig_gen_out_i or triggerlogic_out(3 downto 0);
+ ----Inputs and Outputs
+ --INPUT => hit_in_i(24 downto 1),
+ --OUTPUT => triggerlogic_out(7 downto 0)
+ --);
+ --FPGA5_COMM(10 downto 7) <= trig_gen_out_i or triggerlogic_out(3 downto 0);
- --FPGA5_COMM(10 downto 7) <= trig_gen_out_i;
+ FPGA5_COMM(10 downto 7) <= trig_gen_out_i;
+---------------------------------------------------------------------------
+-- FEE test signals and temperature sensors
+---------------------------------------------------------------------------
+gen_fee_test : if USE_TEST_SIGNALS = 1 generate
+ THE_FEE_TEST : entity work.fee_signals
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ BUS_RX => busfee_rx,
+ BUS_TX => busfee_tx,
+ TEST_SIG_OUT(3 downto 0) => ADDON_TEST,
+ FEETEMP(1 downto 0) => ADDON_TEMP
+ );
+end generate;
+
+gen_no_fee_test : if USE_TEST_SIGNALS = 0 generate
+ busfee_tx.unknown <= busfee_rx.write or busfee_rx.read;
+ busfee_tx.ack <= '0';
+ busfee_tx.nack <= '0';
+end generate;
+
---------------------------------------------------------------------------
-- Feature I/O
---------------------------------------------------------------------------
#############################################################################
BLOCK PATH FROM CLKNET "THE_TDC/edge_rising[*]";
BLOCK NET "THE_TDC/hit_in_s*";
+BLOCK NET "THE_TDC/GEN*hit_in_s*";
BLOCK PATH FROM CLKNET "THE_TDC/hit_in_s*";
BLOCK PATH FROM CLKNET "THE_TDC/*hit_in_s*" ;
MULTICYCLE TO CELL "THE_TDC/edge_rising_100_r[*]" 4 x;
MULTICYCLE FROM CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/ringBuffer_almost_full_flag*" TO CELL "THE_TDC/TheReadout/data_out_r[*]" 2 x;
+
#MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*" 4x;
#MULTICYCLE TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/SimAdderNo.FC/FF*" 4x;
#MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo5.FC/FF*" 4x;
#MULTICYCLE TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/SimAdderNo5.FC/FF*" 4x;
+MULTICYCLE FROM CELL "THE_TDC/calibration_on" 4x;
MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/CHANNEL_200_DEBUG_OUT_1[*]" 4x;
MULTICYCLE TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/CHANNEL_200_DEBUG_OUT_1[*]" 4x;
jspc29 / tdc.git / commitdiff