*** empty log message ***

diff --git a/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd
index 53f12f9045bfafd71f7a0e7015c79bd456fa6f7a..daea29cbe1453cc7b8c03bdafe127f6e7d9f89ac 100755 (executable)
--- a/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd
+++ b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd
@@ -353,8 +353,6 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp_gbe is
   signal led_counter            : std_logic_vector(16 downto 0);
   signal rx_led                 : std_logic;
   signal tx_led                 : std_logic;
-  attribute syn_keep : boolean;
-  attribute syn_keep of led_counter : signal is true;
 
 
   signal tx_correct             : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
@@ -363,9 +361,16 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp_gbe is
   signal reset_word_cnt    : std_logic_vector(4 downto 0);
   signal make_trbnet_reset : std_logic;
   signal send_reset_words  : std_logic;
-
+  signal send_reset_in     : std_logic;
   signal reset_i                : std_logic;
   signal pwr_up                 : std_logic;
+
+  attribute syn_keep : boolean;
+  attribute syn_keep of led_counter : signal is true;
+  attribute syn_keep of send_reset_in : signal is true;
+  attribute syn_keep of reset_i : signal is true;
+
+
 begin
 
 --------------------------------------------------------------------------
@@ -375,7 +380,8 @@ begin
   PROC_RESET : process(SYSCLK)
     begin
       if rising_edge(SYSCLK) then
-        reset_i <= RESET or CTRL_OP(13);
+        reset_i <= RESET;
+        send_reset_in <= ctrl_op(15);
         pwr_up  <= '1'; --not CTRL_OP(i*16+14);
       end if;
     end process;
@@ -863,7 +869,7 @@ THE_SERDES_INPUT_PROC: process( sysclk )
     if( rising_edge(sysclk) ) then
       last_fifo_tx_empty <= fifo_tx_empty;
       first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
-      if CTRL_OP(15) = '1' then
+      if send_reset_in = '1' then
         tx_data <= x"FEFE";
         tx_k <= "11";
       elsif( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then