signal data_out_reg : std_logic_vector(31 downto 0);
signal data_ready_reg : std_logic;
signal unknown_addr_reg : std_logic;
-
+ signal read_en_i : std_logic;
+ signal write_en_i : std_logic;
+ signal addr_i : std_logic_vector(6 downto 0);
+
begin
+ read_en_i <= READ_EN_IN when rising_edge(CLK);
+ write_en_i <= WRITE_EN_IN when rising_edge(CLK);
+ addr_i <= ADDR_IN when rising_edge(CLK);
+
READ_WRITE_RESPONSE : process (CLK, RESET)
begin
if rising_edge(CLK) then
data_out_reg <= (others => '0');
data_ready_reg <= '0';
unknown_addr_reg <= '0';
- elsif READ_EN_IN = '1' then
- if to_integer(unsigned(ADDR_IN)) > BUS_LENGTH then -- if bigger than 64
+ elsif read_en_i = '1' then
+ if to_integer(unsigned(addr_i)) > BUS_LENGTH then -- if bigger than 64
data_out_reg <= (others => '0');
data_ready_reg <= '0';
unknown_addr_reg <= '1';
else
- data_out_reg <= DATA_IN(to_integer(unsigned(ADDR_IN)));
+ data_out_reg <= DATA_IN(to_integer(unsigned(addr_i)));
data_ready_reg <= '1';
unknown_addr_reg <= '0';
end if;
- elsif WRITE_EN_IN = '1' then
+ elsif write_en_i = '1' then
data_out_reg <= (others => '0');
data_ready_reg <= '0';
unknown_addr_reg <= '1';
CLK_100 : in std_logic;
--
HIT_IN : in std_logic;
- TRIGGER_IN : in std_logic;
+ TRIGGER_WIN_END_IN : in std_logic;
READ_EN_IN : in std_logic;
FIFO_DATA_OUT : out std_logic_vector(35 downto 0);
FIFO_WCNT_OUT : out unsigned(7 downto 0);
FIFO_ALMOST_FULL_OUT : out std_logic;
COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0);
- DATA_FINISHED_IN : in std_logic;
+-- DATA_FINISHED_IN : in std_logic;
--
LOST_HIT_NUMBER : out std_logic_vector(23 downto 0);
HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0);
signal encoder_start_100 : std_logic;
signal encoder_finished_i : std_logic;
signal encoder_finished_100 : std_logic;
- signal lost_hit_cntr : unsigned(23 downto 0);
- signal hit_detect_cntr : unsigned(23 downto 0);
- signal encoder_start_cntr : unsigned(23 downto 0);
- signal encoder_finished_cntr : unsigned(23 downto 0);
+ signal lost_hit_cntr : unsigned(23 downto 0) := (others => '0');
+ signal hit_detect_cntr : unsigned(23 downto 0) := (others => '0');
+ signal encoder_start_cntr : unsigned(23 downto 0) := (others => '0');
+ signal encoder_finished_cntr : unsigned(23 downto 0) := (others => '0');
-- other
- signal data_finished_i : std_logic;
+-- signal data_finished_i : std_logic;
-------------------------------------------------------------------------------
CLK_100 => CLK_100,
RESET_100 => RESET_100,
HIT_IN => hit_buf,
- TRIGGER_IN => TRIGGER_IN,
+ TRIGGER_WIN_END_IN => TRIGGER_WIN_END_IN,
EPOCH_COUNTER_IN => EPOCH_COUNTER_IN,
- DATA_FINISHED_IN => data_finished_i,
+-- DATA_FINISHED_IN => data_finished_i,
COARSE_COUNTER_IN => coarse_cntr_reg,
READ_EN_IN => READ_EN_IN,
FIFO_DATA_OUT => FIFO_DATA_OUT,
ENCODER_START_OUT => encoder_start_i,
ENCODER_FINISHED_OUT => encoder_finished_i);
- data_finished_i <= DATA_FINISHED_IN when rising_edge(CLK_100);
+-- data_finished_i <= DATA_FINISHED_IN when rising_edge(CLK_100);
pulse_sync_encoder_start : pulse_sync
port map (
WIDTH => 11)
port map (
CLK => CLK_200,
- RESET => RESET_200,
D_IN => COARSE_COUNTER_IN,
D_OUT => coarse_cntr_reg);
Lost_Hit_Counter : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
lost_hit_cntr <= (others => '0');
elsif hit_pulse_100 = '1' then
lost_hit_cntr <= lost_hit_cntr + to_unsigned(1, 1);
Hit_Detect_Counter : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
hit_detect_cntr <= (others => '0');
elsif hit_pulse_100 = '1' then
hit_detect_cntr <= hit_detect_cntr + to_unsigned(1, 1);
Encoder_Start_Counter : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
encoder_start_cntr <= (others => '0');
elsif encoder_start_100 = '1' then
encoder_start_cntr <= encoder_start_cntr + to_unsigned(1, 1);
Encoder_Finished_Counter : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
encoder_finished_cntr <= (others => '0');
elsif encoder_finished_100 = '1' then
encoder_finished_cntr <= encoder_finished_cntr + to_unsigned(1, 1);
-- File : Channel_200.vhd
-- Author : c.ugur@gsi.de
-- Created : 2012-08-28
--- Last update: 2013-03-05
+-- Last update: 2013-03-19
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
RESET_100 : in std_logic; -- reset sync with 100Mhz clk
--
HIT_IN : in std_logic; -- hit in
- TRIGGER_IN : in std_logic; -- trigger in
+ TRIGGER_WIN_END_IN : in std_logic; -- trigger in
EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); -- system coarse counter
- DATA_FINISHED_IN : in std_logic;
+-- DATA_FINISHED_IN : in std_logic;
COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
READ_EN_IN : in std_logic; -- read en signal
FIFO_DATA_OUT : out std_logic_vector(35 downto 0); -- fifo data out
-- epoch counter
signal epoch_cntr : std_logic_vector(27 downto 0);
- signal epoch_cntr_up : std_logic;
+ signal epoch_cntr_updated : std_logic := '0';
signal epoch_capture_time : std_logic_vector(10 downto 0);
-- fifo
-- fsm
type FSM is (WRITE_EPOCH, WRITE_DATA, WAIT_FOR_HIT);
- signal FSM_CURRENT, FSM_NEXT : FSM;
- signal write_epoch_fsm : std_logic;
- signal write_epoch_i : std_logic;
- signal write_data_fsm : std_logic;
- signal write_data_i : std_logic;
- signal fsm_debug_fsm : std_logic_vector(1 downto 0);
- signal fsm_debug_i : std_logic_vector(1 downto 0);
+ signal FSM_CURRENT : FSM := WRITE_EPOCH;
+ signal FSM_NEXT : FSM;
+ signal write_epoch_fsm : std_logic;
+ signal write_epoch_i : std_logic;
+ signal write_data_fsm : std_logic;
+ signal write_data_i : std_logic;
+ signal fsm_debug_fsm : std_logic_vector(1 downto 0);
+ signal fsm_debug_i : std_logic_vector(1 downto 0);
attribute syn_keep : boolean;
attribute syn_keep of ff_array_en_i : signal is true;
TimeStampCapture : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- time_stamp_i <= (others => '0');
- elsif hit_detect_reg = '1' then
+ if hit_detect_reg = '1' then
time_stamp_i <= coarse_cntr_reg;
end if;
end if;
EpochCounterCapture : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- epoch_cntr <= (others => '0');
- epoch_cntr_up <= '0';
- elsif coarse_cntr_reg = epoch_capture_time or DATA_FINISHED_IN = '1' then
- epoch_cntr <= EPOCH_COUNTER_IN;
- epoch_cntr_up <= '1';
+ if coarse_cntr_reg = epoch_capture_time or TRIGGER_WIN_END_IN = '1' then --DATA_FINISHED_IN = '1' then
+ epoch_cntr <= EPOCH_COUNTER_IN;
+ epoch_cntr_updated <= '1';
elsif write_epoch_i = '1' then
- epoch_cntr_up <= '0';
+ epoch_cntr_updated <= '0';
end if;
end if;
end process EpochCounterCapture;
FSM_CLK : process (CLK_200, RESET_200)
begin
if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- FSM_CURRENT <= WRITE_EPOCH;
- write_epoch_i <= '0';
- write_data_i <= '0';
- fsm_debug_i <= "00";
- else
- FSM_CURRENT <= FSM_NEXT;
- write_epoch_i <= write_epoch_fsm;
- write_data_i <= write_data_fsm;
- fsm_debug_i <= fsm_debug_fsm;
- end if;
+ FSM_CURRENT <= FSM_NEXT;
+ write_epoch_i <= write_epoch_fsm;
+ write_data_i <= write_data_fsm;
+ fsm_debug_i <= fsm_debug_fsm;
end if;
end process FSM_CLK;
- FSM_PROC : process (FSM_CURRENT, encoder_finished_i, epoch_cntr_up, TRIGGER_IN)
+ FSM_PROC : process (FSM_CURRENT, encoder_finished_i, epoch_cntr_updated) --, TRIGGER_IN)
begin
FSM_NEXT <= WAIT_FOR_HIT;
fsm_debug_fsm <= "10";
when WAIT_FOR_HIT =>
- if epoch_cntr_up = '1' or TRIGGER_IN = '1' then
+ if epoch_cntr_updated = '1' then -- or TRIGGER_IN = '1' then
FSM_NEXT <= WRITE_EPOCH;
else
- if encoder_finished_i = '1' and epoch_cntr_up = '1' then
+ if encoder_finished_i = '1' and epoch_cntr_updated = '1' then
write_epoch_fsm <= '1';
FSM_NEXT <= WRITE_DATA;
- elsif encoder_finished_i = '1' and epoch_cntr_up = '0' then
+ elsif encoder_finished_i = '1' and epoch_cntr_updated = '0' then
write_data_fsm <= '1';
FSM_NEXT <= WAIT_FOR_HIT;
else
FifoWriteSignal : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- fifo_data_in_i <= (others => '0');
- fifo_wr_en_i <= '0';
- elsif write_epoch_i = '1' then
+ if write_epoch_i = '1' then
fifo_data_in_i(31 downto 29) <= "011";
fifo_data_in_i(28) <= '0';
fifo_data_in_i(27 downto 0) <= epoch_cntr;
fifo_data_in_i(30) <= '0'; -- reserved bits
fifo_data_in_i(29) <= encoder_info_i(0); -- low resolution info bit
fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number
- if encoder_info_i(1) = '1' then
- fifo_data_in_i(21 downto 12) <= (others => '1'); -- encoder didn't work
- else
- fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder
- end if;
- fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge
- fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp
- fifo_wr_en_i <= '1';
+ fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder
+ fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge
+ fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp
+ fifo_wr_en_i <= '1';
else
fifo_data_in_i <= (others => '0');
fifo_wr_en_i <= '0';
RegisterOutputs : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- FIFO_DATA_OUT <= (others => '1');
- FIFO_WCNT_OUT <= (others => '0');
- FIFO_EMPTY_OUT <= '0';
- FIFO_FULL_OUT <= '0';
- FIFO_ALMOST_FULL_OUT <= '0';
- else
- FIFO_DATA_OUT <= fifo_data_out_i;
- FIFO_WCNT_OUT <= unsigned(fifo_wcnt_i);
- FIFO_EMPTY_OUT <= fifo_empty_i;
- FIFO_FULL_OUT <= fifo_full_i;
- FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i;
- end if;
+ FIFO_DATA_OUT <= fifo_data_out_i;
+ FIFO_WCNT_OUT <= unsigned(fifo_wcnt_i);
+ FIFO_EMPTY_OUT <= fifo_empty_i;
+ FIFO_FULL_OUT <= fifo_full_i;
+ FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i;
end if;
end process RegisterOutputs;
-- File : Encoder_304_Bit.vhd
-- Author : Cahit Ugur
-- Created : 2011-11-28
--- Last update: 2013-03-04
+-- Last update: 2013-03-17
-------------------------------------------------------------------------------
-- Description: Encoder for 304 bits
-------------------------------------------------------------------------------
signal info_2reg : std_logic_vector(1 downto 0);
signal info_3reg : std_logic_vector(1 downto 0);
signal info_4reg : std_logic_vector(1 downto 0);
-
+
-- FSM signals
type FSM is (IDLE, START_CNT_2, START_CNT_3, START_CNT_4);
signal FSM_CURRENT, FSM_NEXT : FSM;
signal proc_finished_4 : std_logic;
signal conv_finished_i : std_logic;
signal thermocode_i : std_logic_vector(304 downto 0);
-
+
attribute syn_keep : boolean;
attribute syn_keep of mux_control : signal is true;
attribute syn_keep of mux_control_reg : signal is true;
end if;
end process Interval_Selection;
- --ROM_Encoder_1 : ROM_Encoder
- -- port map (
- -- Address => address_i,
- -- OutClock => CLK,
- -- OutClockEn => '1',
- -- Reset => RESET,
- -- Q => q_reg);
-
- ROM4_Encoder_1 : ROM4_Encoder
+ ROM_Encoder_1 : ROM_Encoder
port map (
Address => address_i,
OutClock => CLK,
OutClockEn => '1',
Reset => RESET,
Q => q_reg);
+
+ --ROM4_Encoder_1 : ROM4_Encoder
+ -- port map (
+ -- Address => address_i,
+ -- OutClock => CLK,
+ -- OutClockEn => '1',
+ -- Reset => RESET,
+ -- Q => q_reg);
address_i <= start_2reg & interval_reg;
interval_binary <= q_reg(2 downto 0) when rising_edge(CLK);
info <= q_reg(7 downto 6) when rising_edge(CLK);
begin
if rising_edge(CLK) then
if conv_finished_i = '1' then
- BINARY_CODE_OUT <= ('0' & binary_code_r) + ('0' & binary_code_f);
- ENCODER_INFO_OUT <= info_reg or info_2reg;
+ if info_reg(1) = '1' and info_2reg(1) = '1' then
+ BINARY_CODE_OUT <= ('0' & binary_code_r) + ('0' & binary_code_f);
+ else
+ BINARY_CODE_OUT <= (others => '1');
+ end if;
+ ENCODER_INFO_OUT <= (others => '0'); --info_reg or info_2reg;
FINISHED_OUT <= '1';
else
FINISHED_OUT <= '0';
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87)
+-- Module Version: 5.0
+--/opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 10 -data_width 8 -num_rows 1024 -outdata REGISTERED -memfile /home/ugur/projects/encoder/encoder_304_with_more_bbl_errors/source/rom_encoder.mem -memformat orca -cascade -1 -e
+
+-- Mon Apr 16 15:10:22 2012
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity ROM_Encoder is
+ port (
+ Address : in std_logic_vector(9 downto 0);
+ OutClock : in std_logic;
+ OutClockEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(7 downto 0));
+end ROM_Encoder;
+
+architecture Structure of ROM_Encoder is
+
+ -- internal signal declarations
+ signal scuba_vhi : std_logic;
+ signal scuba_vlo : std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z : out std_logic);
+ end component;
+ component VLO
+ port (Z : out std_logic);
+ end component;
+ component DP16KC
+ generic (INITVAL_3F : in string; INITVAL_3E : in string;
+ INITVAL_3D : in string; INITVAL_3C : in string;
+ INITVAL_3B : in string; INITVAL_3A : in string;
+ INITVAL_39 : in string; INITVAL_38 : in string;
+ INITVAL_37 : in string; INITVAL_36 : in string;
+ INITVAL_35 : in string; INITVAL_34 : in string;
+ INITVAL_33 : in string; INITVAL_32 : in string;
+ INITVAL_31 : in string; INITVAL_30 : in string;
+ INITVAL_2F : in string; INITVAL_2E : in string;
+ INITVAL_2D : in string; INITVAL_2C : in string;
+ INITVAL_2B : in string; INITVAL_2A : in string;
+ INITVAL_29 : in string; INITVAL_28 : in string;
+ INITVAL_27 : in string; INITVAL_26 : in string;
+ INITVAL_25 : in string; INITVAL_24 : in string;
+ INITVAL_23 : in string; INITVAL_22 : in string;
+ INITVAL_21 : in string; INITVAL_20 : in string;
+ INITVAL_1F : in string; INITVAL_1E : in string;
+ INITVAL_1D : in string; INITVAL_1C : in string;
+ INITVAL_1B : in string; INITVAL_1A : in string;
+ INITVAL_19 : in string; INITVAL_18 : in string;
+ INITVAL_17 : in string; INITVAL_16 : in string;
+ INITVAL_15 : in string; INITVAL_14 : in string;
+ INITVAL_13 : in string; INITVAL_12 : in string;
+ INITVAL_11 : in string; INITVAL_10 : in string;
+ INITVAL_0F : in string; INITVAL_0E : in string;
+ INITVAL_0D : in string; INITVAL_0C : in string;
+ INITVAL_0B : in string; INITVAL_0A : in string;
+ INITVAL_09 : in string; INITVAL_08 : in string;
+ INITVAL_07 : in string; INITVAL_06 : in string;
+ INITVAL_05 : in string; INITVAL_04 : in string;
+ INITVAL_03 : in string; INITVAL_02 : in string;
+ INITVAL_01 : in string; INITVAL_00 : in string;
+ GSR : in string; WRITEMODE_B : in string;
+ WRITEMODE_A : in string; CSDECODE_B : in string;
+ CSDECODE_A : in string; REGMODE_B : in string;
+ REGMODE_A : in string; DATA_WIDTH_B : in integer;
+ DATA_WIDTH_A : in integer);
+ port (DIA0 : in std_logic; DIA1 : in std_logic;
+ DIA2 : in std_logic; DIA3 : in std_logic;
+ DIA4 : in std_logic; DIA5 : in std_logic;
+ DIA6 : in std_logic; DIA7 : in std_logic;
+ DIA8 : in std_logic; DIA9 : in std_logic;
+ DIA10 : in std_logic; DIA11 : in std_logic;
+ DIA12 : in std_logic; DIA13 : in std_logic;
+ DIA14 : in std_logic; DIA15 : in std_logic;
+ DIA16 : in std_logic; DIA17 : in std_logic;
+ ADA0 : in std_logic; ADA1 : in std_logic;
+ ADA2 : in std_logic; ADA3 : in std_logic;
+ ADA4 : in std_logic; ADA5 : in std_logic;
+ ADA6 : in std_logic; ADA7 : in std_logic;
+ ADA8 : in std_logic; ADA9 : in std_logic;
+ ADA10 : in std_logic; ADA11 : in std_logic;
+ ADA12 : in std_logic; ADA13 : in std_logic;
+ CEA : in std_logic; CLKA : in std_logic; OCEA : in std_logic;
+ WEA : in std_logic; CSA0 : in std_logic; CSA1 : in std_logic;
+ CSA2 : in std_logic; RSTA : in std_logic;
+ DIB0 : in std_logic; DIB1 : in std_logic;
+ DIB2 : in std_logic; DIB3 : in std_logic;
+ DIB4 : in std_logic; DIB5 : in std_logic;
+ DIB6 : in std_logic; DIB7 : in std_logic;
+ DIB8 : in std_logic; DIB9 : in std_logic;
+ DIB10 : in std_logic; DIB11 : in std_logic;
+ DIB12 : in std_logic; DIB13 : in std_logic;
+ DIB14 : in std_logic; DIB15 : in std_logic;
+ DIB16 : in std_logic; DIB17 : in std_logic;
+ ADB0 : in std_logic; ADB1 : in std_logic;
+ ADB2 : in std_logic; ADB3 : in std_logic;
+ ADB4 : in std_logic; ADB5 : in std_logic;
+ ADB6 : in std_logic; ADB7 : in std_logic;
+ ADB8 : in std_logic; ADB9 : in std_logic;
+ ADB10 : in std_logic; ADB11 : in std_logic;
+ ADB12 : in std_logic; ADB13 : in std_logic;
+ CEB : in std_logic; CLKB : in std_logic; OCEB : in std_logic;
+ WEB : in std_logic; CSB0 : in std_logic; CSB1 : in std_logic;
+ CSB2 : in std_logic; RSTB : in std_logic;
+ DOA0 : out std_logic; DOA1 : out std_logic;
+ DOA2 : out std_logic; DOA3 : out std_logic;
+ DOA4 : out std_logic; DOA5 : out std_logic;
+ DOA6 : out std_logic; DOA7 : out std_logic;
+ DOA8 : out std_logic; DOA9 : out std_logic;
+ DOA10 : out std_logic; DOA11 : out std_logic;
+ DOA12 : out std_logic; DOA13 : out std_logic;
+ DOA14 : out std_logic; DOA15 : out std_logic;
+ DOA16 : out std_logic; DOA17 : out std_logic;
+ DOB0 : out std_logic; DOB1 : out std_logic;
+ DOB2 : out std_logic; DOB3 : out std_logic;
+ DOB4 : out std_logic; DOB5 : out std_logic;
+ DOB6 : out std_logic; DOB7 : out std_logic;
+ DOB8 : out std_logic; DOB9 : out std_logic;
+ DOB10 : out std_logic; DOB11 : out std_logic;
+ DOB12 : out std_logic; DOB13 : out std_logic;
+ DOB14 : out std_logic; DOB15 : out std_logic;
+ DOB16 : out std_logic; DOB17 : out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute MEM_LPC_FILE of ROM_Encoder_0_0_0 : label is "ROM_Encoder.lpc";
+ attribute MEM_INIT_FILE of ROM_Encoder_0_0_0 : label is "rom_encoder.mem";
+ attribute RESETMODE of ROM_Encoder_0_0_0 : label is "SYNC";
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst : VHI
+ port map (Z => scuba_vhi);
+
+ scuba_vlo_inst : VLO
+ port map (Z => scuba_vlo);
+
+ ROM_Encoder_0_0_0 : DP16KC
+ generic map (INITVAL_3F => "0x00000000800008000081000000000000000000820000000081000820008200000000000008200083",
+ INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000084",
+ INITVAL_3D => "0x00000000000000000000000000000000000000000000000083000830008300000000000008400084",
+ INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000840008400000000000008500085",
+ INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085",
+ INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000008500000000000008600086",
+ INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085",
+ INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000008600000000000008600086",
+ INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000086",
+ INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000008700000000000008700087",
+ INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_17 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_13 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_12 => "0x00084000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_10 => "0x00083000000000000000000000000000000000000008200000000000000000081000800000000000",
+ INITVAL_0F => "0x00087000000000000000000870000000000000000000000000000000000000000000000000000000",
+ INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0B => "0x00086000000000000000000860000000000000000000000000000000000000000000000000000000",
+ INITVAL_0A => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_07 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_06 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_05 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_04 => "0x00084000000000000000000840000000000000000000000000000000000000083000830000000000",
+ INITVAL_03 => "0x00085000000000000000000840000000000000000000000000000000000000000000000000000000",
+ INITVAL_02 => "0x00084000000000000000000840008400000000000000000000000000000000000000000000000000",
+ INITVAL_01 => "0x00084000000000000000000830000000000000000000000000000000000000082000820000000000",
+ INITVAL_00 => "0x00083000000000000000000820008200081000000008200082000810000000081000800008000000",
+ CSDECODE_B => "0b111", CSDECODE_A => "0b000", WRITEMODE_B => "NORMAL",
+ WRITEMODE_A => "NORMAL", GSR => "DISABLED", REGMODE_B => "NOREG",
+ REGMODE_A => "OUTREG", DATA_WIDTH_B => 18, DATA_WIDTH_A => 18)
+ port map (DIA0 => scuba_vlo, DIA1 => scuba_vlo, DIA2 => scuba_vlo,
+ DIA3 => scuba_vlo, DIA4 => scuba_vlo, DIA5 => scuba_vlo,
+ DIA6 => scuba_vlo, DIA7 => scuba_vlo, DIA8 => scuba_vlo,
+ DIA9 => scuba_vlo, DIA10 => scuba_vlo, DIA11 => scuba_vlo,
+ DIA12 => scuba_vlo, DIA13 => scuba_vlo, DIA14 => scuba_vlo,
+ DIA15 => scuba_vlo, DIA16 => scuba_vlo, DIA17 => scuba_vlo,
+ ADA0 => scuba_vlo, ADA1 => scuba_vlo, ADA2 => scuba_vlo,
+ ADA3 => scuba_vlo, ADA4 => Address(0), ADA5 => Address(1),
+ ADA6 => Address(2), ADA7 => Address(3), ADA8 => Address(4),
+ ADA9 => Address(5), ADA10 => Address(6), ADA11 => Address(7),
+ ADA12 => Address(8), ADA13 => Address(9), CEA => OutClockEn,
+ CLKA => OutClock, OCEA => OutClockEn, WEA => scuba_vlo,
+ CSA0 => scuba_vlo, CSA1 => scuba_vlo, CSA2 => scuba_vlo,
+ RSTA => Reset, DIB0 => scuba_vlo, DIB1 => scuba_vlo,
+ DIB2 => scuba_vlo, DIB3 => scuba_vlo, DIB4 => scuba_vlo,
+ DIB5 => scuba_vlo, DIB6 => scuba_vlo, DIB7 => scuba_vlo,
+ DIB8 => scuba_vlo, DIB9 => scuba_vlo, DIB10 => scuba_vlo,
+ DIB11 => scuba_vlo, DIB12 => scuba_vlo, DIB13 => scuba_vlo,
+ DIB14 => scuba_vlo, DIB15 => scuba_vlo, DIB16 => scuba_vlo,
+ DIB17 => scuba_vlo, ADB0 => scuba_vlo, ADB1 => scuba_vlo,
+ ADB2 => scuba_vlo, ADB3 => scuba_vlo, ADB4 => scuba_vlo,
+ ADB5 => scuba_vlo, ADB6 => scuba_vlo, ADB7 => scuba_vlo,
+ ADB8 => scuba_vlo, ADB9 => scuba_vlo, ADB10 => scuba_vlo,
+ ADB11 => scuba_vlo, ADB12 => scuba_vlo, ADB13 => scuba_vlo,
+ CEB => scuba_vhi, CLKB => scuba_vlo, OCEB => scuba_vhi,
+ WEB => scuba_vlo, CSB0 => scuba_vlo, CSB1 => scuba_vlo,
+ CSB2 => scuba_vlo, RSTB => scuba_vlo, DOA0 => Q(0), DOA1 => Q(1),
+ DOA2 => Q(2), DOA3 => Q(3), DOA4 => Q(4), DOA5 => Q(5), DOA6 => Q(6),
+ DOA7 => Q(7), DOA8 => open, DOA9 => open, DOA10 => open, DOA11 => open,
+ DOA12 => open, DOA13 => open, DOA14 => open, DOA15 => open,
+ DOA16 => open, DOA17 => open, DOB0 => open, DOB1 => open, DOB2 => open,
+ DOB3 => open, DOB4 => open, DOB5 => open, DOB6 => open, DOB7 => open,
+ DOB8 => open, DOB9 => open, DOB10 => open, DOB11 => open,
+ DOB12 => open, DOB13 => open, DOB14 => open, DOB15 => open,
+ DOB16 => open, DOB17 => open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of ROM_Encoder is
+ for Structure
+ for all : VHI use entity ecp3.VHI(V); end for;
+ for all : VLO use entity ecp3.VLO(V); end for;
+ for all : DP16KC use entity ecp3.DP16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
-- File : Readout.vhd
-- Author : cugur@gsi.de
-- Created : 2012-10-25
--- Last update: 2013-03-01
+-- Last update: 2013-03-07
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
RESET_100 : in std_logic;
RESET_COUNTERS : in std_logic;
--
- HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1);
REFERENCE_TIME : in std_logic;
TRIGGER_TIME_IN : in std_logic_vector(38 downto 0);
TRG_WIN_PRE : in std_logic_vector(10 downto 0);
READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0);
TRIGGER_WIN_END_OUT : out std_logic;
--
- STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to 23);
+ STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to 18);
READOUT_DEBUG : out std_logic_vector(31 downto 0)
);
signal slow_control_ch_empty_i : std_logic_vector(63 downto 0);
-- trigger window
- signal start_trg_win_cnt : std_logic;
+ signal start_trg_win_cnt : std_logic := '0';
signal start_trg_win_cnt_200_p : std_logic;
signal trg_win_post_200 : std_logic_vector(10 downto 0);
signal trg_win_cnt : std_logic_vector(11 downto 0);
- signal trg_win_end_200 : std_logic;
+ signal trg_win_end_200 : std_logic := '0';
signal trg_win_end_200_p : std_logic;
signal trg_win_end_100_p : std_logic;
signal trg_win_end_100_reg : std_logic;
-- readout fsm
type FSM_READ is (IDLE, WAIT_FOR_TRG_WIND_END, RD_CH, WAIT_FOR_LVL1_TRG_A, WAIT_FOR_LVL1_TRG_B,
WAIT_FOR_LVL1_TRG_C, SEND_STATUS, SEND_TRG_RELEASE_A, SEND_TRG_RELEASE_B);
- signal RD_CURRENT, RD_NEXT : FSM_READ;
+ signal RD_CURRENT : FSM_READ := IDLE;
+ signal RD_NEXT : FSM_READ;
type FSM_WRITE is (IDLE, WR_CH);
- signal WR_CURRENT, WR_NEXT : FSM_WRITE;
+ signal WR_CURRENT : FSM_WRITE := IDLE;
+ signal WR_NEXT : FSM_WRITE;
signal start_trg_win_cnt_fsm : std_logic;
signal rd_fsm_debug_fsm : std_logic_vector(3 downto 0);
signal ch_almost_full_i : std_logic;
signal rd_fsm_debug : std_logic_vector(3 downto 0);
signal wr_fsm_debug : std_logic_vector(3 downto 0);
- -- delme
- signal win_end_200_cnt : unsigned(7 downto 0) := (others => '0');
- signal win_end_100_cnt : unsigned(7 downto 0) := (others => '0');
- signal start_trg_win_counter : unsigned(7 downto 0) := (others => '0');
- signal wr_finished_cnt : unsigned(7 downto 0) := (others => '0');
begin -- behavioral
-------------------------------------------------------------------------------
begin
if rising_edge(CLK_200) then
if RESET_200 = '1' then
- trg_win_end_200 <= '0';
trg_win_cnt <= '1' & trg_win_post_200;
elsif start_trg_win_cnt_200_p = '1' then
trg_win_end_200 <= '0';
trg_win_end_100_4reg <= trg_win_end_100_3reg when rising_edge(CLK_100);
-- Trigger window borders
- Trg_Win_Calculation : process (CLK_100, RESET_100)
+ Trg_Win_Calculation : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- TW_pre <= (others => '0');
--- TW_post <= (others => '0');
- else
- TW_pre <= std_logic_vector(to_unsigned(to_integer(unsigned(TRIGGER_TIME_IN))-to_integer(unsigned(TRG_WIN_PRE)), 39));
--- TW_post <= std_logic_vector(to_unsigned(to_integer(unsigned(TRIGGER_TIME_IN))+to_integer(unsigned(TRG_WIN_POST)), 39));
- end if;
+ TW_pre <= std_logic_vector(to_unsigned(to_integer(unsigned(TRIGGER_TIME_IN))-to_integer(unsigned(TRG_WIN_PRE)), 39));
+-- TW_post <= std_logic_vector(to_unsigned(to_integer(unsigned(TRIGGER_TIME_IN))+to_integer(unsigned(TRG_WIN_POST)), 39));
end if;
end process Trg_Win_Calculation;
ChannelEpochCounter : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- ch_epoch_cntr_i <= (others => '0');
- --elsif then
- -- ch_epoch_cntr_i <= (others => '0');
- elsif ch_data_reg(fifo_nr_wr_2reg)(31 downto 29) = "011" then
+ if ch_data_reg(fifo_nr_wr_2reg)(31 downto 29) = "011" then
ch_epoch_cntr_i <= ch_data_reg(fifo_nr_wr_2reg)(27 downto 0);
end if;
end if;
ChannelHitTime : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- ch_hit_time <= (others => '0');
- elsif ch_data_reg(fifo_nr_wr_2reg)(31) = '1' then
+ if ch_data_reg(fifo_nr_wr_2reg)(31) = '1' then
ch_hit_time <= ch_epoch_cntr_i & ch_data_reg(fifo_nr_wr_2reg)(10 downto 0);
elsif ch_data_reg(fifo_nr_wr_2reg)(31 downto 29) = "011" then
ch_hit_time <= (others => '0');
end process ChannelHitTime;
-- Controls if the data coming from the channel is greater than the trigger window pre-edge
- Check_Trg_Win_Left : process (RESET_100, TW_pre, ch_hit_time)
+ Check_Trg_Win_Left : process (TW_pre, ch_hit_time)
begin
--if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- trg_win_l <= '0';
- elsif to_integer(unsigned(TW_pre)) <= to_integer(unsigned(ch_hit_time)) then
+ if to_integer(unsigned(TW_pre)) <= to_integer(unsigned(ch_hit_time)) then
trg_win_l <= '1';
else
trg_win_l <= '0';
RD_FSM_CLK : process (CLK_100, RESET_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- RD_CURRENT <= IDLE;
- start_trg_win_cnt <= '0';
- rd_en <= (others => '0');
- wr_header <= '0';
- wr_status <= '0';
- data_finished <= '0';
- trg_release_reg <= '0';
- wrong_readout_up <= '0';
- idle_time_up <= '0';
- readout_time_up <= '0';
- wait_time_up <= '0';
- rd_number <= (others => '0');
- fifo_nr_rd <= 0;
- rd_fsm_debug <= x"0";
- else
- RD_CURRENT <= RD_NEXT;
- start_trg_win_cnt <= start_trg_win_cnt_fsm;
- rd_en <= rd_en_fsm;
- wr_header <= wr_header_fsm;
- wr_status <= wr_status_fsm;
- data_finished <= data_finished_fsm;
- trg_release_reg <= trg_release_fsm;
- wrong_readout_up <= wrong_readout_fsm;
- idle_time_up <= idle_fsm;
- readout_time_up <= readout_fsm;
- wait_time_up <= wait_fsm;
- rd_number <= rd_number_fsm;
- fifo_nr_rd <= fifo_nr_rd_fsm;
- rd_fsm_debug <= rd_fsm_debug_fsm;
- end if;
+ RD_CURRENT <= RD_NEXT;
+ start_trg_win_cnt <= start_trg_win_cnt_fsm;
+ rd_en <= rd_en_fsm;
+ wr_header <= wr_header_fsm;
+ wr_status <= wr_status_fsm;
+ data_finished <= data_finished_fsm;
+ trg_release_reg <= trg_release_fsm;
+ wrong_readout_up <= wrong_readout_fsm;
+ idle_time_up <= idle_fsm;
+ readout_time_up <= readout_fsm;
+ wait_time_up <= wait_fsm;
+ rd_number <= rd_number_fsm;
+ fifo_nr_rd <= fifo_nr_rd_fsm;
+ rd_fsm_debug <= rd_fsm_debug_fsm;
end if;
end process RD_FSM_CLK;
READ_EN_OUT <= rd_en;
WR_FSM_CLK : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- WR_CURRENT <= IDLE;
- wr_ch_data_i <= '0';
- wr_number <= (others => '0');
- fifo_nr_wr <= 0;
- wr_finished <= '0';
- wr_fsm_debug <= x"0";
- else
- WR_CURRENT <= WR_NEXT;
- wr_ch_data_i <= wr_ch_data_fsm;
- wr_number <= wr_number_fsm;
- fifo_nr_wr <= fifo_nr_wr_fsm;
- wr_finished <= wr_finished_fsm;
- wr_fsm_debug <= wr_fsm_debug_fsm;
- end if;
+ WR_CURRENT <= WR_NEXT;
+ wr_ch_data_i <= wr_ch_data_fsm;
+ wr_number <= wr_number_fsm;
+ fifo_nr_wr <= fifo_nr_wr_fsm;
+ wr_finished <= wr_finished_fsm;
+ wr_fsm_debug <= wr_fsm_debug_fsm;
end if;
end process WR_FSM_CLK;
-------------------------------------------------------------------------------
-- Data out mux
-------------------------------------------------------------------------------
- Data_Out_MUX : process (CLK_100, RESET_100)
+ Data_Out_MUX : process (CLK_100)
variable i : integer := 0;
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- data_out_reg <= (others => '1');
- data_wr_reg <= '0';
- stop_status_i <= '0';
- elsif wr_header = '1' then
+ if wr_header = '1' then
data_out_reg <= "001" & "0" & TRG_TYPE_IN & TRG_CODE_IN & header_error_bits;
data_wr_reg <= '1';
stop_status_i <= '0';
pulse => timeout_detected_p);
-- Internal trigger number counter (only valid triggers)
- Statistics_Trigger_Number : process (CLK_100, RESET_100)
+ Statistics_Trigger_Number : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
trig_number <= (others => '0');
elsif valid_timing_trg_p = '1' or valid_notiming_trg_p = '1' then
trig_number <= trig_number + to_unsigned(1, 1);
end process Statistics_Trigger_Number;
-- Internal release number counter
- Statistics_Release_Number : process (CLK_100, RESET_100)
+ Statistics_Release_Number : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
release_number <= (others => '0');
elsif trg_release_reg = '1' then
release_number <= release_number + to_unsigned(1, 1);
end process Statistics_Release_Number;
-- Internal valid timing trigger number counter
- Statistics_Valid_Timing_Trigger_Number : process (CLK_100, RESET_100)
+ Statistics_Valid_Timing_Trigger_Number : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
valid_tmg_trig_number <= (others => '0');
elsif valid_timing_trg_p = '1' then
valid_tmg_trig_number <= valid_tmg_trig_number + to_unsigned(1, 1);
end process Statistics_Valid_Timing_Trigger_Number;
-- Internal valid NOtiming trigger number counter
- Statistics_Valid_NoTiming_Trigger_Number : process (CLK_100, RESET_100)
+ Statistics_Valid_NoTiming_Trigger_Number : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
valid_NOtmg_trig_number <= (others => '0');
elsif valid_notiming_trg_p = '1' then
valid_NOtmg_trig_number <= valid_NOtmg_trig_number + to_unsigned(1, 1);
end process Statistics_Valid_NoTiming_Trigger_Number;
-- Internal invalid trigger number counter
- Statistics_Invalid_Trigger_Number : process (CLK_100, RESET_100)
+ Statistics_Invalid_Trigger_Number : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
invalid_trig_number <= (others => '0');
elsif invalid_trg_p = '1' then
invalid_trig_number <= invalid_trig_number + to_unsigned(1, 1);
end process Statistics_Invalid_Trigger_Number;
-- Internal multi timing trigger number counter
- Statistics_Multi_Timing_Trigger_Number : process (CLK_100, RESET_100)
+ Statistics_Multi_Timing_Trigger_Number : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
multi_tmg_trig_number <= (others => '0');
elsif multi_tmg_trg_p = '1' then
multi_tmg_trig_number <= multi_tmg_trig_number + to_unsigned(1, 1);
end process Statistics_Multi_Timing_Trigger_Number;
-- Internal spurious trigger number counter
- Statistics_Spurious_Trigger_Number : process (CLK_100, RESET_100)
+ Statistics_Spurious_Trigger_Number : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
spurious_trig_number <= (others => '0');
elsif spurious_trg_p = '1' then
spurious_trig_number <= spurious_trig_number + to_unsigned(1, 1);
end process Statistics_Spurious_Trigger_Number;
-- Number of wrong readout becasue of spurious trigger
- Statistics_Wrong_Readout_Number : process (CLK_100, RESET_100)
+ Statistics_Wrong_Readout_Number : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
wrong_readout_number <= (others => '0');
elsif wrong_readout_up = '1' then
wrong_readout_number <= wrong_readout_number + to_unsigned(1, 1);
end process Statistics_Wrong_Readout_Number;
-- Internal spike number counter
- Statistics_Spike_Number : process (CLK_100, RESET_100)
+ Statistics_Spike_Number : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
spike_number <= (others => '0');
elsif spike_detected_p = '1' then
spike_number <= spike_number + to_unsigned(1, 1);
end process Statistics_Spike_Number;
-- Internal timeout number counter
- Statistics_Timeout_Number : process (CLK_100, RESET_100)
+ Statistics_Timeout_Number : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
timeout_number <= (others => '0');
elsif timeout_detected_p = '1' then
timeout_number <= timeout_number + to_unsigned(1, 1);
end process Statistics_Timeout_Number;
-- IDLE time of the TDC readout
- Statistics_Idle_Time : process (CLK_100, RESET_100)
+ Statistics_Idle_Time : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
idle_time <= (others => '0');
elsif idle_time_up = '1' then
idle_time <= idle_time + to_unsigned(1, 1);
end process Statistics_Idle_Time;
-- Readout and Wait time of the TDC readout
- Statistics_Readout_Wait_Time : process (CLK_100, RESET_100)
+ Statistics_Readout_Wait_Time : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
readout_time <= (others => '0');
wait_time <= (others => '0');
elsif readout_time_up = '1' then
end process Statistics_Readout_Wait_Time;
-- Empty channel number
- Statistics_Empty_Channel_Number : process (CLK_100, RESET_100)
+ Statistics_Empty_Channel_Number : process (CLK_100)
variable i : integer := CHANNEL_NUMBER;
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
total_empty_channel <= (others => '0');
i := CHANNEL_NUMBER;
elsif trg_win_end_100_p = '1' then
end if;
end process Statistics_Empty_Channel_Number;
- -- Readout and Wait time of the TDC readout
+ -- Number of sent data finished
Statistics_Finished_Number : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
+ if RESET_COUNTERS = '1' then
finished_number <= (others => '0');
elsif finished_i = '1' then
finished_number <= finished_number + to_unsigned(1, 1);
STATUS_REGISTERS_BUS_OUT(17)(23 downto 0) <= std_logic_vector(timeout_number);
STATUS_REGISTERS_BUS_OUT(18)(23 downto 0) <= std_logic_vector(finished_number);
STATUS_REGISTERS_BUS_OUT(18)(31 downto 24) <= std_logic_vector(wr_number);
- STATUS_REGISTERS_BUS_OUT(19)(7 downto 0) <= std_logic_vector(win_end_200_cnt);
- STATUS_REGISTERS_BUS_OUT(19)(15 downto 8) <= std_logic_vector(start_trg_win_counter);
- STATUS_REGISTERS_BUS_OUT(19)(23 downto 16) <= std_logic_vector(win_end_100_cnt);
- STATUS_REGISTERS_BUS_OUT(19)(31 downto 24) <= std_logic_vector(wr_finished_cnt);
- STATUS_REGISTERS_BUS_OUT(20)(10 downto 0) <= trg_win_post_200;
- STATUS_REGISTERS_BUS_OUT(20)(27 downto 16) <= trg_win_cnt;
FILL_BUS1 : for i in 4 to 17 generate
STATUS_REGISTERS_BUS_OUT(i)(31 downto 24) <= (others => '0');
end generate FILL_BUS1;
- FILL_BUS2 : for i in 21 to 23 generate
- STATUS_REGISTERS_BUS_OUT(i) <= (others => '0');
- end generate FILL_BUS2;
-
slow_control_ch_empty_i(63 downto CHANNEL_NUMBER-1) <= (others => '1');
slow_control_ch_empty_i(CHANNEL_NUMBER-2 downto 0) <= ch_empty_2reg(CHANNEL_NUMBER-1 downto 1);
--------------------------------------------------------------------------------
--- delme
--------------------------------------------------------------------------------
-
- debug1 : process (CLK_200)
- begin
- if rising_edge(CLK_200) then
- if RESET_200 = '1' or RESET_COUNTERS = '1' then
- win_end_200_cnt <= (others => '0');
- elsif trg_win_end_200_p = '1' then
- win_end_200_cnt <= win_end_200_cnt + to_unsigned(1,1);
- end if;
- end if;
- end process debug1;
-
- debug2 : process (CLK_200)
- begin
- if rising_edge(CLK_200) then
- if RESET_200 = '1' or RESET_COUNTERS = '1' then
- start_trg_win_counter <= (others => '0');
- elsif start_trg_win_cnt_200_p = '1' then
- start_trg_win_counter <= start_trg_win_counter + to_unsigned(1, 1);
- end if;
- end if;
- end process debug2;
-
- debug3 : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
- win_end_100_cnt <= (others => '0');
- elsif trg_win_end_100_3reg = '1' then
- win_end_100_cnt <= win_end_100_cnt + to_unsigned(1,1);
- end if;
- end if;
- end process debug3;
-
- debug4 : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_100 = '1' or RESET_COUNTERS = '1' then
- wr_finished_cnt <= (others => '0');
- elsif wr_finished_2reg = '1' then
- wr_finished_cnt <= wr_finished_cnt + to_unsigned(1,1);
- end if;
- end if;
- end process debug4;
-
-
-------------------------------------------------------------------------------
-- Registering
-------------------------------------------------------------------------------
--- 100 MHz
--- updt_index_reg <= updt_index when rising_edge(CLK_100);
--- data_finished_reg <= data_finished when rising_edge(CLK_100);
ch_data_reg <= CH_DATA_IN when rising_edge(CLK_100);
ch_data_2reg <= ch_data_reg when rising_edge(CLK_100);
--- ch_data_3reg <= ch_data_2reg when rising_edge(CLK_100);
ch_empty_reg <= CH_EMPTY_IN when rising_edge(CLK_100);
ch_empty_2reg <= ch_empty_reg when rising_edge(CLK_100);
ch_empty_3reg <= ch_empty_2reg when rising_edge(CLK_100);
ch_empty_4reg <= ch_empty_3reg when rising_edge(CLK_100);
--- 200 MHz
trg_win_post_200 <= std_logic_vector(unsigned(TRG_WIN_POST)-8) when rising_edge(CLK_200);
end behavioral;
WIDTH => 11)
port map (
CLK => CLK_200,
- RESET => RESET_200,
D_IN => COARSE_COUNTER_IN,
D_OUT => coarse_cntr_reg);
-- File : Reference_channel_200.vhd
-- Author : c.ugur@gsi.de
-- Created : 2012-09-04
--- Last update: 2013-03-05
+-- Last update: 2013-03-18
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- carry chain
signal data_a_i : std_logic_vector(303 downto 0);
signal data_b_i : std_logic_vector(303 downto 0);
- signal result_i : std_logic_vector(303 downto 0);
- signal ff_array_en_i : std_logic;
+ signal result_i : std_logic_vector(303 downto 0) := (others => '1');
+ signal ff_array_en_i : std_logic := '0';
-- hit detection
signal result_2_reg : std_logic;
signal fifo_wcnt_i : std_logic_vector(7 downto 0);
signal fifo_empty_i : std_logic;
signal fifo_full_i : std_logic;
- signal fifo_was_full_i : std_logic;
+ signal fifo_was_full_i : std_logic := '0';
signal fifo_almost_full_i : std_logic;
- signal fifo_wr_en_i : std_logic;
+ signal fifo_wr_en_i : std_logic := '0';
signal fifo_rd_en_i : std_logic;
-- timing trigger
signal spike_detected_i : std_logic;
-- coarse counter overflow
- signal coarse_cntr_overflow_release : std_logic;
- signal coarse_cntr_overflow_flag : std_logic;
+ signal coarse_cntr_overflow_release : std_logic := '0';
+ signal coarse_cntr_overflow_flag : std_logic := '0';
-- epoch counter
signal epoch_cntr : std_logic_vector(27 downto 0);
signal epoch_time : std_logic_vector(27 downto 0);
signal epoch_word_first : std_logic_vector(35 downto 0);
- signal epoch_cntr_up : std_logic;
+ signal epoch_cntr_up : std_logic := '0';
signal epoch_capture_time : std_logic_vector(10 downto 0);
-- other
-- fsm
type FSM is (IDLE, LOOK_FOR_VALIDITY, ENCODER_FINISHED, WAIT_FOR_FALLING_EDGE);
- signal FSM_CURRENT, FSM_NEXT : FSM;
- signal valid_trigger_i : std_logic;
- signal valid_trigger_fsm : std_logic;
- signal fsm_debug_i : std_logic_vector(3 downto 0);
- signal fsm_debug_fsm : std_logic_vector(3 downto 0);
+ signal FSM_CURRENT : FSM := IDLE;
+ signal FSM_NEXT : FSM;
+ signal valid_trigger_i : std_logic;
+ signal valid_trigger_fsm : std_logic;
+ signal fsm_debug_i : std_logic_vector(3 downto 0);
+ signal fsm_debug_fsm : std_logic_vector(3 downto 0);
attribute syn_keep : boolean;
attribute syn_keep of ff_array_en_i : signal is true;
TimeStampCapture : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- time_stamp_i <= (others => '0');
- elsif hit_detect_reg = '1' then
+ if hit_detect_reg = '1' then
time_stamp_i <= coarse_cntr_reg;
end if;
end if;
EpochCounterUpdate : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- epoch_cntr <= (others => '0');
- epoch_cntr_up <= '0';
- elsif coarse_cntr_reg = epoch_capture_time then
+ if coarse_cntr_reg = epoch_capture_time then
epoch_cntr <= EPOCH_COUNTER_IN;
epoch_cntr_up <= '1';
end if;
EpochCounterCapture : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- epoch_time <= (others => '0');
- elsif encoder_finished_i = '1' then
+ if encoder_finished_i = '1' then
epoch_time <= epoch_cntr;
end if;
end if;
CoarseCounterOverflowFlag : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- coarse_cntr_overflow_flag <= '0';
- elsif epoch_cntr_up = '1' or trg_win_end_i = '1' then
+ if epoch_cntr_up = '1' or trg_win_end_i = '1' then
coarse_cntr_overflow_flag <= '1';
elsif coarse_cntr_overflow_release = '1' then
coarse_cntr_overflow_flag <= '0';
FifoWriteSignal : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- fifo_data_in_i <= (others => '0');
- coarse_cntr_overflow_release <= '0';
- fifo_wr_en_i <= '0';
- time_stamp_epoch_bits <= (others => '0');
- elsif valid_trigger_i = '1' then
+ if valid_trigger_i = '1' then
fifo_data_in_i(31 downto 29) <= "011";
fifo_data_in_i(28) <= '0';
fifo_data_in_i(27 downto 0) <= epoch_time;
TRIGGER_TIME_STAMP_OUT <= time_stamp_epoch_bits & time_stamp_i;
- EpochCounterCaptureFirstWord : process (CLK_100, RESET_100)
+ EpochCounterCaptureFirstWord : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- epoch_word_first <= x"060000000";
- elsif DATA_FINISHED_IN = '1' and RUN_MODE = '0' then
+ if DATA_FINISHED_IN = '1' and RUN_MODE = '0' then
epoch_word_first <= x"060000000";
elsif fifo_data_out_i(31 downto 29) = "011" then
epoch_word_first <= fifo_data_out_i;
read_en_2reg <= read_en_reg when rising_edge(CLK_100);
first_read_i <= read_en_reg and not(read_en_2reg) when rising_edge(CLK_100);
- FifoWasFull : process (CLK_100, RESET_100)
+ FifoWasFull : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- fifo_was_full_i <= '0';
- elsif fifo_full_i = '1' then
+ if fifo_full_i = '1' then
fifo_was_full_i <= '1';
elsif fifo_empty_i = '1' then
fifo_was_full_i <= '0';
RegisterOutputs : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- FIFO_DATA_OUT <= (others => '1');
- FIFO_WCNT_OUT <= (others => '0');
- FIFO_EMPTY_OUT <= '0';
- FIFO_FULL_OUT <= '0';
- FIFO_ALMOST_FULL_OUT <= '0';
+ if first_read_i = '1' and fifo_was_full_i = '1' then
+ FIFO_DATA_OUT <= epoch_word_first;
else
- if first_read_i = '1' and fifo_was_full_i = '1' then
- FIFO_DATA_OUT <= epoch_word_first;
- else
- FIFO_DATA_OUT <= fifo_data_out_i;
- end if;
- FIFO_WCNT_OUT <= unsigned(fifo_wcnt_i);
- FIFO_EMPTY_OUT <= fifo_empty_i;
- FIFO_FULL_OUT <= fifo_full_i;
- FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i;
+ FIFO_DATA_OUT <= fifo_data_out_i;
end if;
+ FIFO_WCNT_OUT <= unsigned(fifo_wcnt_i);
+ FIFO_EMPTY_OUT <= fifo_empty_i;
+ FIFO_FULL_OUT <= fifo_full_i;
+ FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i;
end if;
end process RegisterOutputs;
--purpose: FSM for controlling the validity of the timing signal
- FSM_CLK : process (CLK_200, RESET_200)
+ FSM_CLK : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- FSM_CURRENT <= IDLE;
- valid_trigger_i <= '0';
- fsm_debug_i <= (others => '0');
- else
- FSM_CURRENT <= FSM_NEXT;
- valid_trigger_i <= valid_trigger_fsm;
- fsm_debug_i <= fsm_debug_fsm;
- end if;
+ FSM_CURRENT <= FSM_NEXT;
+ valid_trigger_i <= valid_trigger_fsm;
+ fsm_debug_i <= fsm_debug_fsm;
end if;
end process FSM_CLK;
-- File : Register.vhd
-- Author : c.ugur@gsi.de
-- Created : 2012-10-02
--- Last update: 2012-10-04
+-- Last update: 2013-03-06
-------------------------------------------------------------------------------
-- Description: Used to register signals n levels.
-------------------------------------------------------------------------------
port (
CLK : in std_logic; -- register clock
- RESET : in std_logic; -- register reset
D_IN : in std_logic_vector(WIDTH-1 downto 0); -- register input
D_OUT : out std_logic_vector(WIDTH-1 downto 0)); -- register out
reg(0) <= D_IN;
GEN_Registers : for i in 1 to DEPTH generate
- Registers : process (CLK, RESET)
+ Registers : process (CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
- reg(i) <= (others => '0');
- else
- reg(i) <= reg(i-1);
- end if;
+ reg(i) <= reg(i-1);
end if;
end process Registers;
end generate GEN_Registers;
signal ch_debug_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1);
signal readout_debug_i : std_logic_vector(31 downto 0);
-- Bus signals
- signal status_registers_bus_i : std_logic_vector_array_32(0 to 23);
+ signal status_registers_bus_i : std_logic_vector_array_32(0 to 18);
attribute syn_keep : boolean;
attribute syn_keep of reset_tdc : signal is true;
CLK_200 => CLK_TDC,
CLK_100 => CLK_READOUT,
HIT_IN => hit_in_i(i),
- TRIGGER_IN => '0', -- input for the febex design
+ TRIGGER_WIN_END_IN => trg_win_end_i,
READ_EN_IN => rd_en_i(i),
FIFO_DATA_OUT => ch_data_i(i),
FIFO_WCNT_OUT => ch_wcnt_i(i),
FIFO_ALMOST_FULL_OUT => ch_almost_full_i(i),
COARSE_COUNTER_IN => coarse_cntr(integer(ceil(real(i)/real(16)))),
EPOCH_COUNTER_IN => epoch_cntr,
- DATA_FINISHED_IN => data_finished_i,
+-- DATA_FINISHED_IN => data_finished_i,
LOST_HIT_NUMBER => ch_lost_hit_number_i(i),
HIT_DETECT_NUMBER => ch_hit_detect_number_i(i),
ENCODER_START_NUMBER => ch_encoder_start_number_i(i),
CLK_100 => CLK_READOUT,
RESET_100 => RESET,
RESET_COUNTERS => reset_counters_i,
- HIT_IN => hit_in_i,
REFERENCE_TIME => REFERENCE_TIME,
TRIGGER_TIME_IN => trg_time_i,
TRG_WIN_PRE => TRG_WIN_PRE,
TheStatusRegistersBus : BusHandler
generic map (
- BUS_LENGTH => 23)
+ BUS_LENGTH => 18)
port map (
RESET => RESET,
CLK => CLK_READOUT,
ch_lost_hit_bus_i(i) <= x"00" & ch_lost_hit_number_i(i) when rising_edge(CLK_READOUT);
end generate GenLostHitNumber;
- TheEncoderStartBus : BusHandler
- generic map (
- BUS_LENGTH => CHANNEL_NUMBER-1)
- port map (
- RESET => RESET,
- CLK => CLK_READOUT,
- DATA_IN => ch_encoder_start_bus_i,
- READ_EN_IN => ESB_READ_EN_IN,
- WRITE_EN_IN => ESB_WRITE_EN_IN,
- ADDR_IN => ESB_ADDR_IN,
- DATA_OUT => ESB_DATA_OUT,
- DATAREADY_OUT => ESB_DATAREADY_OUT,
- UNKNOWN_ADDR_OUT => ESB_UNKNOWN_ADDR_OUT);
+ --TheEncoderStartBus : BusHandler
+ -- generic map (
+ -- BUS_LENGTH => CHANNEL_NUMBER-1)
+ -- port map (
+ -- RESET => RESET,
+ -- CLK => CLK_READOUT,
+ -- DATA_IN => ch_encoder_start_bus_i,
+ -- READ_EN_IN => ESB_READ_EN_IN,
+ -- WRITE_EN_IN => ESB_WRITE_EN_IN,
+ -- ADDR_IN => ESB_ADDR_IN,
+ -- DATA_OUT => ESB_DATA_OUT,
+ -- DATAREADY_OUT => ESB_DATAREADY_OUT,
+ -- UNKNOWN_ADDR_OUT => ESB_UNKNOWN_ADDR_OUT);
- GenEncoderStartNumber : for i in 1 to CHANNEL_NUMBER-1 generate
- ch_encoder_start_bus_i(i) <= x"00" & ch_encoder_start_number_i(i) when rising_edge(CLK_READOUT);
- end generate GenEncoderStartNumber;
+ --GenEncoderStartNumber : for i in 1 to CHANNEL_NUMBER-1 generate
+ -- ch_encoder_start_bus_i(i) <= x"00" & ch_encoder_start_number_i(i) when rising_edge(CLK_READOUT);
+ --end generate GenEncoderStartNumber;
- TheEncoderFinishedBus : BusHandler
- generic map (
- BUS_LENGTH => CHANNEL_NUMBER-1)
- port map (
- RESET => RESET,
- CLK => CLK_READOUT,
- DATA_IN => ch_encoder_finished_bus_i,
- READ_EN_IN => EFB_READ_EN_IN,
- WRITE_EN_IN => EFB_WRITE_EN_IN,
- ADDR_IN => EFB_ADDR_IN,
- DATA_OUT => EFB_DATA_OUT,
- DATAREADY_OUT => EFB_DATAREADY_OUT,
- UNKNOWN_ADDR_OUT => EFB_UNKNOWN_ADDR_OUT);
+ ESB_DATA_OUT <= (others => '0');
+ ESB_DATAREADY_OUT <= '0';
+ ESB_UNKNOWN_ADDR_OUT <= '0';
+
+ --TheEncoderFinishedBus : BusHandler
+ -- generic map (
+ -- BUS_LENGTH => CHANNEL_NUMBER-1)
+ -- port map (
+ -- RESET => RESET,
+ -- CLK => CLK_READOUT,
+ -- DATA_IN => ch_encoder_finished_bus_i,
+ -- READ_EN_IN => EFB_READ_EN_IN,
+ -- WRITE_EN_IN => EFB_WRITE_EN_IN,
+ -- ADDR_IN => EFB_ADDR_IN,
+ -- DATA_OUT => EFB_DATA_OUT,
+ -- DATAREADY_OUT => EFB_DATAREADY_OUT,
+ -- UNKNOWN_ADDR_OUT => EFB_UNKNOWN_ADDR_OUT);
+
+ --GenFifoWriteNumber : for i in 1 to CHANNEL_NUMBER-1 generate
+ -- ch_encoder_finished_bus_i(i) <= x"00" & ch_encoder_finished_number_i(i) when rising_edge(CLK_READOUT);
+ --end generate GenFifoWriteNumber;
- GenFifoWriteNumber : for i in 1 to CHANNEL_NUMBER-1 generate
- ch_encoder_finished_bus_i(i) <= x"00" & ch_encoder_finished_number_i(i) when rising_edge(CLK_READOUT);
- end generate GenFifoWriteNumber;
+ EFB_DATA_OUT <= (others => '0');
+ EFB_DATAREADY_OUT <= '0';
+ EFB_UNKNOWN_ADDR_OUT <= '0';
-- Logic Analyser
TheLogicAnalyser : LogicAnalyser
+++ /dev/null
-
-#################################################################
-# TDC Constraints
-#################################################################
-##############################################################################
-## REGION DECLERATION ##
-##############################################################################
-REGION "REGION_UR_CC" "R51C106D" 4 3 DEVSIZE;
-REGION "REGION_LR_CC" "R85C106D" 3 3 DEVSIZE;
-REGION "REGION_UL_CC" "R48C53D" 3 3 DEVSIZE;
-REGION "REGION_LL_CC" "R90C53D" 3 3 DEVSIZE;
-
-
-PROHIBIT SECONDARY NET "THE_TDC/The_Reference_Time/ff_array_en_i";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.*.Channels/Channel_200_1/ff_array_en_i";
-
-
-##############################################################################
-## REFERENCE CHANNEL PLACEMENT ##
-##############################################################################
-UGROUP "Ref_Ch" BBOX 1 51
- BLKNAME THE_TDC/The_Reference_Time/Reference_Channel_200_1/FC;
-LOCATE UGROUP "Ref_Ch" SITE "R8C131D" ;
-UGROUP "ref_hit" BBOX 1 1
- BLKNAME THE_TDC/The_Reference_Time/hit_buf_RNO;
-LOCATE UGROUP "ref_hit" SITE "R9C133D" ;
-UGROUP "Ref_ff_en" BBOX 1 1
- BLKNAME THE_TDC/The_Reference_Time/Reference_Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ;
-
-##############################################################################
-## DELAY LINE and HIT BUFFER PLACEMENTS ##
-##############################################################################
-UGROUP "FC_1" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_1" SITE "R10C131D" ;
-UGROUP "hit_1" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.1.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_1" SITE "R11C133D" ;
-UGROUP "ff_en_1" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel_200_1/ff_array_en_i_RNO;
-LOCATE UGROUP "ff_en_1" SITE "R10C156D" ;
-#
-UGROUP "FC_2" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_2" SITE "R21C131D" ;
-UGROUP "hit_2" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.2.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_2" SITE "R22C133D" ;
-UGROUP "ff_en_2" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_2" SITE "R21C156D" ;
-#
-UGROUP "FC_3" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_3" SITE "R23C131D" ;
-UGROUP "hit_3" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.3.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_3" SITE "R24C133D" ;
-UGROUP "ff_en_3" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_3" SITE "R23C156D" ;
-#
-UGROUP "FC_4" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_4" SITE "R30C131D" ;
-UGROUP "hit_4" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.4.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_4" SITE "R31C133D" ;
-UGROUP "ff_en_4" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_4" SITE "R30C156D" ;
-#
-UGROUP "FC_5" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_5" SITE "R32C131D" ;
-UGROUP "hit_5" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.5.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_5" SITE "R33C133D" ;
-UGROUP "ff_en_5" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_5" SITE "R32C156D" ;
-#
-UGROUP "FC_6" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_6" SITE "R35C131D" ;
-UGROUP "hit_6" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.6.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_6" SITE "R36C133D" ;
-UGROUP "ff_en_6" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_6" SITE "R35C156D" ;
-#
-UGROUP "FC_7" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_7" SITE "R37C131D" ;
-UGROUP "hit_7" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.7.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_7" SITE "R38C133D" ;
-UGROUP "ff_en_7" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_7" SITE "R37C156D" ;
-#
-UGROUP "FC_8" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_8" SITE "R48C131D" ;
-UGROUP "hit_8" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.8.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_8" SITE "R49C133D" ;
-UGROUP "ff_en_8" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_8" SITE "R48C156D" ;
-#
-UGROUP "FC_9" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_9" SITE "R50C131D" ;
-UGROUP "hit_9" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.9.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_9" SITE "R51C133D" ;
-UGROUP "ff_en_9" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_9" SITE "R50C156D" ;
-#
-UGROUP "FC_10" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_10" SITE "R53C131D" ;
-UGROUP "hit_10" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.10.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_10" SITE "R54C133D" ;
-UGROUP "ff_en_10" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_10" SITE "R53C156D" ;
-#
-UGROUP "FC_11" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_11" SITE "R55C131D" ;
-UGROUP "hit_11" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.11.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_11" SITE "R56C133D" ;
-UGROUP "ff_en_11" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_11" SITE "R55C156D" ;
-#
-UGROUP "FC_12" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_12" SITE "R10C58D" ;
-UGROUP "hit_12" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.12.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_12" SITE "R11C60D" ;
-UGROUP "ff_en_12" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_12" SITE "R10C83D" ;
-#
-UGROUP "FC_13" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_13" SITE "R23C58D" ;
-UGROUP "hit_13" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.13.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_13" SITE "R24C60D" ;
-UGROUP "ff_en_13" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_13" SITE "R23C83D" ;
-#
-UGROUP "FC_14" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_14" SITE "R32C58D" ;
-UGROUP "hit_14" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.14.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_14" SITE "R33C60D" ;
-UGROUP "ff_en_14" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_14" SITE "R32C83D" ;
-#
-UGROUP "FC_15" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_15" SITE "R37C58D" ;
-UGROUP "hit_15" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.15.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_15" SITE "R38C60D" ;
-UGROUP "ff_en_15" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_15" SITE "R37C83D" ;
-#
-UGROUP "FC_16" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_16" SITE "R50C58D" ;
-UGROUP "hit_16" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.16.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_16" SITE "R51C60D" ;
-UGROUP "ff_en_16" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_16" SITE "R50C83D" ;
-#
-UGROUP "FC_17" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_17" SITE "R66C131D" ;
-UGROUP "hit_17" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.17.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_17" SITE "R67C133D" ;
-UGROUP "ff_en_17" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_17" SITE "R66C156D" ;
-#
-UGROUP "FC_18" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_18" SITE "R68C131D" ;
-UGROUP "hit_18" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.18.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_18" SITE "R69C133D" ;
-UGROUP "ff_en_18" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_18" SITE "R68C156D" ;
-#
-UGROUP "FC_19" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_19" SITE "R71C131D" ;
-UGROUP "hit_19" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.19.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_19" SITE "R72C133D" ;
-UGROUP "ff_en_19" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_19" SITE "R71C156D" ;
-#
-UGROUP "FC_20" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_20" SITE "R73C131D" ;
-UGROUP "hit_20" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.20.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_20" SITE "R74C133D" ;
-UGROUP "ff_en_20" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_20" SITE "R73C156D" ;
-#
-UGROUP "FC_21" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_21" SITE "R84C131D" ;
-UGROUP "hit_21" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.21.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_21" SITE "R85C133D" ;
-UGROUP "ff_en_21" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_21" SITE "R84C156D" ;
-#
-UGROUP "FC_22" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_22" SITE "R86C131D" ;
-UGROUP "hit_22" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.22.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_22" SITE "R87C133D" ;
-UGROUP "ff_en_22" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_22" SITE "R86C156D" ;
-#
-UGROUP "FC_23" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_23" SITE "R89C131D" ;
-UGROUP "hit_23" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.23.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_23" SITE "R90C133D" ;
-UGROUP "ff_en_23" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_23" SITE "R89C156D" ;
-#
-UGROUP "FC_24" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_24" SITE "R91C131D" ;
-UGROUP "hit_24" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.24.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_24" SITE "R92C133D" ;
-UGROUP "ff_en_24" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_24" SITE "R91C156D" ;
-#
-UGROUP "FC_25" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_25" SITE "R102C131D" ;
-UGROUP "hit_25" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.25.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_25" SITE "R103C133D" ;
-UGROUP "ff_en_25" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_25" SITE "R102C156D" ;
-#
-UGROUP "FC_26" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_26" SITE "R104C131D" ;
-UGROUP "hit_26" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.26.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_26" SITE "R105C133D" ;
-UGROUP "ff_en_26" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_26" SITE "R104C156D" ;
-#
-UGROUP "FC_27" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_27" SITE "R111C131D" ;
-UGROUP "hit_27" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.27.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_27" SITE "R112C133D" ;
-UGROUP "ff_en_27" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_27" SITE "R111C156D" ;
-#
-UGROUP "FC_28" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_28" SITE "R113C131D" ;
-UGROUP "hit_28" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.28.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_28" SITE "R114C133D" ;
-UGROUP "ff_en_28" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_28" SITE "R113C156D" ;
-#
-UGROUP "FC_29" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_29" SITE "R91C58D" ;
-UGROUP "hit_29" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.29.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_29" SITE "R92C60D" ;
-UGROUP "ff_en_29" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_29" SITE "R91C83D" ;
-#
-UGROUP "FC_30" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_30" SITE "R104C58D" ;
-UGROUP "hit_30" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.30.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_30" SITE "R105C60D" ;
-UGROUP "ff_en_30" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_30" SITE "R104C83D" ;
-#
-UGROUP "FC_31" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_31" SITE "R113C58D" ;
-UGROUP "hit_31" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.31.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_31" SITE "R114C60D" ;
-UGROUP "ff_en_31" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_31" SITE "R113C83D" ;
-#
-UGROUP "FC_32" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_32" SITE "R84C58D" ;
-UGROUP "hit_32" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.32.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_32" SITE "R85C60D" ;
-UGROUP "ff_en_32" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_32" SITE "R84C83D" ;
-#
-UGROUP "FC_33" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_33" SITE "R8C58D" ;
-UGROUP "hit_33" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.33.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_33" SITE "R9C60D" ;
-UGROUP "ff_en_33" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_33" SITE "R8C83D" ;
-#
-UGROUP "FC_34" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_34" SITE "R21C58D" ;
-UGROUP "hit_34" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.34.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_34" SITE "R22C60D" ;
-UGROUP "ff_en_34" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_34" SITE "R21C83D" ;
-#
-UGROUP "FC_35" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_35" SITE "R30C58D" ;
-UGROUP "hit_35" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.35.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_35" SITE "R31C60D" ;
-UGROUP "ff_en_35" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_35" SITE "R30C83D" ;
-#
-UGROUP "FC_36" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_36" SITE "R35C58D" ;
-UGROUP "hit_36" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.36.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_36" SITE "R36C60D" ;
-UGROUP "ff_en_36" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_36" SITE "R35C83D" ;
-#
-UGROUP "FC_37" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_37" SITE "R48C58D" ;
-UGROUP "hit_37" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.37.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_37" SITE "R49C60D" ;
-UGROUP "ff_en_37" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_37" SITE "R48C83D" ;
-#
-UGROUP "FC_38" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_38" SITE "R8C2D" ;
-UGROUP "hit_38" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.38.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_38" SITE "R9C4D" ;
-UGROUP "ff_en_38" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_38" SITE "R8C27D" ;
-#
-UGROUP "FC_39" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_39" SITE "R10C2D" ;
-UGROUP "hit_39" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.39.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_39" SITE "R11C4D" ;
-UGROUP "ff_en_39" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_39" SITE "R10C27D" ;
-#
-UGROUP "FC_40" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_40" SITE "R21C2D" ;
-UGROUP "hit_40" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.40.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_40" SITE "R22C4D" ;
-UGROUP "ff_en_40" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_40" SITE "R21C27D" ;
-#
-UGROUP "FC_41" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_41" SITE "R23C2D" ;
-UGROUP "hit_41" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.41.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_41" SITE "R24C4D" ;
-UGROUP "ff_en_41" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_41" SITE "R23C27D" ;
-#
-UGROUP "FC_42" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_42" SITE "R30C2D" ;
-UGROUP "hit_42" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.42.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_42" SITE "R31C4D" ;
-UGROUP "ff_en_42" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_42" SITE "R30C27D" ;
-#
-UGROUP "FC_43" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_43" SITE "R32C2D" ;
-UGROUP "hit_43" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.43.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_43" SITE "R33C4D" ;
-UGROUP "ff_en_43" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_43" SITE "R32C27D" ;
-#
-UGROUP "FC_44" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_44" SITE "R35C2D" ;
-UGROUP "hit_44" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.44.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_44" SITE "R36C4D" ;
-UGROUP "ff_en_44" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_44" SITE "R35C27D" ;
-#
-UGROUP "FC_45" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_45" SITE "R37C2D" ;
-UGROUP "hit_45" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.45.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_45" SITE "R38C4D" ;
-UGROUP "ff_en_45" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_45" SITE "R37C27D" ;
-#
-UGROUP "FC_46" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_46" SITE "R48C2D" ;
-UGROUP "hit_46" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.46.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_46" SITE "R49C4D" ;
-UGROUP "ff_en_46" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_46" SITE "R48C27D" ;
-#
-UGROUP "FC_47" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_47" SITE "R50C2D" ;
-UGROUP "hit_47" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.47.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_47" SITE "R51C4D" ;
-UGROUP "ff_en_47" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_47" SITE "R50C27D" ;
-#
-UGROUP "FC_48" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_48" SITE "R53C2D" ;
-UGROUP "hit_48" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.48.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_48" SITE "R54C4D" ;
-UGROUP "ff_en_48" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_48" SITE "R53C27D" ;
-#
-UGROUP "FC_49" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_49" SITE "R55C2D" ;
-UGROUP "hit_49" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.49.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_49" SITE "R56C4D" ;
-UGROUP "ff_en_49" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_49" SITE "R55C27D" ;
-#
-UGROUP "FC_50" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_50" SITE "R89C58D" ;
-UGROUP "hit_50" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.50.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_50" SITE "R90C60D" ;
-UGROUP "ff_en_50" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_50" SITE "R89C83D" ;
-#
-UGROUP "FC_51" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_51" SITE "R102C58D" ;
-UGROUP "hit_51" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.51.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_51" SITE "R103C60D" ;
-UGROUP "ff_en_51" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_51" SITE "R102C83D" ;
-#
-UGROUP "FC_52" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_52" SITE "R111C58D" ;
-UGROUP "hit_52" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.52.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_52" SITE "R112C60D" ;
-UGROUP "ff_en_52" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_52" SITE "R111C83D" ;
-#
-UGROUP "FC_53" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_53" SITE "R66C2D" ;
-UGROUP "hit_53" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.53.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_53" SITE "R67C4D" ;
-UGROUP "ff_en_53" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_53" SITE "R66C27D" ;
-#
-UGROUP "FC_54" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_54" SITE "R68C2D" ;
-UGROUP "hit_54" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.54.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_54" SITE "R69C4D" ;
-UGROUP "ff_en_54" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_54" SITE "R68C27D" ;
-#
-UGROUP "FC_55" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_55" SITE "R71C2D" ;
-UGROUP "hit_55" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.55.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_55" SITE "R72C4D" ;
-UGROUP "ff_en_55" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_55" SITE "R71C27D" ;
-#
-UGROUP "FC_56" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_56" SITE "R73C2D" ;
-UGROUP "hit_56" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.56.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_56" SITE "R74C4D" ;
-UGROUP "ff_en_56" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_56" SITE "R73C27D" ;
-#
-UGROUP "FC_57" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_57" SITE "R84C2D" ;
-UGROUP "hit_57" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.57.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_57" SITE "R85C4D" ;
-UGROUP "ff_en_57" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_57" SITE "R84C27D" ;
-#
-UGROUP "FC_58" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_58" SITE "R86C2D" ;
-UGROUP "hit_58" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.58.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_58" SITE "R87C4D" ;
-UGROUP "ff_en_58" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_58" SITE "R86C27D" ;
-#
-UGROUP "FC_59" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_59" SITE "R89C2D" ;
-UGROUP "hit_59" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.59.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_59" SITE "R90C4D" ;
-UGROUP "ff_en_59" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_59" SITE "R89C27D" ;
-#
-UGROUP "FC_60" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_60" SITE "R91C2D" ;
-UGROUP "hit_60" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.60.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_60" SITE "R92C4D" ;
-UGROUP "ff_en_60" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_60" SITE "R91C27D" ;
-#
-UGROUP "FC_61" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_61" SITE "R102C2D" ;
-UGROUP "hit_61" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.61.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_61" SITE "R103C4D" ;
-UGROUP "ff_en_61" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_61" SITE "R102C27D" ;
-#
-UGROUP "FC_62" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_62" SITE "R104C2D" ;
-UGROUP "hit_62" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.62.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_62" SITE "R105C4D" ;
-UGROUP "ff_en_62" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_62" SITE "R104C27D" ;
-#
-UGROUP "FC_63" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_63" SITE "R111C2D" ;
-UGROUP "hit_63" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.63.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_63" SITE "R112C4D" ;
-UGROUP "ff_en_63" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_63" SITE "R111C27D" ;
-#
-UGROUP "FC_64" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel_200_1/FC;
-LOCATE UGROUP "FC_64" SITE "R113C2D" ;
-UGROUP "hit_64" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.64.Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_64" SITE "R114C4D" ;
-UGROUP "ff_en_64" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel_200_1/ff_array_en_i_1_i;
-LOCATE UGROUP "ff_en_64" SITE "R113C27D" ;
-
-
-##############################################################################
-## CHANNEL PLACEMENTS ##
-##############################################################################
-UGROUP "E&F_ref" BBOX 6 25
- BLKNAME THE_TDC/The_Reference_Time/Reference_Channel_200_1;
-LOCATE UGROUP "E&F_ref" SITE "R11C131D" ;
-UGROUP "E&F_1" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_1" SITE "R11C156D" ;
-UGROUP "E&F_2" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_2" SITE "R15C131D" ;
-UGROUP "E&F_3" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_3" SITE "R15C156D" ;
-UGROUP "E&F_4" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_4" SITE "R24C131D" ;
-UGROUP "E&F_5" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_5" SITE "R24C156D" ;
-UGROUP "E&F_6" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_6" SITE "R38C131D" ;
-UGROUP "E&F_7" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_7" SITE "R38C156D" ;
-UGROUP "E&F_8" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_8" SITE "R42C131D" ;
-UGROUP "E&F_9" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_9" SITE "R42C156D" ;
-UGROUP "E&F_10" BBOX 6 24
- BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_10" SITE "R56C131D" ;
-UGROUP "E&F_11" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_11" SITE "R56C155D" ;
-UGROUP "E&F_12" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_12" SITE "R11C84D" ;
-UGROUP "E&F_13" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_13" SITE "R15C84D" ;
-UGROUP "E&F_14" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_14" SITE "R24C84D" ;
-UGROUP "E&F_15" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_15" SITE "R38C84D" ;
-UGROUP "E&F_16" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_16" SITE "R42C84D" ;
-UGROUP "E&F_17" BBOX 6 24
- BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_17" SITE "R60C131D" ;
-UGROUP "E&F_18" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_18" SITE "R60C155D" ;
-UGROUP "E&F_19" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_19" SITE "R74C131D" ;
-UGROUP "E&F_20" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_20" SITE "R74C156D" ;
-UGROUP "E&F_21" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_21" SITE "R78C131D" ;
-UGROUP "E&F_22" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_22" SITE "R78C156D" ;
-UGROUP "E&F_23" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_23" SITE "R92C131D" ;
-UGROUP "E&F_24" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_24" SITE "R92C156D" ;
-UGROUP "E&F_25" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_25" SITE "R96C131D" ;
-UGROUP "E&F_26" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_26" SITE "R96C156D" ;
-UGROUP "E&F_27" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_27" SITE "R105C131D" ;
-UGROUP "E&F_28" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_28" SITE "R105C156D" ;
-UGROUP "E&F_29" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_29" SITE "R92C84D" ;
-UGROUP "E&F_30" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_30" SITE "R96C84D" ;
-UGROUP "E&F_31" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_31" SITE "R105C84D" ;
-UGROUP "E&F_32" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_32" SITE "R78C72D" ;
-UGROUP "E&F_33" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_33" SITE "R11C59D" ;
-UGROUP "E&F_34" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_34" SITE "R15C59D" ;
-UGROUP "E&F_35" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_35" SITE "R24C59D" ;
-UGROUP "E&F_36" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_36" SITE "R38C59D" ;
-UGROUP "E&F_37" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_37" SITE "R42C59D" ;
-UGROUP "E&F_38" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_38" SITE "R11C3D" ;
-UGROUP "E&F_39" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_39" SITE "R11C28D" ;
-UGROUP "E&F_40" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_40" SITE "R15C3D" ;
-UGROUP "E&F_41" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_41" SITE "R15C28D" ;
-UGROUP "E&F_42" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_42" SITE "R24C3D" ;
-UGROUP "E&F_43" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_43" SITE "R24C28D" ;
-UGROUP "E&F_44" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_44" SITE "R38C3D" ;
-UGROUP "E&F_45" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_45" SITE "R38C28D" ;
-UGROUP "E&F_46" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_46" SITE "R42C3D" ;
-UGROUP "E&F_47" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_47" SITE "R42C28D" ;
-UGROUP "E&F_48" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_48" SITE "R56C3D" ;
-UGROUP "E&F_49" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_49" SITE "R56C28D" ;
-UGROUP "E&F_50" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_50" SITE "R92C59D" ;
-UGROUP "E&F_51" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_51" SITE "R96C59D" ;
-UGROUP "E&F_52" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_52" SITE "R105C59D" ;
-UGROUP "E&F_53" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_53" SITE "R60C3D" ;
-UGROUP "E&F_54" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_54" SITE "R60C28D" ;
-UGROUP "E&F_55" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_55" SITE "R74C3D" ;
-UGROUP "E&F_56" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_56" SITE "R74C28D" ;
-UGROUP "E&F_57" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_57" SITE "R78C3D" ;
-UGROUP "E&F_58" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_58" SITE "R78C28D" ;
-UGROUP "E&F_59" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_59" SITE "R92C3D" ;
-UGROUP "E&F_60" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_60" SITE "R92C28D" ;
-UGROUP "E&F_61" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_61" SITE "R96C3D" ;
-UGROUP "E&F_62" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_62" SITE "R96C28D" ;
-UGROUP "E&F_63" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_63" SITE "R105C3D" ;
-UGROUP "E&F_64" BBOX 6 25
- BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel_200_1;
-LOCATE UGROUP "E&F_64" SITE "R105C28D" ;
-
-#############################################################################
-## Coarse counter register placement
-
-UGROUP "UR_Coarse_Counter"
- BLKNAME THE_TDC/GenCoarseCounter.1.TheCoarseCounter;
-LOCATE UGROUP "UR_Coarse_Counter" SITE R36C134D; #REGION "REGION_UR_CC" ;
-UGROUP "LR_Coarse_Counter"
- BLKNAME THE_TDC/GenCoarseCounter.2.TheCoarseCounter;
-LOCATE UGROUP "LR_Coarse_Counter" SITE R85C134D; #REGION "REGION_LR_CC" ;
-UGROUP "UL_Coarse_Counter"
- BLKNAME THE_TDC/GenCoarseCounter.3.TheCoarseCounter;
-LOCATE UGROUP "UL_Coarse_Counter" SITE R36C50D; #REGION "REGION_UL_CC" ;
-UGROUP "LL_Coarse_Counter"
- BLKNAME THE_TDC/GenCoarseCounter.4.TheCoarseCounter;
-LOCATE UGROUP "LL_Coarse_Counter" SITE R85C50D; #REGION "REGION_LL_CC" ;
-
-
-
-
-#############################################################################
-## Unimportant Data Lines ##
-#############################################################################
-
-BLOCK NET "THE_TDC/reset_tdc*" ;
-BLOCK NET "THE_TDC/hit_in_i_*" ;
-BLOCK PATH TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel_200_1/FC/FF_*" ;
-BLOCK NET "THE_TDC/reset_counters_200*" ;
-
-MAXDELAY NET "THE_TDC/The_Reference_Time/hit_buf" 0.600000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels.*.Channels/hit_buf" 0.600000 nS DATAPATH_ONLY ;
-
-
-MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter[*]" TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel_200_1/epoch_cntr[*]" 5.000000 X;
-MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter[*]" TO CELL "THE_TDC/The_Reference_Time/Reference_Channel_200_1/epoch_cntr[*]" 5.000000 X;
-#MULTICYCLE FROM CELL "THE_TDC/The_Reference_Time/Reference_Channel_200_1/FIFO_ALMOST_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg_*" 2.000000 X;
-MULTICYCLE FROM CELL "THE_TDC/The_Reference_Time/Reference_Channel_200_1/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg_*" 2.000000 X;
-MULTICYCLE FROM CELL "THE_TDC/GEN_Channels.*.Channels/Channel_200_1/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg*" 2.000000 X;
-#MULTICYCLE FROM CELL "THE_TDC/GEN_Channels.*.Channels/Channel_200_1/FIFO_ALMOST_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg*" 2.000000 X;
-
jspc29 / trb3.git / commitdiff