\begin{document}
\title{Implementation of the FPGA-based cluster finder for the CBM-MVD\thanks{Work supported by BMBF (05P12RFFC7), HIC for FAIR, and GSI.}}
-\author[]{Qiyan Li}
-\author[]{S. Amar-Youcef}
-\author[]{M. Deveaux}
-\author[]{I. Fröhlich}
-\author[]{B. Milanovic}
-\author[]{J. Michel}
-\author[]{C. Müntz}
-\author[]{J.Stroth for the CBM-MVD Collaboration}
+\author[1]{Qiyan Li}
+\author[1]{S. Amar-Youcef}
+\author[1]{M. Deveaux}
+\author[1]{I. Fröhlich}
+\author[1]{B. Milanovic}
+\author[1]{J. Michel}
+\author[1]{C. Müntz}
+\author[1,2]{J.Stroth}
+\author[]{the CBM-MVD Collaboration}
-
-\affil[]{IKF, Goethe-University Frankfurt, Germany}
+\affil[1]{IKF, Goethe-University Frankfurt, Germany}
+\affil[2]{GSI, Darmstadt, Germany}
\maketitle
%\section{}
-Searching for open charm particles with CBM demands for high collision rates of $\sim$ 100 kHz Au+Au collisions and for performing tracking and secondary decay vertex finding in real time. This generates a significant load to the First Level Event Selector (FLES) of the experiment. To reduce this load, we aim to pre-process the data provided by the Micro-Vertex-Detector (MVD) of CBM before sending it to the FLES.
+Searching for open charm particles with CBM demands high collision rates of up to 100\ kHz Au+Au collisions and performing tracking and secondary decay vertex finding in real time. This generates a significant load to the First Level Event Selector (FLES) of the experiment. To reduce this load, we aim at pre-processing the data provided by the Micro-Vertex-Detector (MVD) of CBM before sending it to the FLES.
-Our strategy was studied with the CMOS Monolithic Active Pixel Sensor MIMOSA-26, which features already an on-chip zero suppression and an 1-dimensional cluster finding. To reduce the data further, we implemented and tested algorithms performing a 2-dimensional cluster finding and a more efficient cluster encoding [1]. Based on data obtained from the beam test of the MVD-prototype, we concluded that 99.99\% of all clusters can be encoded, if the most abundant cluster shapes are associated to a 10-bit code. This so-called shape code is packed together whith the x- and y-coordinate of the cluster into 32-bit word. As shown in figure 1, which displays the data volume needed to encode a sensor frame in multiples of 16 bit, the novel
+Our strategy was studied with the CMOS Monolithic Active Pixel Sensor MIMOSA-26, which features already an on-chip zero suppression and an 1-dimensional cluster finding. To further reduce the data, we implemented and tested algorithms performing a 2-dimensional cluster finding and an efficient cluster encoding [1]. Based on data obtained from the beam test of the MVD-prototype, we concluded that 99.99\% of all found cluster types can be encoded, if the most abundant cluster shapes are associated to a 10-bit code. This so-called shape code is packed together whith the x- and y-coordinate of the cluster into 32-bit word. As shown in figure 1, which displays the data volume needed to encode a sensor frame in multiples of 16 bit, the novel
encoding scheme reduces the data by a factor of two as compared to the native encoding of MIMOSA-26. Moreover, the fluctuations are reduced, which helps to balance the load of the readout network.
\begin{figure}[htb]
\centering
%\includegraphics*[width=65mm]{gsisr1}
\includegraphics*[width=65mm]{dataCompression.png}
-\caption{Comparison of the data volume generated by SPS beam test data encoded in proposed format and native data format of MIMOSA-26.}
+\caption{Comparison of the data volume generated by SPS beam test data encoded in proposed format and the native data format of MIMOSA-26. The average cluster size is between 1 and 2 pixels per cluster. }
\label{l2ea4-f1}
\end{figure}
-The algorithms are being implemented into the FPGA of the readout controller board (ROC) of the MVD. Figure 2 (left) shows the modules of the current ROC logic.After the sensors’ data are cross-checked for possible errors and synchronization problems, they are stored in a frame buffer, which serves as the input for the cluster finder. The output of this cluster finder is transferred to a readout buffer and shipped forward via TRB-net. Figure 2(right) displays the main logic structure of the cluster finder. The data of each new row arriving at the \emph{Read Row} - module are compared with the potentially incomplete clusters known from previous rows. In case a new state matches geometrically a known cluster, it is added to this cluster. Otherwise, a new cluster is created. Once a cluster does not find new neighbors, it is considered as completed and sent to the \emph{Shape} and \emph{Cluster Coder}-module. Here, the cluster is encoded into the final 32-bit word by means of a look-up table.
+The algorithms are being implemented into the FPGA of the readout controller board (ROC) of the MVD. Figure 2 (left) shows the modules of the current ROC logic. After the sensors’ data are cross-checked for possible errors and synchronization problems, they are stored in a frame buffer, which serves as the input for the cluster finder. The output of this cluster finder is transferred to a readout buffer and shipped forward via TRB-net. Figure 2 (right) displays the main logic structure of the cluster finder. The data of each new row arriving at the \emph{Read Row} - module are compared with the potentially incomplete clusters known from previous rows. In case a new state matches geometrically a known cluster, it is added to this cluster. Otherwise, a new cluster is created. Once a cluster does not find new neighbors, it is considered as completed and sent to the \emph{Shape} and \emph{Cluster Coder}-module. Here, the cluster is encoded into the final 32-bit word by means of a look-up table.
To accelerate the encoding, a \emph{fast coder} encodes the 8 most abundant shapes and all fully symmetrical shapes without accessing the table. Moreover, the \emph{look-up table} was subdivided into groups of shapes with identical numbers of fired pixels and each group was ordered such that the most abundant cluster shape is encoded with shortest access times. According to our FPGA-simulations, this optimization accelerated the access by a factor of two.
\begin{figure}[ht]
\centering
%\includegraphics*[width=65mm]{gsisr1}
\includegraphics*[width=82mm]{DAQ-FPGA.png}
-\caption{ Main modules of ROC logic(left), logic structure of the cluster finder(right).}
+\caption{ Main modules of ROC logic (left), logic structure of the cluster finder (right).}
\label{l2ea4-f1}
\end{figure}
-A first version of the VHDL code was implemented in the FPGA on the TRBv2-board and tested with test patterns. The algorithm recognized the patterns within the anticipated processing time. In a next step, the code will be exposed to real data and finally integrated into the real time data processing chain of the TRBv3-board[2], which are foreseen as ROCs of the MVD.
-
-
+A first version of the VHDL code was implemented in the FPGA on the TRBv2-board and tested with test patterns. The algorithm recognized the patterns within the anticipated processing time. In a next step, the code will be exposed to real data and finally integrated into the real time data processing chain of the TRBv3-board [2,3].
\begin{thebibliography}{9} % Use for 1-9 references
%\begin{thebibliography}{99} % Use for 10-99 references
\bibitem{}
-Q. Li and the CBM-MVD Collaboration, "Online data processing with CBM-MVD prototype",GSI Scientific Report 2012 6
+Q. Li et al., GSI Scientific Report 2012
\bibitem {Paper:TRB-Board}M. Traxler et al., 2011 JINST 6 C12004
-
+\bibitem {} J. Michel et al., this report
\end{thebibliography}
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