--- /dev/null
+-- the full endpoint for HADES: trg, data, unused, regio including data buffer & handling
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+
+entity trb_net16_endpoint_hades_full_handler is
+ generic (
+ IBUF_DEPTH : channel_config_t := (6,6,6,6);
+ FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);
+ FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1);
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
+ REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0');
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100;
+ --Configure data handler
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8;
+ TRG_RELEASE_AFTER_DATA_FINISH: integer range 0 to 1 := c_YES;
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8;
+ --RegIO Bus Handler
+ PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 1;
+ PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0'));
+ PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0)
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic := '1';
+
+ -- Media direction port
+ MED_DATAREADY_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic;
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic;
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN : in std_logic;
+ --LVL1 trigger to FEE
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid
+ LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received
+ LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received
+ LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only
+
+ --Response from FEE
+ FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+
+ --Slow Control Port
+ --common registers
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);
+ REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);
+ --user defined registers
+ REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');
+ REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
+ REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+ REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ --internal data port
+ BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0);
+ BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_DATA_IN : in std_logic_vector(PORT_NUMBER*32-1 downto 0) := (others => '0');
+ BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0');
+ BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0');
+ BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0');
+ BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0');
+ --Onewire
+ ONEWIRE_INOUT : inout std_logic; --temperature sensor
+ ONEWIRE_MONITOR_IN : in std_logic := '0';
+ ONEWIRE_MONITOR_OUT : out std_logic;
+ --Config endpoint id, if not statically assigned
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0');
+
+ --Timing registers
+ TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds
+ TIME_LOCAL_OUT : out std_logic_vector ( 7 downto 0); --local time running with chip frequency
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger
+ TIME_TICKS_OUT : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick
+
+ --Debugging & Status information
+ STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);
+ STAT_DEBUG_1 : out std_logic_vector (31 downto 0);
+ STAT_DEBUG_2 : out std_logic_vector (31 downto 0);
+ STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0);
+ STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0);
+ CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');
+ IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');
+ STAT_ONEWIRE : out std_logic_vector (31 downto 0);
+ STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0)
+ );
+end entity;
+
+
+
+
+
+architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_hades_full_handler is
+
+ signal lvl1_data_valid_i : std_logic;
+ signal lvl1_valid_timing_i : std_logic;
+ signal lvl1_valid_notiming_i : std_logic;
+ signal lvl1_invalid_i : std_logic;
+ signal lvl1_type_i : std_logic_vector ( 3 downto 0);
+ signal lvl1_number_i : std_logic_vector (15 downto 0);
+ signal lvl1_code_i : std_logic_vector ( 7 downto 0);
+ signal lvl1_information_i : std_logic_vector (23 downto 0);
+ signal lvl1_error_pattern_i : std_logic_vector (31 downto 0);
+ signal lvl1_release_i : std_logic;
+ signal lvl1_int_trg_number_i : std_logic_vector (15 downto 0);
+
+ signal ipu_number_i : std_logic_vector (15 downto 0);
+ signal ipu_readout_type_i : std_logic_vector ( 3 downto 0);
+ signal ipu_information_i : std_logic_vector ( 7 downto 0);
+ signal ipu_start_readout_i : std_logic;
+ signal ipu_data_i : std_logic_vector (31 downto 0);
+ signal ipu_dataready_i : std_logic;
+ signal ipu_readout_finished_i : std_logic;
+ signal ipu_read_i : std_logic;
+ signal ipu_length_i : std_logic_vector (15 downto 0);
+ signal ipu_error_pattern_i : std_logic_vector (31 downto 0);
+
+ signal common_stat_reg_i : std_logic_vector (std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg_i : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
+ signal common_stat_strobe_i : std_logic_vector (std_COMSTATREG-1 downto 0);
+ signal common_ctrl_strobe_i : std_logic_vector (std_COMCTRLREG-1 downto 0);
+ signal stat_reg_i : std_logic_vector (2**(REGIO_NUM_STAT_REGS)*32-1 downto 0);
+ signal ctrl_reg_i : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
+ signal stat_strobe_i : std_logic_vector (2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+ signal ctrl_strobe_i : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+
+ signal regio_addr_i : std_logic_vector (15 downto 0);
+ signal regio_read_enable_i : std_logic;
+ signal regio_write_enable_i : std_logic;
+ signal regio_data_out_i : std_logic_vector (31 downto 0);
+ signal regio_data_in_i : std_logic_vector (31 downto 0);
+ signal regio_dataready_i : std_logic;
+ signal regio_nomoredata_i : std_logic;
+ signal regio_write_ack_i : std_logic;
+ signal regio_unknown_addr_i : std_logic;
+ signal regio_timeout_i : std_logic;
+
+ signal time_global_i : std_logic_vector (31 downto 0);
+ signal time_local_i : std_logic_vector ( 7 downto 0);
+ signal time_since_last_trg_i : std_logic_vector (31 downto 0);
+ signal time_ticks_i : std_logic_vector ( 1 downto 0);
+
+ signal stat_handler_i : std_logic_vector (127 downto 0);
+
+
+begin
+---------------------------------------------------------------------------
+-- TrbNet Endpoint
+---------------------------------------------------------------------------
+
+ THE_ENDPOINT: trb_net16_endpoint_hades_full
+ generic map(
+ IBUF_DEPTH => IBUF_DEPTH,
+ FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
+ APL_WRITE_ALL_WORDS => APL_WRITE_ALL_WORDS,
+ ADDRESS_MASK => ADDRESS_MASK,
+ BROADCAST_BITMASK => BROADCAST_BITMASK,
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS,
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,
+ REGIO_INIT_CTRL_REGS => REGIO_INIT_CTRL_REGS,
+ REGIO_INIT_ADDRESS => REGIO_INIT_ADDRESS,
+ REGIO_INIT_BOARD_INFO => REGIO_INIT_BOARD_INFO,
+ REGIO_INIT_ENDPOINT_ID => REGIO_INIT_ENDPOINT_ID,
+ REGIO_COMPILE_TIME => REGIO_COMPILE_TIME,
+ REGIO_COMPILE_VERSION => REGIO_COMPILE_VERSION,
+ REGIO_HARDWARE_VERSION => REGIO_HARDWARE_VERSION,
+ REGIO_USE_1WIRE_INTERFACE => REGIO_USE_1WIRE_INTERFACE,
+ REGIO_USE_VAR_ENDPOINT_ID => REGIO_USE_VAR_ENDPOINT_ID,
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_STAT_OP_IN => MED_STAT_OP,
+ MED_CTRL_OP_OUT => MED_CTRL_OP,
+
+ -- LVL1 trigger APL
+ TRG_TIMING_TRG_RECEIVED_IN => TRG_TIMING_TRG_RECEIVED_IN,
+ LVL1_TRG_DATA_VALID_OUT => lvl1_data_valid_i,
+ LVL1_TRG_VALID_TIMING_OUT => lvl1_valid_timing_i,
+ LVL1_TRG_VALID_NOTIMING_OUT=> lvl1_valid_notiming_i,
+ LVL1_TRG_INVALID_OUT => lvl1_invalid_i,
+ LVL1_TRG_TYPE_OUT => lvl1_type_i,
+ LVL1_TRG_NUMBER_OUT => lvl1_number_i,
+ LVL1_TRG_CODE_OUT => lvl1_code_i,
+ LVL1_TRG_INFORMATION_OUT => lvl1_information_i,
+ LVL1_ERROR_PATTERN_IN => lvl1_error_pattern_i,
+ LVL1_TRG_RELEASE_IN => lvl1_release_i,
+ LVL1_INT_TRG_NUMBER_OUT => lvl1_int_trg_number_i,
+
+ --Data Port
+ IPU_NUMBER_OUT => ipu_number_i,
+ IPU_READOUT_TYPE_OUT => ipu_readout_type_i,
+ IPU_INFORMATION_OUT => ipu_information_i,
+ IPU_START_READOUT_OUT => ipu_start_readout_i,
+ IPU_DATA_IN => ipu_data_i,
+ IPU_DATAREADY_IN => ipu_dataready_i,
+ IPU_READOUT_FINISHED_IN => ipu_readout_finished_i,
+ IPU_READ_OUT => ipu_read_i,
+ IPU_LENGTH_IN => ipu_length_i,
+ IPU_ERROR_PATTERN_IN => ipu_error_pattern_i,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg_i,
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg_i,
+ REGIO_REGISTERS_IN => stat_reg_i,
+ REGIO_REGISTERS_OUT => ctrl_reg_i,
+ COMMON_STAT_REG_STROBE => common_stat_strobe_i,
+ COMMON_CTRL_REG_STROBE => common_ctrl_strobe_i,
+ STAT_REG_STROBE => stat_strobe_i,
+ CTRL_REG_STROBE => ctrl_strobe_i,
+
+ REGIO_ADDR_OUT => regio_addr_i,
+ REGIO_READ_ENABLE_OUT => regio_read_enable_i,
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_i,
+ REGIO_DATA_OUT => regio_data_out_i,
+ REGIO_DATA_IN => regio_data_in_i,
+ REGIO_DATAREADY_IN => regio_dataready_i,
+ REGIO_NO_MORE_DATA_IN => regio_nomoredata_i,
+ REGIO_WRITE_ACK_IN => regio_write_ack_i,
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_i,
+ REGIO_TIMEOUT_OUT => regio_timeout_i,
+
+ REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT,
+ REGIO_ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,
+ REGIO_ONEWIRE_MONITOR_OUT => ONEWIRE_MONITOR_OUT,
+ REGIO_VAR_ENDPOINT_ID => REGIO_VAR_ENDPOINT_ID,
+
+ GLOBAL_TIME_OUT => time_global_i,
+ LOCAL_TIME_OUT => time_local_i,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg_i,
+ TIMER_TICKS_OUT => time_ticks_i,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ MED_STAT_OP => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- RegIO Bus Handler
+---------------------------------------------------------------------------
+
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => PORT_NUMBER,
+ PORT_ADDRESSES => PORT_ADDRESSES,
+ PORT_ADDR_MASK => PORT_ADDR_MASK
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ DAT_ADDR_IN => regio_addr_i,
+ DAT_DATA_IN => regio_data_out_i,
+ DAT_DATA_OUT => regio_data_in_i,
+ DAT_READ_ENABLE_IN => regio_read_enable_i,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_i,
+ DAT_TIMEOUT_IN => regio_timeout_i,
+ DAT_DATAREADY_OUT => regio_dataready_i,
+ DAT_WRITE_ACK_OUT => regio_write_ack_i,
+ DAT_NO_MORE_DATA_OUT => regio_nomoredata_i,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_i,
+
+ BUS_READ_ENABLE_OUT => BUS_READ_ENABLE_OUT,
+ BUS_WRITE_ENABLE_OUT => BUS_WRITE_ENABLE_OUT,
+ BUS_DATA_OUT => BUS_DATA_OUT,
+ BUS_ADDR_OUT => BUS_ADDR_OUT,
+ BUS_TIMEOUT_OUT => BUS_TIMEOUT_OUT,
+ BUS_DATA_IN => BUS_DATA_IN,
+ BUS_DATAREADY_IN => BUS_DATAREADY_IN,
+ BUS_WRITE_ACK_IN => BUS_WRITE_ACK_IN,
+ BUS_NO_MORE_DATA_IN => BUS_NO_MORE_DATA_IN,
+ BUS_UNKNOWN_ADDR_IN => BUS_UNKNOWN_ADDR_IN
+ );
+
+---------------------------------------------------------------------------
+-- Data and IPU Handler
+---------------------------------------------------------------------------
+
+ THE_HANDLER_TRIGGER_DATA : handler_trigger_and_data
+ generic map(
+ DATA_INTERFACE_NUMBER => DATA_INTERFACE_NUMBER,
+ DATA_BUFFER_DEPTH => DATA_BUFFER_DEPTH,
+ DATA_BUFFER_WIDTH => DATA_BUFFER_WIDTH,
+ DATA_BUFFER_FULL_THRESH => DATA_BUFFER_FULL_THRESH,
+ TRG_RELEASE_AFTER_DATA => TRG_RELEASE_AFTER_DATA,
+ HEADER_BUFFER_DEPTH => HEADER_BUFFER_DEPTH,
+ HEADER_BUFFER_FULL_THRESH => HEADER_BUFFER_FULL_THRESH,
+ )
+ port map(
+ CLOCK => CLOCK,
+ RESET => RESET,
+
+ --LVL1 channel
+ LVL1_VALID_TRIGGER_IN => lvl1_valid_i,
+ LVL1_INT_TRG_NUMBER_IN => lvl1_int_trg_number_i,
+ LVL1_TRG_DATA_VALID_IN => lvl1_data_valid_i,
+ LVL1_TRG_TYPE_IN => lvl1_type_i,
+ LVL1_TRG_NUMBER_IN => lvl1_number_i,
+ LVL1_TRG_CODE_IN => lvl1_code_i,
+ LVL1_TRG_INFORMATION_IN => lvl1_information_i,
+ LVL1_ERROR_PATTERN_OUT => lvl1_error_pattern_i,
+ LVL1_TRG_RELEASE_OUT => lvl1_release_i,
+
+ --IPU channel
+ IPU_NUMBER_IN => ipu_number_i,
+ IPU_INFORMATION_IN => ipu_information_i,
+ IPU_READOUT_TYPE_IN => ipu_readout_type_i,
+ IPU_START_READOUT_IN => ipu_start_readout_i,
+ IPU_DATA_OUT => ipu_data_i,
+ IPU_DATAREADY_OUT => ipu_dataready_i,
+ IPU_READOUT_FINISHED_OUT => ipu_readout_finished_i,
+ IPU_READ_IN => ipu_read_i,
+ IPU_LENGTH_OUT => ipu_length_i,
+ IPU_ERROR_PATTERN_OUT => ipu_error_pattern_i,
+
+ --FEE Input
+ FEE_TRG_RELEASE_IN => FEE_TRG_RELEASE_IN,
+ FEE_TRG_STATUSBITS_IN => FEE_TRG_STATUSBITS_IN,
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATA_WRITE_IN => FEE_DATA_WRITE_IN,
+ FEE_DATA_FINISHED_IN => FEE_DATA_FINISHED_IN,
+ FEE_DATA_ALMOST_FULL_OUT => FEE_DATA_ALMOST_FULL_OUT,
+
+ --Status Registers
+ STATUS_OUT => stat_handler_i;
+
+ --Debug
+ DEBUG_DATA_HANDLER_OUT => DEBUG_DATA_HANDLER_OUT,
+ DEBUG_IPU_HANDLER_OUT => DEBUG_IPU_HANDLER_OUT
+
+ );
+
+ lvl1_valid_i <= lvl1_valid_timing_i or lvl1_valid_notiming_i;
+
+---------------------------------------------------------------------------
+-- Connect I/O Ports
+---------------------------------------------------------------------------
+
+ LVL1_TRG_DATA_VALID_OUT <= lvl1_data_valid_i;
+ LVL1_VALID_TIMING_TRG_OUT <= lvl1_valid_timing_i;
+ LVL1_VALID_NOTIMING_TRG_OUT <= lvl1_valid_notiming_i;
+ LVL1_INVALID_TRG_OUT <= lvl1_invalid_i;
+ LVL1_TRG_TYPE_OUT <= lvl1_type_i;
+ LVL1_TRG_NUMBER_OUT <= lvl1_number_i;
+ LVL1_TRG_CODE_OUT <= lvl1_code_i;
+ LVL1_TRG_INFORMATION_OUT <= lvl1_information_i;
+ LVL1_INT_TRG_NUMBER_OUT <= lvl1_int_trg_number_i;
+
+ REGIO_COMMON_CTRL_REG_OUT <= common_ctrl_reg_i;
+ REGIO_COMMON_STAT_STROBE_OUT <= common_stat_strobe_i;
+ REGIO_COMMON_CTRL_STROBE_OUT <= common_ctrl_strobe_i;
+ REGIO_CTRL_REG_OUT <= ctrl_reg_i;
+ REGIO_STAT_STROBE_OUT <= stat_strobe_i;
+ REGIO_CTRL_STROBE_OUT <= ctrl_strobe_i;
+
+ common_stat_reg_i <= REGIO_COMMON_STAT_REG_IN;
+ stat_reg_i <= REGIO_STAT_REG_IN;
+
+ TIME_GLOBAL_OUT <= time_global_i;
+ TIME_LOCAL_OUT <= time_local_i;
+ TIME_SINCE_LAST_TRG_OUT <= time_since_last_trg_i;
+ TIME_TICKS_OUT <= time_ticks_i;
+
+end architecture;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff