add long reset signal for i2c bus

diff --git a/special/trb_net_i2cwire.vhd b/special/trb_net_i2cwire.vhd
index 268ac4cc8e7b66cc0ad11484e247b2e58ff36f40..6d15a2697f44b11acf8b44d260dee48a6700cfc8 100644 (file)
--- a/special/trb_net_i2cwire.vhd
+++ b/special/trb_net_i2cwire.vhd
@@ -32,7 +32,7 @@ end trb_net_i2cwire;
 architecture trb_net_i2cwire_arch of trb_net_i2cwire is\r
 \r
   -- States\r
-  type FSM_STATES is (SLEEP, IDLE, RD_ID0, ST_ID0, RD_ID1, ST_ID1, RD_ID2, ST_ID2, WR_TMP, RD_TMP, ST_TMP, ID_DONE);\r
+  type FSM_STATES is (SLEEP, I2C_RESET, IDLE, RD_ID0, ST_ID0, RD_ID1, ST_ID1, RD_ID2, ST_ID2, WR_TMP, RD_TMP, ST_TMP, ID_DONE);\r
   signal CURRENT_STATE, NEXT_STATE: FSM_STATES;\r
 \r
   -- Signals\r
@@ -71,6 +71,7 @@ architecture trb_net_i2cwire_arch of trb_net_i2cwire is
 \r
   signal sda_drv            : std_logic;\r
   signal scl_drv            : std_logic;\r
+  signal scl_reset, scl_reset_x : std_logic;\r
   \r
   -- Components\r
   component i2c_slim is\r
@@ -114,11 +115,13 @@ begin
       ram_we        <= '0';\r
       temp_we       <= '0';\r
       i2c_go        <= '0';\r
+      scl_reset     <= '1';\r
     else\r
       CURRENT_STATE <= NEXT_STATE;\r
       ram_we        <= ram_we_x;\r
-      temp_we        <= temp_we_x;\r
+      temp_we       <= temp_we_x;\r
       i2c_go        <= i2c_go_x;\r
+      scl_reset     <= scl_reset_x;\r
     end if;\r
   end if;\r
 end process STATE_MEM;\r
@@ -132,6 +135,7 @@ begin
   temp_we_x <= '0';\r
   addr_int <= b"011";\r
   i2c_go_x <= '0';\r
+  scl_reset_x <= '0';\r
 \r
   i2c_action_int <= '1';\r
   i2c_word_int   <= '1';\r
@@ -141,11 +145,18 @@ begin
 \r
   case CURRENT_STATE is\r
     when SLEEP    =>\r
+      scl_reset_x <= '1';\r
       if( READOUT_ENABLE_IN = '1' ) then\r
-        NEXT_STATE <= IDLE;\r
+        NEXT_STATE <= I2C_RESET;\r
         rst_tc_x   <= '1';\r
         ram_we_x   <= '1';\r
       end if;\r
+    when I2C_RESET =>\r
+      scl_reset_x <= '1';\r
+      if( is_time_reached(timecounter,IDLE_PERIOD,CLK_PERIOD) = '1' ) then\r
+        NEXT_STATE  <= IDLE;\r
+        rst_tc_x    <= '1';\r
+      end if;  \r
     when IDLE      =>\r
       if( is_time_reached(timecounter,IDLE_PERIOD,CLK_PERIOD) = '1' ) then\r
         NEXT_STATE <= RD_ID0;\r
@@ -349,7 +360,7 @@ port map(
 \r
 -- I2C signal open collector driver\r
 SDA_INOUT <= '0' when (sda_drv = '0') else 'Z';\r
-SCL_INOUT <= '0' when (scl_drv = '0') else 'Z';\r
+SCL_INOUT <= '0' when (scl_drv = '0' or scl_reset = '1') else 'Z';\r
 \r
 ADDR_OUT  <= addr_int;\r
 DATA_OUT  <= i2c_dr_int;\r
@@ -358,11 +369,10 @@ WRITE_OUT <= ram_we;
 ID_OUT    <= id_int;\r
 TEMP_OUT  <= temp_int;\r
 \r
-STAT(31 downto 25) <= (others => '0');\r
-STAT(24)           <= sda_drv;\r
-STAT(23 downto 21) <= (others => '0');\r
+STAT(31 downto 22) <= (others => '0');\r
+STAT(21)           <= sda_drv;\r
 STAT(20)           <= scl_drv;\r
-STAT(19)           <= '0';\r
+STAT(19)           <= scl_reset;\r
 STAT(18)           <= i2c_done_int;\r
 STAT(17)           <= i2c_busy_int;\r
 STAT(16)           <= i2c_go;\r