# Basic Settings
#################################################################
-FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
-FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
-
-# to be checked...
-FREQUENCY NET "med2int_0.clk_full" 200 MHz;
-
+# Clocks
+FREQUENCY NET "clk_sys" 100.000 MHz;
+FREQUENCY NET "CLK_125_c" 125.000 MHz;
+FREQUENCY NET "GBE/physical/gbe_serdes/tx_pclk" 125.000 MHz;
+FREQUENCY NET "GBE/physical/CLK_125_RX_OUT" 125.000 MHz;
+
BLOCK PATH TO PORT "LED*";
BLOCK PATH TO PORT "PROGRAMN";
-BLOCK PATH TO PORT "TEMP_LINE";
-BLOCK PATH FROM PORT "TEMP_LINE";
-BLOCK PATH TO PORT "TEST_LINE*";
-
-MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
-MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
-
-## read from SCI can be delayed due to long read strobe
-#MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
-## write strobe can be delayed due to A/D being stable after access
-#MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
-
-GSR_NET NET "clear_i";
-
-REGION "MEDIA" "R81C44D" 13 25;
-LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
+BLOCK PATH TO PORT "GPIO*";
+BLOCK PATH TO PORT "INT_COM*";
-- LED
-------------------------------------------------------------------------------
LED_SFP_GREEN <= not (status(0) and status(1) and status(2)); --'0';
- LED_SFP_YELLOW <= not (status(3) and status(4)); --'0';
+ LED_SFP_YELLOW <= not (status(3) or status(4)); --'0';
LED_SFP_RED <= not '0';
LED(3) <= not '0';
LED(2) <= not '0';