Updating dirich lpf

diff --git a/dirich/dirich.lpf b/dirich/dirich.lpf
index 7765bf4c7ed5d29109a9843e22e84e238f33abfc..303b227f20e465b67fd70e8134c2ba443fc20ac7 100644 (file)
--- a/dirich/dirich.lpf
+++ b/dirich/dirich.lpf
@@ -15,6 +15,9 @@ BANK 8 VCCIO 3.3 V;
 
 
 FREQUENCY PORT CLOCK_IN        240 MHz;
+FREQUENCY PORT CLOCK_CAL       33 MHz;
+
+
 
 
 BLOCK PATH TO   PORT "LED*";

diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd
index f1a182ce1c3c66a50b923177001e20ca0566f514..3da0d3adaaf2c35b0be51bfa34e1290b8c005187 100644 (file)
--- a/dirich/dirich.vhd
+++ b/dirich/dirich.vhd
@@ -14,20 +14,20 @@ entity dirich is
   port(
     CLOCK_IN        : in    std_logic; --Main Oscillator
     TRIG_IN         : in    std_logic; --Reference Time
-    CLOCK_CAL_IN    : in    std_logic; --on-board calibration oscillator
+    CLOCK_CAL       : in    std_logic; --on-board calibration oscillator
     
     INPUT                : in    std_logic_vector(32 downto 1);
     PWM                  : out   std_logic_vector(32 downto 1);
     
     --Additional IO
-    COM                  : inout std_logic_vector( 6 downto 1);
+    SIG                  : inout std_logic_vector( 6 downto 1);
     --LED
     LED_GREEN            : out   std_logic;
     LED_YELLOW           : out   std_logic;
     LED_ORANGE           : out   std_logic;
     LED_RED              : out   std_logic;
     --ADC
-    ADC_CLK              : out   std_logic;
+    ADC_SCLK             : out   std_logic;
     ADC_CS               : out   std_logic;
     ADC_DIN              : out   std_logic;
     ADC_DOUT             : in    std_logic;
@@ -163,8 +163,8 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
 --       CTRL_DEBUG     => open
 --       );
 
-COM(2) <= '0' when link_stat_out = '1' else 'Z';
-link_stat_in <= COM(1);
+SIG(2) <= '0' when link_stat_out = '1' else 'Z';
+link_stat_in <= SIG(1);
       
 ---------------------------------------------------------------------------
 -- Endpoint
@@ -274,11 +274,11 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
       ADC_CS      => ADC_CS,
       ADC_MOSI    => ADC_DIN,
       ADC_MISO    => ADC_DOUT,
-      ADC_CLK     => ADC_CLK,
+      ADC_CLK     => ADC_SCLK,
       --Trigger & Monitor 
       MONITOR_INPUTS   => INPUT,
       TRIG_GEN_INPUTS  => INPUT,
-      TRIG_GEN_OUTPUTS => COM(4 downto 3),
+      TRIG_GEN_OUTPUTS => SIG(4 downto 3),
       --SED
       SED_ERROR_OUT => sed_error_i,
       --Slowcontrol
@@ -334,13 +334,13 @@ THE_PWM_GEN : entity work.pwm_generator
 ---------------------------------------------------------------------------
 -- Test Circuits
 ---------------------------------------------------------------------------
-  process begin
-    wait until rising_edge(clk_sys);
-    time_counter <= time_counter + 1; 
-    if reset_i = '1' then
-      time_counter <= (others => '0');
-    end if;
-  end process;  
+--   process begin
+--     wait until rising_edge(clk_sys);
+--     time_counter <= time_counter + 1; 
+--     if reset_i = '1' then
+--       time_counter <= (others => '0');
+--     end if;
+--   end process;  
 
 --   TEST_LINE <= med_stat_debug(15 downto 0);
   

diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf
index 4c176c3bb541c8b3998fb6548142d31b436f241a..55602ccbf316315b1a3a5415e72e76afbaed97b8 100644 (file)
--- a/pinout/dirich.lpf
+++ b/pinout/dirich.lpf
@@ -1,39 +1,40 @@
-LOCATE COMP "INPUT[0]" SITE "B5" ;
-LOCATE COMP "INPUT[1]" SITE "C4" ;
-LOCATE COMP "INPUT[2]" SITE "A2" ;
-LOCATE COMP "INPUT[3]" SITE "B2" ;
-LOCATE COMP "INPUT[4]" SITE "C1" ;
-LOCATE COMP "INPUT[5]" SITE "D2" ;
-LOCATE COMP "INPUT[6]" SITE "K2" ;
-LOCATE COMP "INPUT[7]" SITE "H1" ;
-LOCATE COMP "INPUT[8]" SITE "K4" ;
-LOCATE COMP "INPUT[9]" SITE "L4" ;
-LOCATE COMP "INPUT[10]" SITE "M4" ;
-LOCATE COMP "INPUT[11]" SITE "N4" ;
-LOCATE COMP "INPUT[12]" SITE "P1" ;
-LOCATE COMP "INPUT[13]" SITE "P3" ;
-LOCATE COMP "INPUT[14]" SITE "U18" ;
-LOCATE COMP "INPUT[15]" SITE "U16" ;
-LOCATE COMP "INPUT[16]" SITE "C18" ;
-LOCATE COMP "INPUT[17]" SITE "E16" ;
-LOCATE COMP "INPUT[18]" SITE "K16" ;
-LOCATE COMP "INPUT[19]" SITE "C20" ;
-LOCATE COMP "INPUT[20]" SITE "D20" ;
-LOCATE COMP "INPUT[21]" SITE "E20" ;
-LOCATE COMP "INPUT[22]" SITE "N16" ;
-LOCATE COMP "INPUT[23]" SITE "N18" ;
-LOCATE COMP "INPUT[24]" SITE "N17" ;
-LOCATE COMP "INPUT[25]" SITE "R16" ;
-LOCATE COMP "INPUT[26]" SITE "N19" ;
-LOCATE COMP "INPUT[27]" SITE "P19" ;
-LOCATE COMP "INPUT[28]" SITE "N3" ;
-LOCATE COMP "INPUT[29]" SITE "L3" ;
-LOCATE COMP "INPUT[30]" SITE "N2" ;
-LOCATE COMP "INPUT[31]" SITE "L1" ;
+LOCATE COMP "INPUT[0]"  SITE "E5";
+LOCATE COMP "INPUT[1]"  SITE "F4";
+LOCATE COMP "INPUT[2]"  SITE "E4";
+LOCATE COMP "INPUT[3]"  SITE "B5";
+LOCATE COMP "INPUT[4]"  SITE "A4";
+LOCATE COMP "INPUT[5]"  SITE "C4";
+LOCATE COMP "INPUT[6]"  SITE "A3";
+LOCATE COMP "INPUT[7]"  SITE "C3";
+LOCATE COMP "INPUT[8]"  SITE "A2";
+LOCATE COMP "INPUT[9]"  SITE "B2";
+LOCATE COMP "INPUT[10]" SITE "C1";
+LOCATE COMP "INPUT[11]" SITE "D2";
+LOCATE COMP "INPUT[12]" SITE "F2";
+LOCATE COMP "INPUT[13]" SITE "G3";
+LOCATE COMP "INPUT[14]" SITE "H4";
+LOCATE COMP "INPUT[15]" SITE "H5";
+LOCATE COMP "INPUT[16]" SITE "T19";
+LOCATE COMP "INPUT[17]" SITE "T20";
+LOCATE COMP "INPUT[18]" SITE "U19";
+LOCATE COMP "INPUT[19]" SITE "P20";
+LOCATE COMP "INPUT[20]" SITE "R16";
+LOCATE COMP "INPUT[21]" SITE "N19";
+LOCATE COMP "INPUT[22]" SITE "P19";
+LOCATE COMP "INPUT[23]" SITE "L18";
+LOCATE COMP "INPUT[24]" SITE "N18";
+LOCATE COMP "INPUT[25]" SITE "D18";
+LOCATE COMP "INPUT[26]" SITE "E16";
+LOCATE COMP "INPUT[27]" SITE "L16";
+LOCATE COMP "INPUT[28]" SITE "N16";
+LOCATE COMP "INPUT[29]" SITE "N17";
+LOCATE COMP "INPUT[30]" SITE "U16";
+LOCATE COMP "INPUT[31]" SITE "U18";
 DEFINE PORT GROUP "INP_group" "INP*" ;
 IOBUF GROUP  "INP_group" IO_TYPE=LVDS  DIFFRESISTOR=OFF BANK_VCCIO=2.5;
 
-LOCATE COMP "CLOCK_IN" SITE "L20";
+LOCATE COMP "CLOCK_IN"   SITE "L20";
+LOCATE COMP "CLOCK_CAL"                 SITE "J20";
 DEFINE PORT GROUP "CLK_group" "CL*" ;
 IOBUF GROUP  "CLK_group" IO_TYPE=LVDS  DIFFRESISTOR=100 BANK_VCCIO=2.5;
 
@@ -42,3 +43,99 @@ DEFINE PORT GROUP "TRIG_group" "TRIG*" ;
 IOBUF GROUP  "TRIG_group" IO_TYPE=LVDS  DIFFRESISTOR=100 BANK_VCCIO=2.5;
 
 
+LOCATE COMP "PWM[1]"                       SITE "D8";
+LOCATE COMP "PWM[2]"                       SITE "D9";
+LOCATE COMP "PWM[3]"                       SITE "E7";
+LOCATE COMP "PWM[4]"                       SITE "C8";
+LOCATE COMP "PWM[5]"                       SITE "B8";
+LOCATE COMP "PWM[6]"                       SITE "C6";
+LOCATE COMP "PWM[7]"                       SITE "A8";
+LOCATE COMP "PWM[8]"                       SITE "D7";
+LOCATE COMP "PWM[9]"                       SITE "A7";
+LOCATE COMP "PWM[10]"                      SITE "C7";
+LOCATE COMP "PWM[11]"                      SITE "D6";
+LOCATE COMP "PWM[12]"                      SITE "E6";
+LOCATE COMP "PWM[13]"                      SITE "E8";
+LOCATE COMP "PWM[14]"                      SITE "E9";
+LOCATE COMP "PWM[15]"                      SITE "D10";
+LOCATE COMP "PWM[16]"                      SITE "C9";
+LOCATE COMP "PWM[17]"                      SITE "C17";
+LOCATE COMP "PWM[18]"                      SITE "C16";
+LOCATE COMP "PWM[19]"                      SITE "D16";
+LOCATE COMP "PWM[20]"                      SITE "B19";
+LOCATE COMP "PWM[21]"                      SITE "D15";
+LOCATE COMP "PWM[22]"                      SITE "A18";
+LOCATE COMP "PWM[23]"                      SITE "B18";
+LOCATE COMP "PWM[24]"                      SITE "B17";
+LOCATE COMP "PWM[25]"                      SITE "A17";
+LOCATE COMP "PWM[26]"                      SITE "B15";
+LOCATE COMP "PWM[27]"                      SITE "C15";
+LOCATE COMP "PWM[28]"                      SITE "B16";
+LOCATE COMP "PWM[29]"                      SITE "A15";
+LOCATE COMP "PWM[30]"                      SITE "A16";
+LOCATE COMP "PWM[31]"                      SITE "E14";
+LOCATE COMP "PWM[32]"                      SITE "E15";
+DEFINE PORT GROUP "PWM_group" "PWM*" ;
+IOBUF GROUP  "PWM_group" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+
+LOCATE COMP "LED_GREEN"                      SITE "G16";
+LOCATE COMP "LED_ORANGE"                     SITE "H16";
+LOCATE COMP "LED_RED"                        SITE "H18";
+LOCATE COMP "LED_YELLOW"                     SITE "H17";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP  "LED_group" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+
+LOCATE COMP "ADC_CS"                         SITE "J16";
+LOCATE COMP "ADC_DIN"                        SITE "K17";
+LOCATE COMP "ADC_DOUT"                       SITE "K16";
+LOCATE COMP "ADC_SCLK"                       SITE "J17";
+IOBUF PORT  "ADC_CS" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+IOBUF PORT  "ADC_DIN" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+IOBUF PORT  "ADC_DOUT" IO_TYPE=LVCMOS25  BANK_VCCIO=2.5;
+IOBUF PORT  "ADC_SCLK" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+
+
+
+LOCATE COMP "PROGRAMN"                       SITE "W3";
+IOBUF PORT  "PROGRAMN" IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+
+LOCATE COMP "SIG[1]"                           SITE "N4";
+LOCATE COMP "SIG[2]"                           SITE "N5";
+LOCATE COMP "SIG[3]"                           SITE "M5";
+LOCATE COMP "SIG[4]"                           SITE "M4";
+LOCATE COMP "SIG[5]"                           SITE "L5";
+LOCATE COMP "SIG[6]"                           SITE "L4";
+DEFINE PORT GROUP "SIG_group" "SIG*" ;
+IOBUF GROUP  "SIG_group" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+
+
+LOCATE COMP "FLASH_CLK"                        SITE "U3";
+LOCATE COMP "FLASH_CS"                         SITE "R2";
+LOCATE COMP "FLASH_IN"                         SITE "W2";
+LOCATE COMP "FLASH_OUT"                        SITE "V2";
+IOBUF PORT  "FLASH_CS" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_IN" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_OUT" IO_TYPE=LVCMOS25   BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_CS" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=3.3;
+
+
+LOCATE COMP "TEMP_LINE"                      SITE "R1";
+IOBUF PORT  "TEMP_LINE" IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+
+
+LOCATE COMP "TEST[1]"                          SITE "N3";
+LOCATE COMP "TEST[2]"                          SITE "M3";
+LOCATE COMP "TEST[3]"                          SITE "L3";
+LOCATE COMP "TEST[4]"                          SITE "K3";
+LOCATE COMP "TEST[5]"                          SITE "N2";
+LOCATE COMP "TEST[6]"                          SITE "J3";
+LOCATE COMP "TEST[7]"                          SITE "P1";
+LOCATE COMP "TEST[8]"                          SITE "L2";
+LOCATE COMP "TEST[9]"                          SITE "P2";
+LOCATE COMP "TEST[10]"                         SITE "L1";
+LOCATE COMP "TEST[11]"                         SITE "P3";
+LOCATE COMP "TEST[12]"                         SITE "M1";
+LOCATE COMP "TEST[13]"                         SITE "P4";
+LOCATE COMP "TEST[14]"                         SITE "N1";
+DEFINE PORT GROUP "TEST_group" "TEST*" ;
+IOBUF GROUP  "TEST_group" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
\ No newline at end of file