-- DCUA is a black-box. Cannot print a valid VHDL entity description for it
---
--- Verific VHDL Description of module serdes_gbersl_core
---
-
--- serdes_gbersl_core is a black-box. Cannot print a valid VHDL entity description for it
-
--
-- Verific VHDL Description of module serdes_gbesll_core
--
rx_disp_err: out std_logic_vector(0 downto 0);
rx_cv_err: out std_logic_vector(0 downto 0);
signal_detect_c: in std_logic;
+ rx_los_low_s: out std_logic;
lsm_status_s: out std_logic;
rx_cdr_lol_s: out std_logic;
- sli_rst: in std_logic;
+ tx_pcs_rst_c: in std_logic;
+ rx_pcs_rst_c: in std_logic;
+ rx_serdes_rst_c: in std_logic;
tx_pwrup_c: in std_logic;
rx_pwrup_c: in std_logic;
- sci_wrdata: in std_logic_vector(7 downto 0);
- sci_addr: in std_logic_vector(5 downto 0);
- sci_rddata: out std_logic_vector(7 downto 0);
- sci_en_dual: in std_logic;
- sci_sel_dual: in std_logic;
- sci_en: in std_logic;
- sci_sel: in std_logic;
- sci_rd: in std_logic;
- sci_wrn: in std_logic;
- sci_int: out std_logic;
- cyawstn: in std_logic;
- serdes_pdb: in std_logic;
- pll_refclki: in std_logic;
- rsl_disable: in std_logic;
- rsl_rst: in std_logic;
- serdes_rst_dual_c: in std_logic;
rst_dual_c: in std_logic;
+ serdes_rst_dual_c: in std_logic;
+ serdes_pdb: in std_logic;
tx_serdes_rst_c: in std_logic;
- tx_pcs_rst_c: in std_logic;
- pll_lol: out std_logic;
- rx_serdes_rst_c: in std_logic;
- rx_pcs_rst_c: in std_logic
+ pll_refclki: in std_logic;
+ sli_rst: in std_logic;
+ pll_lol: out std_logic
);
end entity serdes_gbe;
architecture v1 of serdes_gbe is
- component serdes_gbersl_core is
- generic (pnum_channels: integer := 1;
- pprotocol: string := "SGMII";
- pserdes_mode: string := "RX AND TX";
- pport_tx_rdy: string := "DISABLED";
- pwait_tx_rdy: integer := 3000;
- pport_rx_rdy: string := "DISABLED";
- pwait_rx_rdy: integer := 3000);
- port (rui_rst: in std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(132)
- rui_serdes_rst_dual_c: in std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(133)
- rui_rst_dual_c: in std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(134)
- rui_rsl_disable: in std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(135)
- rui_tx_ref_clk: in std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(137)
- rui_tx_serdes_rst_c: in std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(138)
- rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(139)
- rdi_pll_lol: in std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(140)
- rui_rx_ref_clk: in std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(142)
- rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(143)
- rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(144)
- rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(145)
- rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(146)
- rdo_serdes_rst_dual_c: out std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(149)
- rdo_rst_dual_c: out std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(150)
- ruo_tx_rdy: out std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(152)
- rdo_tx_serdes_rst_c: out std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(153)
- rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(154)
- ruo_rx_rdy: out std_logic; -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(156)
- rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(157)
- rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(158)
- );
-
- end component serdes_gbersl_core; -- syn_black_box=1 -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(88)
component serdes_gbesll_core is
generic (PPROTOCOL: string := "SGMII";
PLOL_SETTING: integer := 0;
end component serdes_gbesll_core; -- syn_black_box=1 -- /opt/lattice/diamond/3.12/ispfpga/sa5p00g/data/sll_core_template.v(107)
signal n48,n47,n1,n2,n3,n4,rx_pclk_c,n5,n6,n7,n8,tx_pclk_c,n9,
- n10,n11,n12,n13,n14,n15,n16,rx_cdr_lol_s_c,n17,n18,rsl_tx_pcs_rst_c,
- rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,rsl_serdes_rst_dual_c,
- rsl_tx_serdes_rst_c,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,
- n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,
- n43,n44,n45,n46,n49,n107,n106,n50,n51,n52,n53,n54,n55,n56,
- n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,n68,n69,n70,
- n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,n82,n83,n84,
- n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,n96,n97,n98,
- n99,n100,n101,n102,n103,n104,n105,n116,n115,n114,pll_lol_c,
- n128,n127,n117,n118,n119,n120,n121,n122,n123,n124,n125,n126,
- \_Z\,n130,n129,gnd,pwr : std_logic;
+ n10,n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,
+ n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,
+ n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n115,n114,n50,n51,
+ n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,
+ n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,
+ n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,
+ n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n105,n106,
+ n107,n108,n109,n110,n111,n112,n113,\_Z\,n117,n116,gnd,pwr : std_logic;
attribute LOC : string;
attribute LOC of DCU0_inst : label is "DCU0";
attribute CHAN : string;
begin
rx_pclk <= rx_pclk_c;
tx_pclk <= tx_pclk_c;
- rx_cdr_lol_s <= rx_cdr_lol_s_c;
- pll_lol <= pll_lol_c;
DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
CH0_UDF_COMMA_MASK=>"0x3ff",CH0_UDF_COMMA_A=>"0x283",CH0_UDF_COMMA_B=>"0x17C",
CH0_RX_DCO_CK_DIV=>"0b000",CH0_RCV_DCC_EN=>"0b0",CH0_TPWDNB=>"0b1",
CH0_RATE_MODE_TX=>"0b1",CH0_RTERM_TX=>"0d19",CH0_TX_CM_SEL=>"0b00",
- CH0_TDRV_PRE_EN=>"0b0",CH0_TDRV_SLICE0_SEL=>"0b00",CH0_TDRV_SLICE1_SEL=>"0b00",
+ CH0_TDRV_PRE_EN=>"0b0",CH0_TDRV_SLICE0_SEL=>"0b01",CH0_TDRV_SLICE1_SEL=>"0b00",
CH0_TDRV_SLICE2_SEL=>"0b01",CH0_TDRV_SLICE3_SEL=>"0b01",CH0_TDRV_SLICE4_SEL=>"0b01",
- CH0_TDRV_SLICE5_SEL=>"0b00",CH0_TDRV_SLICE0_CUR=>"0b000",CH0_TDRV_SLICE1_CUR=>"0b000",
- CH0_TDRV_SLICE2_CUR=>"0b11",CH0_TDRV_SLICE3_CUR=>"0b11",CH0_TDRV_SLICE4_CUR=>"0b01",
+ CH0_TDRV_SLICE5_SEL=>"0b01",CH0_TDRV_SLICE0_CUR=>"0b101",CH0_TDRV_SLICE1_CUR=>"0b000",
+ CH0_TDRV_SLICE2_CUR=>"0b11",CH0_TDRV_SLICE3_CUR=>"0b11",CH0_TDRV_SLICE4_CUR=>"0b11",
CH0_TDRV_SLICE5_CUR=>"0b00",CH0_TDRV_DAT_SEL=>"0b00",CH0_TX_DIV11_SEL=>"0b0",
CH0_RPWDNB=>"0b1",CH0_RATE_MODE_RX=>"0b1",CH0_RX_DIV11_SEL=>"0b0",
CH0_SEL_SD_RX_CLK=>"0b1",CH0_FF_RX_H_CLK_EN=>"0b0",CH0_FF_RX_F_CLK_DIS=>"0b0",
CH0_TX_POST_SIGN=>"0b0",CH0_TX_PRE_SIGN=>"0b0",CH0_REQ_LVL_SET=>"0b00",
CH0_REQ_EN=>"0b1",CH0_RTERM_RX=>"0d22",CH0_RXTERM_CM=>"0b11",CH0_PDEN_SEL=>"0b1",
CH0_RXIN_CM=>"0b11",CH0_LEQ_OFFSET_SEL=>"0b0",CH0_LEQ_OFFSET_TRIM=>"0b000",
- CH0_RLOS_SEL=>"0b1",CH0_RX_LOS_LVL=>"0b010",CH0_RX_LOS_CEQ=>"0b11",
- CH0_RX_LOS_HYST_EN=>"0b0",CH0_RX_LOS_EN=>"0b0",CH0_LDR_RX2CORE_SEL=>"0b0",
+ CH0_RLOS_SEL=>"0b1",CH0_RX_LOS_LVL=>"0b100",CH0_RX_LOS_CEQ=>"0b11",
+ CH0_RX_LOS_HYST_EN=>"0b0",CH0_RX_LOS_EN=>"0b1",CH0_LDR_RX2CORE_SEL=>"0b0",
CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2.5",CH0_CDR_MAX_RATE=>"2.5",
- CH0_TXAMPLITUDE=>"0d800",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED",
+ CH0_TXAMPLITUDE=>"0d1100",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED",
CH0_PROTOCOL=>"SGMII",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00",
D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000",
D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH0_CDR_CNT4SEL=>"0b00",
D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH0_RX_RATE_SEL=>"0d8",
D_REFCK_MODE=>"0b000",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b00",
D_RG_EN=>"0b0",D_RG_SET=>"0b00")
- port map (CH0_HDINP=>hdinp,CH1_HDINP=>n107,CH0_HDINN=>hdinn,CH1_HDINN=>n107,
+ port map (CH0_HDINP=>hdinp,CH1_HDINP=>n115,CH0_HDINN=>hdinn,CH1_HDINN=>n115,
D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47,
- CH0_RX_REFCLK=>rxrefclk,CH1_RX_REFCLK=>n107,CH0_FF_RXI_CLK=>rx_pclk_c,
- CH1_FF_RXI_CLK=>n106,CH0_FF_TXI_CLK=>txi_clk,CH1_FF_TXI_CLK=>n106,CH0_FF_EBRD_CLK=>n48,
- CH1_FF_EBRD_CLK=>n106,CH0_FF_TX_D_0=>txdata(0),CH1_FF_TX_D_0=>n107,CH0_FF_TX_D_1=>txdata(1),
- CH1_FF_TX_D_1=>n107,CH0_FF_TX_D_2=>txdata(2),CH1_FF_TX_D_2=>n107,CH0_FF_TX_D_3=>txdata(3),
- CH1_FF_TX_D_3=>n107,CH0_FF_TX_D_4=>txdata(4),CH1_FF_TX_D_4=>n107,CH0_FF_TX_D_5=>txdata(5),
- CH1_FF_TX_D_5=>n107,CH0_FF_TX_D_6=>txdata(6),CH1_FF_TX_D_6=>n107,CH0_FF_TX_D_7=>txdata(7),
- CH1_FF_TX_D_7=>n107,CH0_FF_TX_D_8=>tx_k(0),CH1_FF_TX_D_8=>n107,CH0_FF_TX_D_9=>n47,
- CH1_FF_TX_D_9=>n107,CH0_FF_TX_D_10=>xmit(0),CH1_FF_TX_D_10=>n107,CH0_FF_TX_D_11=>tx_disp_correct(0),
- CH1_FF_TX_D_11=>n107,CH0_FF_TX_D_12=>n107,CH1_FF_TX_D_12=>n107,CH0_FF_TX_D_13=>n107,
- CH1_FF_TX_D_13=>n107,CH0_FF_TX_D_14=>n107,CH1_FF_TX_D_14=>n107,CH0_FF_TX_D_15=>n107,
- CH1_FF_TX_D_15=>n107,CH0_FF_TX_D_16=>n107,CH1_FF_TX_D_16=>n107,CH0_FF_TX_D_17=>n107,
- CH1_FF_TX_D_17=>n107,CH0_FF_TX_D_18=>n107,CH1_FF_TX_D_18=>n107,CH0_FF_TX_D_19=>n107,
- CH1_FF_TX_D_19=>n107,CH0_FF_TX_D_20=>n107,CH1_FF_TX_D_20=>n107,CH0_FF_TX_D_21=>n47,
- CH1_FF_TX_D_21=>n107,CH0_FF_TX_D_22=>n107,CH1_FF_TX_D_22=>n107,CH0_FF_TX_D_23=>n107,
- CH1_FF_TX_D_23=>n107,CH0_FFC_EI_EN=>n47,CH1_FFC_EI_EN=>n107,CH0_FFC_PCIE_DET_EN=>n47,
- CH1_FFC_PCIE_DET_EN=>n107,CH0_FFC_PCIE_CT=>n47,CH1_FFC_PCIE_CT=>n107,
- CH0_FFC_SB_INV_RX=>n107,CH1_FFC_SB_INV_RX=>n107,CH0_FFC_ENABLE_CGALIGN=>n107,
- CH1_FFC_ENABLE_CGALIGN=>n107,CH0_FFC_SIGNAL_DETECT=>signal_detect_c,CH1_FFC_SIGNAL_DETECT=>n107,
- CH0_FFC_FB_LOOPBACK=>n47,CH1_FFC_FB_LOOPBACK=>n107,CH0_FFC_SB_PFIFO_LP=>n47,
- CH1_FFC_SB_PFIFO_LP=>n107,CH0_FFC_PFIFO_CLR=>n47,CH1_FFC_PFIFO_CLR=>n107,
- CH0_FFC_RATE_MODE_RX=>n47,CH1_FFC_RATE_MODE_RX=>n107,CH0_FFC_RATE_MODE_TX=>n47,
- CH1_FFC_RATE_MODE_TX=>n107,CH0_FFC_DIV11_MODE_RX=>n47,CH1_FFC_DIV11_MODE_RX=>n107,
- CH0_FFC_DIV11_MODE_TX=>n47,CH1_FFC_DIV11_MODE_TX=>n107,CH0_FFC_RX_GEAR_MODE=>n47,
- CH1_FFC_RX_GEAR_MODE=>n107,CH0_FFC_TX_GEAR_MODE=>n47,CH1_FFC_TX_GEAR_MODE=>n107,
- CH0_FFC_LDR_CORE2TX_EN=>n107,CH1_FFC_LDR_CORE2TX_EN=>n107,CH0_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,
- CH1_FFC_LANE_TX_RST=>n107,CH0_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH1_FFC_LANE_RX_RST=>n107,
- CH0_FFC_RRST=>rsl_rx_serdes_rst_c,CH1_FFC_RRST=>n107,CH0_FFC_TXPWDNB=>tx_pwrup_c,
- CH1_FFC_TXPWDNB=>n107,CH0_FFC_RXPWDNB=>rx_pwrup_c,CH1_FFC_RXPWDNB=>n107,
- CH0_LDR_CORE2TX=>n107,CH1_LDR_CORE2TX=>n107,D_SCIWDATA0=>sci_wrdata(0),
- D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2),D_SCIWDATA3=>sci_wrdata(3),
- D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5),D_SCIWDATA6=>sci_wrdata(6),
- D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0),D_SCIADDR1=>sci_addr(1),
- D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3),D_SCIADDR4=>sci_addr(4),
- D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual,D_SCISELAUX=>sci_sel_dual,
- CH0_SCIEN=>sci_en,CH1_SCIEN=>n107,CH0_SCISEL=>sci_sel,CH1_SCISEL=>n107,
- D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn,D_FFC_SYNC_TOGGLE=>n107,
- D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,
- D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n47,
- CH1_FFC_CDR_EN_BITSLIP=>n107,D_SCAN_ENABLE=>n47,D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47,
- D_SCAN_IN_2=>n47,D_SCAN_IN_3=>n47,D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47,
- D_SCAN_IN_6=>n47,D_SCAN_IN_7=>n47,D_SCAN_MODE=>n47,D_SCAN_RESET=>n47,
- D_CIN0=>n47,D_CIN1=>n47,D_CIN2=>n47,D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47,
- D_CIN6=>n47,D_CIN7=>n47,D_CIN8=>n47,D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47,
- CH0_HDOUTP=>hdoutp,CH1_HDOUTP=>n50,CH0_HDOUTN=>hdoutn,CH1_HDOUTN=>n51,
- D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,
- CH0_FF_RX_F_CLK=>n5,CH1_FF_RX_F_CLK=>n52,CH0_FF_RX_H_CLK=>n6,CH1_FF_RX_H_CLK=>n53,
- CH0_FF_TX_F_CLK=>n7,CH1_FF_TX_F_CLK=>n54,CH0_FF_TX_H_CLK=>n8,CH1_FF_TX_H_CLK=>n55,
- CH0_FF_RX_PCLK=>rx_pclk_c,CH1_FF_RX_PCLK=>n56,CH0_FF_TX_PCLK=>tx_pclk_c,
- CH1_FF_TX_PCLK=>n57,CH0_FF_RX_D_0=>rxdata(0),CH1_FF_RX_D_0=>n58,CH0_FF_RX_D_1=>rxdata(1),
- CH1_FF_RX_D_1=>n59,CH0_FF_RX_D_2=>rxdata(2),CH1_FF_RX_D_2=>n60,CH0_FF_RX_D_3=>rxdata(3),
- CH1_FF_RX_D_3=>n61,CH0_FF_RX_D_4=>rxdata(4),CH1_FF_RX_D_4=>n62,CH0_FF_RX_D_5=>rxdata(5),
- CH1_FF_RX_D_5=>n63,CH0_FF_RX_D_6=>rxdata(6),CH1_FF_RX_D_6=>n64,CH0_FF_RX_D_7=>rxdata(7),
- CH1_FF_RX_D_7=>n65,CH0_FF_RX_D_8=>rx_k(0),CH1_FF_RX_D_8=>n66,CH0_FF_RX_D_9=>rx_disp_err(0),
- CH1_FF_RX_D_9=>n67,CH0_FF_RX_D_10=>rx_cv_err(0),CH1_FF_RX_D_10=>n68,CH0_FF_RX_D_11=>n9,
- CH1_FF_RX_D_11=>n69,CH0_FF_RX_D_12=>n70,CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72,
- CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74,CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76,
- CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78,CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80,
- CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82,CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84,
- CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86,CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88,
- CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90,CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n10,
- CH1_FF_RX_D_23=>n92,CH0_FFS_PCIE_DONE=>n11,CH1_FFS_PCIE_DONE=>n93,CH0_FFS_PCIE_CON=>n12,
- CH1_FFS_PCIE_CON=>n94,CH0_FFS_RLOS=>n95,CH1_FFS_RLOS=>n96,CH0_FFS_LS_SYNC_STATUS=>lsm_status_s,
- CH1_FFS_LS_SYNC_STATUS=>n97,CH0_FFS_CC_UNDERRUN=>n13,CH1_FFS_CC_UNDERRUN=>n98,
- CH0_FFS_CC_OVERRUN=>n14,CH1_FFS_CC_OVERRUN=>n99,CH0_FFS_RXFBFIFO_ERROR=>n15,
- CH1_FFS_RXFBFIFO_ERROR=>n100,CH0_FFS_TXFBFIFO_ERROR=>n16,CH1_FFS_TXFBFIFO_ERROR=>n101,
- CH0_FFS_RLOL=>rx_cdr_lol_s_c,CH1_FFS_RLOL=>n102,CH0_FFS_SKP_ADDED=>n17,
- CH1_FFS_SKP_ADDED=>n103,CH0_FFS_SKP_DELETED=>n18,CH1_FFS_SKP_DELETED=>n104,
- CH0_LDR_RX2CORE=>n105,CH1_LDR_RX2CORE=>n116,D_SCIRDATA0=>sci_rddata(0),
- D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2),D_SCIRDATA3=>sci_rddata(3),
- D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5),D_SCIRDATA6=>sci_rddata(6),
- D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int,D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,
- D_SCAN_OUT_2=>n21,D_SCAN_OUT_3=>n22,D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,
- D_SCAN_OUT_6=>n25,D_SCAN_OUT_7=>n26,D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,
- D_COUT3=>n30,D_COUT4=>n31,D_COUT5=>n32,D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,
- D_COUT9=>n36,D_COUT10=>n37,D_COUT11=>n38,D_COUT12=>n39,D_COUT13=>n40,
- D_COUT14=>n41,D_COUT15=>n42,D_COUT16=>n43,D_COUT17=>n44,D_COUT18=>n45,
- D_COUT19=>n46,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49);
+ CH0_RX_REFCLK=>rxrefclk,CH1_RX_REFCLK=>n115,CH0_FF_RXI_CLK=>rx_pclk_c,
+ CH1_FF_RXI_CLK=>n114,CH0_FF_TXI_CLK=>txi_clk,CH1_FF_TXI_CLK=>n114,CH0_FF_EBRD_CLK=>n48,
+ CH1_FF_EBRD_CLK=>n114,CH0_FF_TX_D_0=>txdata(0),CH1_FF_TX_D_0=>n115,CH0_FF_TX_D_1=>txdata(1),
+ CH1_FF_TX_D_1=>n115,CH0_FF_TX_D_2=>txdata(2),CH1_FF_TX_D_2=>n115,CH0_FF_TX_D_3=>txdata(3),
+ CH1_FF_TX_D_3=>n115,CH0_FF_TX_D_4=>txdata(4),CH1_FF_TX_D_4=>n115,CH0_FF_TX_D_5=>txdata(5),
+ CH1_FF_TX_D_5=>n115,CH0_FF_TX_D_6=>txdata(6),CH1_FF_TX_D_6=>n115,CH0_FF_TX_D_7=>txdata(7),
+ CH1_FF_TX_D_7=>n115,CH0_FF_TX_D_8=>tx_k(0),CH1_FF_TX_D_8=>n115,CH0_FF_TX_D_9=>n47,
+ CH1_FF_TX_D_9=>n115,CH0_FF_TX_D_10=>xmit(0),CH1_FF_TX_D_10=>n115,CH0_FF_TX_D_11=>tx_disp_correct(0),
+ CH1_FF_TX_D_11=>n115,CH0_FF_TX_D_12=>n115,CH1_FF_TX_D_12=>n115,CH0_FF_TX_D_13=>n115,
+ CH1_FF_TX_D_13=>n115,CH0_FF_TX_D_14=>n115,CH1_FF_TX_D_14=>n115,CH0_FF_TX_D_15=>n115,
+ CH1_FF_TX_D_15=>n115,CH0_FF_TX_D_16=>n115,CH1_FF_TX_D_16=>n115,CH0_FF_TX_D_17=>n115,
+ CH1_FF_TX_D_17=>n115,CH0_FF_TX_D_18=>n115,CH1_FF_TX_D_18=>n115,CH0_FF_TX_D_19=>n115,
+ CH1_FF_TX_D_19=>n115,CH0_FF_TX_D_20=>n115,CH1_FF_TX_D_20=>n115,CH0_FF_TX_D_21=>n47,
+ CH1_FF_TX_D_21=>n115,CH0_FF_TX_D_22=>n115,CH1_FF_TX_D_22=>n115,CH0_FF_TX_D_23=>n115,
+ CH1_FF_TX_D_23=>n115,CH0_FFC_EI_EN=>n47,CH1_FFC_EI_EN=>n115,CH0_FFC_PCIE_DET_EN=>n47,
+ CH1_FFC_PCIE_DET_EN=>n115,CH0_FFC_PCIE_CT=>n47,CH1_FFC_PCIE_CT=>n115,
+ CH0_FFC_SB_INV_RX=>n115,CH1_FFC_SB_INV_RX=>n115,CH0_FFC_ENABLE_CGALIGN=>n115,
+ CH1_FFC_ENABLE_CGALIGN=>n115,CH0_FFC_SIGNAL_DETECT=>signal_detect_c,CH1_FFC_SIGNAL_DETECT=>n115,
+ CH0_FFC_FB_LOOPBACK=>n47,CH1_FFC_FB_LOOPBACK=>n115,CH0_FFC_SB_PFIFO_LP=>n47,
+ CH1_FFC_SB_PFIFO_LP=>n115,CH0_FFC_PFIFO_CLR=>n47,CH1_FFC_PFIFO_CLR=>n115,
+ CH0_FFC_RATE_MODE_RX=>n47,CH1_FFC_RATE_MODE_RX=>n115,CH0_FFC_RATE_MODE_TX=>n47,
+ CH1_FFC_RATE_MODE_TX=>n115,CH0_FFC_DIV11_MODE_RX=>n47,CH1_FFC_DIV11_MODE_RX=>n115,
+ CH0_FFC_DIV11_MODE_TX=>n47,CH1_FFC_DIV11_MODE_TX=>n115,CH0_FFC_RX_GEAR_MODE=>n47,
+ CH1_FFC_RX_GEAR_MODE=>n115,CH0_FFC_TX_GEAR_MODE=>n47,CH1_FFC_TX_GEAR_MODE=>n115,
+ CH0_FFC_LDR_CORE2TX_EN=>n115,CH1_FFC_LDR_CORE2TX_EN=>n115,CH0_FFC_LANE_TX_RST=>tx_pcs_rst_c,
+ CH1_FFC_LANE_TX_RST=>n115,CH0_FFC_LANE_RX_RST=>rx_pcs_rst_c,CH1_FFC_LANE_RX_RST=>n115,
+ CH0_FFC_RRST=>rx_serdes_rst_c,CH1_FFC_RRST=>n115,CH0_FFC_TXPWDNB=>tx_pwrup_c,
+ CH1_FFC_TXPWDNB=>n115,CH0_FFC_RXPWDNB=>rx_pwrup_c,CH1_FFC_RXPWDNB=>n115,
+ CH0_LDR_CORE2TX=>n115,CH1_LDR_CORE2TX=>n115,D_SCIWDATA0=>n115,D_SCIWDATA1=>n115,
+ D_SCIWDATA2=>n115,D_SCIWDATA3=>n115,D_SCIWDATA4=>n115,D_SCIWDATA5=>n115,
+ D_SCIWDATA6=>n115,D_SCIWDATA7=>n115,D_SCIADDR0=>n115,D_SCIADDR1=>n115,
+ D_SCIADDR2=>n115,D_SCIADDR3=>n115,D_SCIADDR4=>n115,D_SCIADDR5=>n115,
+ D_SCIENAUX=>n115,D_SCISELAUX=>n115,CH0_SCIEN=>n115,CH1_SCIEN=>n115,CH0_SCISEL=>n115,
+ CH1_SCISEL=>n115,D_SCIRD=>n115,D_SCIWSTN=>n115,D_CYAWSTN=>n115,D_FFC_SYNC_TOGGLE=>n115,
+ D_FFC_DUAL_RST=>rst_dual_c,D_FFC_MACRO_RST=>serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,
+ D_FFC_TRST=>tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n47,CH1_FFC_CDR_EN_BITSLIP=>n115,
+ D_SCAN_ENABLE=>n47,D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47,D_SCAN_IN_2=>n47,
+ D_SCAN_IN_3=>n47,D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47,D_SCAN_IN_6=>n47,
+ D_SCAN_IN_7=>n47,D_SCAN_MODE=>n47,D_SCAN_RESET=>n47,D_CIN0=>n47,D_CIN1=>n47,
+ D_CIN2=>n47,D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47,D_CIN6=>n47,D_CIN7=>n47,
+ D_CIN8=>n47,D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47,CH0_HDOUTP=>hdoutp,
+ CH1_HDOUTP=>n50,CH0_HDOUTN=>hdoutn,CH1_HDOUTN=>n51,D_TXBIT_CLKP_TO_ND=>n1,
+ D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n5,
+ CH1_FF_RX_F_CLK=>n52,CH0_FF_RX_H_CLK=>n6,CH1_FF_RX_H_CLK=>n53,CH0_FF_TX_F_CLK=>n7,
+ CH1_FF_TX_F_CLK=>n54,CH0_FF_TX_H_CLK=>n8,CH1_FF_TX_H_CLK=>n55,CH0_FF_RX_PCLK=>rx_pclk_c,
+ CH1_FF_RX_PCLK=>n56,CH0_FF_TX_PCLK=>tx_pclk_c,CH1_FF_TX_PCLK=>n57,CH0_FF_RX_D_0=>rxdata(0),
+ CH1_FF_RX_D_0=>n58,CH0_FF_RX_D_1=>rxdata(1),CH1_FF_RX_D_1=>n59,CH0_FF_RX_D_2=>rxdata(2),
+ CH1_FF_RX_D_2=>n60,CH0_FF_RX_D_3=>rxdata(3),CH1_FF_RX_D_3=>n61,CH0_FF_RX_D_4=>rxdata(4),
+ CH1_FF_RX_D_4=>n62,CH0_FF_RX_D_5=>rxdata(5),CH1_FF_RX_D_5=>n63,CH0_FF_RX_D_6=>rxdata(6),
+ CH1_FF_RX_D_6=>n64,CH0_FF_RX_D_7=>rxdata(7),CH1_FF_RX_D_7=>n65,CH0_FF_RX_D_8=>rx_k(0),
+ CH1_FF_RX_D_8=>n66,CH0_FF_RX_D_9=>rx_disp_err(0),CH1_FF_RX_D_9=>n67,CH0_FF_RX_D_10=>rx_cv_err(0),
+ CH1_FF_RX_D_10=>n68,CH0_FF_RX_D_11=>n9,CH1_FF_RX_D_11=>n69,CH0_FF_RX_D_12=>n70,
+ CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72,CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74,
+ CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76,CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78,
+ CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80,CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82,
+ CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84,CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86,
+ CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88,CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90,
+ CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n10,CH1_FF_RX_D_23=>n92,CH0_FFS_PCIE_DONE=>n11,
+ CH1_FFS_PCIE_DONE=>n93,CH0_FFS_PCIE_CON=>n12,CH1_FFS_PCIE_CON=>n94,CH0_FFS_RLOS=>rx_los_low_s,
+ CH1_FFS_RLOS=>n95,CH0_FFS_LS_SYNC_STATUS=>lsm_status_s,CH1_FFS_LS_SYNC_STATUS=>n96,
+ CH0_FFS_CC_UNDERRUN=>n13,CH1_FFS_CC_UNDERRUN=>n97,CH0_FFS_CC_OVERRUN=>n14,
+ CH1_FFS_CC_OVERRUN=>n98,CH0_FFS_RXFBFIFO_ERROR=>n15,CH1_FFS_RXFBFIFO_ERROR=>n99,
+ CH0_FFS_TXFBFIFO_ERROR=>n16,CH1_FFS_TXFBFIFO_ERROR=>n100,CH0_FFS_RLOL=>rx_cdr_lol_s,
+ CH1_FFS_RLOL=>n101,CH0_FFS_SKP_ADDED=>n17,CH1_FFS_SKP_ADDED=>n102,CH0_FFS_SKP_DELETED=>n18,
+ CH1_FFS_SKP_DELETED=>n103,CH0_LDR_RX2CORE=>n104,CH1_LDR_RX2CORE=>n105,
+ D_SCIRDATA0=>n106,D_SCIRDATA1=>n107,D_SCIRDATA2=>n108,D_SCIRDATA3=>n109,
+ D_SCIRDATA4=>n110,D_SCIRDATA5=>n111,D_SCIRDATA6=>n112,D_SCIRDATA7=>n113,
+ D_SCIINT=>\_Z\,D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21,
+ D_SCAN_OUT_3=>n22,D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25,
+ D_SCAN_OUT_7=>n26,D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30,
+ D_COUT4=>n31,D_COUT5=>n32,D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36,
+ D_COUT10=>n37,D_COUT11=>n38,D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41,
+ D_COUT15=>n42,D_COUT16=>n43,D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46,
+ D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49);
n48 <= '1' ;
n47 <= '0' ;
n1 <= 'Z' ;
n45 <= 'Z' ;
n46 <= 'Z' ;
n49 <= 'Z' ;
- n107 <= '0' ;
- n106 <= '1' ;
+ n115 <= '0' ;
+ n114 <= '1' ;
n50 <= 'Z' ;
n51 <= 'Z' ;
n52 <= 'Z' ;
n103 <= 'Z' ;
n104 <= 'Z' ;
n105 <= 'Z' ;
- n116 <= 'Z' ;
- rsl_inst: component serdes_gbersl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c,
- rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki,
- rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n128,
- rui_tx_pcs_rst_c(2)=>n128,rui_tx_pcs_rst_c(1)=>n128,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c,
- rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n128,
- rui_rx_serdes_rst_c(2)=>n128,rui_rx_serdes_rst_c(1)=>n128,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c,
- rui_rx_pcs_rst_c(3)=>n128,rui_rx_pcs_rst_c(2)=>n128,rui_rx_pcs_rst_c(1)=>n128,
- rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n128,rdi_rx_los_low_s(2)=>n128,
- rdi_rx_los_low_s(1)=>n128,rdi_rx_los_low_s(0)=>n128,rdi_rx_cdr_lol_s(3)=>n128,
- rdi_rx_cdr_lol_s(2)=>n128,rdi_rx_cdr_lol_s(1)=>n128,rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,
- rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c,rdo_rst_dual_c=>rsl_rst_dual_c,
- ruo_tx_rdy=>n117,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c,rdo_tx_pcs_rst_c(3)=>n118,
- rdo_tx_pcs_rst_c(2)=>n119,rdo_tx_pcs_rst_c(1)=>n120,rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,
- ruo_rx_rdy=>n121,rdo_rx_serdes_rst_c(3)=>n122,rdo_rx_serdes_rst_c(2)=>n123,
- rdo_rx_serdes_rst_c(1)=>n124,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c,
- rdo_rx_pcs_rst_c(3)=>n125,rdo_rx_pcs_rst_c(2)=>n126,rdo_rx_pcs_rst_c(1)=>\_Z\,
- rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c);
- n115 <= '1' ;
- n114 <= '0' ;
- n128 <= '0' ;
- n127 <= '1' ;
- n117 <= 'Z' ;
- n118 <= 'Z' ;
- n119 <= 'Z' ;
- n120 <= 'Z' ;
- n121 <= 'Z' ;
- n122 <= 'Z' ;
- n123 <= 'Z' ;
- n124 <= 'Z' ;
- n125 <= 'Z' ;
- n126 <= 'Z' ;
+ n106 <= 'Z' ;
+ n107 <= 'Z' ;
+ n108 <= 'Z' ;
+ n109 <= 'Z' ;
+ n110 <= 'Z' ;
+ n111 <= 'Z' ;
+ n112 <= 'Z' ;
+ n113 <= 'Z' ;
\_Z\ <= 'Z' ;
sll_inst: component serdes_gbesll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki,
sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd,
sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd,
- sli_pcie_mode=>gnd,slo_plol=>pll_lol_c);
- n130 <= '1' ;
- n129 <= '0' ;
+ sli_pcie_mode=>gnd,slo_plol=>pll_lol);
+ n117 <= '1' ;
+ n116 <= '0' ;
gnd <= '0' ;
pwr <= '1' ;
-
-// ===========================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// ---------------------------------------------------------------------------
-// Copyright (c) 2016 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code
-// pursuant to the terms of the Lattice Reference Design License Agreement.
-//
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// ---------------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// ---------------------------------------------------------------------------
-//
-// =============================================================================
-// FILE DETAILS
-// Project : RSL- Reset Sequence Logic
-// File : rsl_core.v
-// Title : Top-level file for RSL
-// Dependencies : 1.
-// : 2.
-// Description :
-// =============================================================================
-// REVISION HISTORY
-// Version : 1.0
-// Author(s) : BM
-// Mod. Date : October 28, 2013
-// Changes Made : Initial Creation
-// -----------------------------------------------------------------------------
-// Version : 1.1
-// Author(s) : BM
-// Mod. Date : November 06, 2013
-// Changes Made : Tx/Rx separation, ready port code exclusion
-// -----------------------------------------------------------------------------
-// Version : 1.2
-// Author(s) : BM
-// Mod. Date : June 13, 2014
-// Changes Made : Updated Rx PCS reset method
-// -----------------------------------------------------------------------------
-// -----------------------------------------------------------------------------
-// Version : 1.3
-// Author(s) : UA
-// Mod. Date : Dec 19, 2014
-// Changes Made : Added new parameter fro PCIE
-// -----------------------------------------------------------------------------
-// Version : 1.31
-// Author(s) : BM/UM
-// Mod. Date : Feb 23, 2016
-// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy
-// and the rx_rdy wait counter are reset to zero on
-// LOL or LOS. Reverted back the counter value change for PCIE.
-// -----------------------------------------------------------------------------
-// Version : 1.4
-// Author(s) : EB
-// Mod. Date: : March 21, 2017
-// Changes Made :
-// -----------------------------------------------------------------------------
-// Version : 1.5
-// Author(s) : ES
-// Mod. Date: : May 8, 2017
-// Changes Made : Implemented common RSL behaviour as proposed by BM.
-// =============================================================================
-
-`timescale 1ns/10ps
-
-module serdes_gbersl_core (
- // ------------ Inputs
- // Common
- rui_rst, // Active high reset for the RSL module
- rui_serdes_rst_dual_c, // SERDES macro reset user command
- rui_rst_dual_c, // PCS dual reset user command
- rui_rsl_disable, // Active high signal that disables all reset outputs of RSL
- // Tx
- rui_tx_ref_clk, // Tx reference clock
- rui_tx_serdes_rst_c, // Tx SERDES reset user command
- rui_tx_pcs_rst_c, // Tx lane reset user command
- rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES
- // Rx
- rui_rx_ref_clk, // Rx reference clock
- rui_rx_serdes_rst_c, // SERDES Receive channel reset user command
- rui_rx_pcs_rst_c, // Rx lane reset user command
- rdi_rx_los_low_s, // Receive loss of signal status input from SERDES
- rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES
-
- // ------------ Outputs
- // Common
- rdo_serdes_rst_dual_c, // SERDES macro reset command output
- rdo_rst_dual_c, // PCS dual reset command output
- // Tx
- ruo_tx_rdy, // Tx lane ready status output
- rdo_tx_serdes_rst_c, // SERDES Tx reset command output
- rdo_tx_pcs_rst_c, // PCS Tx lane reset command output
- // Rx
- ruo_rx_rdy, // Rx lane ready status output
- rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output
- rdo_rx_pcs_rst_c // PCS Rx lane reset command output
- );
-
-// ------------ Module parameters
-`ifdef NUM_CHANNELS
- parameter pnum_channels = `NUM_CHANNELS; // 1,2,4
-`else
- parameter pnum_channels = 1;
-`endif
-
-`ifdef PCIE
- parameter pprotocol = "PCIE";
-`else
- parameter pprotocol = "";
-`endif
-
-`ifdef RX_ONLY
- parameter pserdes_mode = "RX ONLY";
-`else
- `ifdef TX_ONLY
- parameter pserdes_mode = "TX ONLY";
- `else
- parameter pserdes_mode = "RX AND TX";
- `endif
-`endif
-
-`ifdef PORT_TX_RDY
- parameter pport_tx_rdy = "ENABLED";
-`else
- parameter pport_tx_rdy = "DISABLED";
-`endif
-
-`ifdef WAIT_TX_RDY
- parameter pwait_tx_rdy = `WAIT_TX_RDY;
-`else
- parameter pwait_tx_rdy = 3000;
-`endif
-
-`ifdef PORT_RX_RDY
- parameter pport_rx_rdy = "ENABLED";
-`else
- parameter pport_rx_rdy = "DISABLED";
-`endif
-
-`ifdef WAIT_RX_RDY
- parameter pwait_rx_rdy = `WAIT_RX_RDY;
-`else
- parameter pwait_rx_rdy = 3000;
-`endif
-
-// ------------ Local parameters
- localparam wa_num_cycles = 1024;
- localparam dac_num_cycles = 3;
- localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3
- localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz
- localparam lwait_b4_trst_s = 781; // for simulation
- localparam lplol_cnt_width = 20; // width for lwait_b4_trst
- localparam lwait_after_plol0 = 4;
- localparam lwait_b4_rrst = 180224; // total calibration time
- localparam lrrst_wait_width = 20;
- localparam lwait_after_rrst = 800000; // For CPRI- unused
- localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team
- localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst
- localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles
- localparam lwait_after_lols_s = 150; // wait cycles provided by design team
- localparam llols_cnt_width = 18; // lols count width
- localparam lrdb_max = 15; // maximum debounce count
- localparam ltxr_wait_width = 12; // width of tx ready wait counter
- localparam lrxr_wait_width = 12; // width of tx ready wait counter
-
-// ------------ input ports
- input rui_rst;
- input rui_serdes_rst_dual_c;
- input rui_rst_dual_c;
- input rui_rsl_disable;
-
- input rui_tx_ref_clk;
- input rui_tx_serdes_rst_c;
- input [3:0] rui_tx_pcs_rst_c;
- input rdi_pll_lol;
-
- input rui_rx_ref_clk;
- input [3:0] rui_rx_serdes_rst_c;
- input [3:0] rui_rx_pcs_rst_c;
- input [3:0] rdi_rx_los_low_s;
- input [3:0] rdi_rx_cdr_lol_s;
-
-// ------------ output ports
- output rdo_serdes_rst_dual_c;
- output rdo_rst_dual_c;
-
- output ruo_tx_rdy;
- output rdo_tx_serdes_rst_c;
- output [3:0] rdo_tx_pcs_rst_c;
-
- output ruo_rx_rdy;
- output [3:0] rdo_rx_serdes_rst_c;
- output [3:0] rdo_rx_pcs_rst_c;
-
-// ------------ Internal registers and wires
- // inputs
- wire rui_rst;
- wire rui_serdes_rst_dual_c;
- wire rui_rst_dual_c;
- wire rui_rsl_disable;
- wire rui_tx_ref_clk;
- wire rui_tx_serdes_rst_c;
- wire [3:0] rui_tx_pcs_rst_c;
- wire rdi_pll_lol;
- wire rui_rx_ref_clk;
- wire [3:0] rui_rx_serdes_rst_c;
- wire [3:0] rui_rx_pcs_rst_c;
- wire [3:0] rdi_rx_los_low_s;
- wire [3:0] rdi_rx_cdr_lol_s;
-
- // outputs
- wire rdo_serdes_rst_dual_c;
- wire rdo_rst_dual_c;
- wire ruo_tx_rdy;
- wire rdo_tx_serdes_rst_c;
- wire [3:0] rdo_tx_pcs_rst_c;
- wire ruo_rx_rdy;
- wire [3:0] rdo_rx_serdes_rst_c;
- wire [3:0] rdo_rx_pcs_rst_c;
-
- // internal signals
- // common
- wire rsl_enable;
- wire [lplol_cnt_width-1:0] wait_b4_trst;
- wire [lrlol_cnt_width-1:0] wait_b4_rrst;
- wire [llols_cnt_width-1:0] wait_after_lols;
- reg pll_lol_p1;
- reg pll_lol_p2;
- reg pll_lol_p3;
- // ------------ Tx
- // rdo_tx_serdes_rst_c
- reg [lplol_cnt_width-1:0] plol_cnt;
- wire plol_cnt_tc;
-
- reg [2:0] txs_cnt;
- reg txs_rst;
- wire txs_cnt_tc;
- // rdo_tx_pcs_rst_c
- wire plol_fedge;
- wire plol_redge;
- reg waita_plol0;
- reg [2:0] plol0_cnt;
- wire plol0_cnt_tc;
- reg [2:0] txp_cnt;
- reg txp_rst;
- wire txp_cnt_tc;
- // ruo_tx_rdy
- wire dual_or_serd_rst;
- wire tx_any_pcs_rst;
- wire tx_any_rst;
- reg txsr_appd /* synthesis syn_keep=1 */;
- reg txdpr_appd;
- reg [pnum_channels-1:0] txpr_appd;
- reg txr_wt_en;
- reg [ltxr_wait_width-1:0] txr_wt_cnt;
- wire txr_wt_tc;
- reg ruo_tx_rdyr;
-
- // ------------ Rx
- wire comb_rlos;
- wire comb_rlol;
- //wire rlols;
- wire rx_all_well;
-
- //reg rlols_p1;
- //reg rlols_p2;
- //reg rlols_p3;
-
- reg rlol_p1;
- reg rlol_p2;
- reg rlol_p3;
- reg rlos_p1;
- reg rlos_p2;
- reg rlos_p3;
-
- //reg [3:0] rdb_cnt;
- //wire rdb_cnt_max;
- //wire rdb_cnt_zero;
- //reg rlols_db;
- //reg rlols_db_p1;
-
- reg [3:0] rlol_db_cnt;
- wire rlol_db_cnt_max;
- wire rlol_db_cnt_zero;
- reg rlol_db;
- reg rlol_db_p1;
-
- reg [3:0] rlos_db_cnt;
- wire rlos_db_cnt_max;
- wire rlos_db_cnt_zero;
- reg rlos_db;
- reg rlos_db_p1;
-
- // rdo_rx_serdes_rst_c
- reg [lrlol_cnt_width-1:0] rlol1_cnt;
- wire rlol1_cnt_tc;
- reg [2:0] rxs_cnt;
- reg rxs_rst;
- wire rxs_cnt_tc;
- reg [lrrst_wait_width-1:0] rrst_cnt;
- wire rrst_cnt_tc;
- reg rrst_wait;
- // rdo_rx_pcs_rst_c
- //wire rlols_fedge;
- //wire rlols_redge;
- wire rlol_fedge;
- wire rlol_redge;
- wire rlos_fedge;
- wire rlos_redge;
-
- reg wait_calib;
- reg waita_rlols0;
- reg [llols_cnt_width-1:0] rlols0_cnt;
- wire rlols0_cnt_tc;
- reg [2:0] rxp_cnt;
- reg rxp_rst;
- wire rxp_cnt_tc;
-
- wire rx_any_serd_rst;
- reg [llols_cnt_width-1:0] rlolsz_cnt;
- wire rlolsz_cnt_tc;
- reg [2:0] rxp_cnt2;
- reg rxp_rst2;
- wire rxp_cnt2_tc;
- reg [15:0] data_loop_b_cnt;
- reg data_loop_b;
- wire data_loop_b_tc;
-
- // ruo_rx_rdy
- reg [pnum_channels-1:0] rxsr_appd;
- reg [pnum_channels-1:0] rxpr_appd;
- reg rxsdr_appd /* synthesis syn_keep=1 */;
- reg rxdpr_appd;
- wire rxsdr_or_sr_appd;
- wire dual_or_rserd_rst;
- wire rx_any_pcs_rst;
- wire rx_any_rst;
- reg rxr_wt_en;
- reg [lrxr_wait_width-1:0] rxr_wt_cnt;
- wire rxr_wt_tc;
- reg ruo_rx_rdyr;
-
-// ==================================================================
-// Start of code
-// ==================================================================
- assign rsl_enable = ~rui_rsl_disable;
-
-// ------------ rdo_serdes_rst_dual_c
- assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c;
-
-// ------------ rdo_rst_dual_c
- assign rdo_rst_dual_c = rui_rst_dual_c;
-
-// ------------ Setting counter values for RSL_SIM_MODE
- `ifdef RSL_SIM_MODE
- assign wait_b4_trst = lwait_b4_trst_s;
- assign wait_b4_rrst = lwait_b4_rrst_s;
- assign wait_after_lols = lwait_after_lols_s;
- `else
- assign wait_b4_trst = lwait_b4_trst;
- assign wait_b4_rrst = lwait_b4_rrst;
- assign wait_after_lols = lwait_after_lols;
- `endif
-
-// ==================================================================
-// Tx
-// ==================================================================
- generate
- if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin
-
-// ------------ Synchronizing pll_lol to the tx clock
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) begin
- pll_lol_p1 <= 1'd0;
- pll_lol_p2 <= 1'd0;
- pll_lol_p3 <= 1'd0;
- end
- else begin
- pll_lol_p1 <= rdi_pll_lol;
- pll_lol_p2 <= pll_lol_p1;
- pll_lol_p3 <= pll_lol_p2;
- end
- end
-
-// ------------ rdo_tx_serdes_rst_c
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- plol_cnt <= 'd0;
- else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1))
- plol_cnt <= 'd0;
- else
- plol_cnt <= plol_cnt+1;
- end
- assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0;
-
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) begin
- txs_cnt <= 'd0; // tx serdes reset pulse count
- txs_rst <= 1'b0; // tx serdes reset
- end
- else if(plol_cnt_tc==1)
- txs_rst <= 1'b1;
- else if(txs_cnt_tc==1) begin
- txs_cnt <= 'd0;
- txs_rst <= 1'b0;
- end
- else if(txs_rst==1)
- txs_cnt <= txs_cnt+1;
- end
- assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0;
-
- assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c;
-
-// ------------ rdo_tx_pcs_rst_c
- assign plol_fedge = ~pll_lol_p2 & pll_lol_p3;
- assign plol_redge = pll_lol_p2 & ~pll_lol_p3;
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- waita_plol0 <= 1'd0;
- else if(plol_fedge==1'b1)
- waita_plol0 <= 1'b1;
- else if((plol0_cnt_tc==1)||(plol_redge==1))
- waita_plol0 <= 1'd0;
- end
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- plol0_cnt <= 'd0;
- else if((pll_lol_p2==1)||(plol0_cnt_tc==1))
- plol0_cnt <= 'd0;
- else if(waita_plol0==1'b1)
- plol0_cnt <= plol0_cnt+1;
- end
- assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0;
-
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) begin
- txp_cnt <= 'd0; // tx serdes reset pulse count
- txp_rst <= 1'b0; // tx serdes reset
- end
- else if(plol0_cnt_tc==1)
- txp_rst <= 1'b1;
- else if(txp_cnt_tc==1) begin
- txp_cnt <= 'd0;
- txp_rst <= 1'b0;
- end
- else if(txp_rst==1)
- txp_cnt <= txp_cnt+1;
- end
- assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0;
-
- genvar i;
- for(i=0;i<pnum_channels;i=i+1) begin : ifor
- assign rdo_tx_pcs_rst_c[i] = (rsl_enable&txp_rst)| rui_tx_pcs_rst_c[i];
- end
- if(pnum_channels==1)
- assign rdo_tx_pcs_rst_c[3:1] = 3'b000;
- else if(pnum_channels==2)
- assign rdo_tx_pcs_rst_c[3:2] = 2'b00;
-
- // ------------ ruo_tx_rdy
- if(pport_tx_rdy=="ENABLED") begin
- assign dual_or_serd_rst = rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c;
- assign tx_any_pcs_rst = rdo_rst_dual_c|(|rdo_tx_pcs_rst_c[pnum_channels-1:0]);
- assign tx_any_rst = dual_or_serd_rst | tx_any_pcs_rst;
-
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- txsr_appd <= 1'b1; // tx serdes reset applied
- else if(dual_or_serd_rst==1)
- txsr_appd <= 1'b1;
- end
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- txdpr_appd <= 1'b0; // tx dual (pcs) reset applied
- else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
- txdpr_appd <= 1'b0;
- else if(rdo_rst_dual_c==1)
- txdpr_appd <= 1'b1;
- end
-
- genvar m;
- for(m=0;m<pnum_channels;m=m+1) begin :mfor
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- txpr_appd[m] <= 1'b0; // tx pcs reset applied
- else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
- txpr_appd[m] <= 1'b0;
- else if(txsr_appd&(rdo_tx_pcs_rst_c[m]|txdpr_appd))
- txpr_appd[m] <= 1'b1;
- end
- end
-
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- txr_wt_en <= 0; // tx ready wait counter enable
- else if((txr_wt_tc==1)||(dual_or_serd_rst==1))
- txr_wt_en <= 0;
- else if((~ruo_tx_rdyr)&(~pll_lol_p2)&(&txpr_appd))
- txr_wt_en <= 1;
- end
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- txr_wt_cnt <= 'd0; // tx ready wait count
- else if((txr_wt_tc==1)||(tx_any_rst==1))
- txr_wt_cnt <= 'd0;
- else if(txr_wt_en==1)
- txr_wt_cnt <= txr_wt_cnt+1;
- end
- assign txr_wt_tc = (txr_wt_cnt==pwait_tx_rdy)?1'b1:1'b0;
-
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- ruo_tx_rdyr <= 1'b0; // tx serdes reset applied
- else if((tx_any_rst==1)||(pll_lol_p2==1))
- ruo_tx_rdyr <= 1'b0;
- else if(txr_wt_tc==1)
- ruo_tx_rdyr <= 1'b1;
- end
- assign ruo_tx_rdy = ruo_tx_rdyr;
- end // if pport_tx_rdy
- else
- assign ruo_tx_rdy = 1'b0;
- end // generate if(Rx and Tx) or (Tx only)
- else begin // generate else (Rx only)
- assign rdo_tx_serdes_rst_c = 1'b0;
- assign rdo_tx_pcs_rst_c = 4'd0;
- assign ruo_tx_rdy = 1'b0;
- end
- endgenerate
-
-// ==================================================================
-// Rx
-// ==================================================================
- generate
- if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY")) begin
- assign comb_rlos = |rdi_rx_los_low_s[pnum_channels-1:0];
- assign comb_rlol = |rdi_rx_cdr_lol_s[pnum_channels-1:0];
- //assign rlols = comb_rlos|comb_rlol;
-
- // ------------ Synchronizing rlols to the rx ref clock
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) begin
- //rlols_p1 <= 1'd0;
- //rlols_p2 <= 1'd0;
- //rlols_p3 <= 1'd0;
- //rlols_db_p1 <= 1'd1;
-
- rlol_p1 <= 1'd0;
- rlol_p2 <= 1'd0;
- rlol_p3 <= 1'd0;
- rlol_db_p1 <= 1'd1;
-
- rlos_p1 <= 1'd0;
- rlos_p2 <= 1'd0;
- rlos_p3 <= 1'd0;
- rlos_db_p1 <= 1'd1;
- end
- else begin
- //rlols_p1 <= rlols;
- //rlols_p2 <= rlols_p1;
- //rlols_p3 <= rlols_p2;
- //rlols_db_p1 <= rlols_db;
-
- rlol_p1 <= comb_rlol;
- rlol_p2 <= rlol_p1;
- rlol_p3 <= rlol_p2;
- rlol_db_p1 <= rlol_db;
-
- rlos_p1 <= comb_rlos;
- rlos_p2 <= rlos_p1;
- rlos_p3 <= rlos_p2;
- rlos_db_p1 <= rlos_db;
- end
- end
- assign rx_all_well = ~rlol_db && ~rlos_db;
-
-//******************************************************************************
-// [ES:05.03.17] Unused registers for clean-up
-//------------------------------------------------------------------------------
-// ------------ Debouncing rlols
-// always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
-// if(rui_rst==1'b1) rdb_cnt <= lrdb_max;
-// else if(rlols_p2==1) begin
-// if(!rdb_cnt_max) rdb_cnt <= rdb_cnt+1;
-// end
-// else if(!rdb_cnt_zero) rdb_cnt <= rdb_cnt-1;
-// end
-// assign rdb_cnt_max = (rdb_cnt==lrdb_max);
-// assign rdb_cnt_zero = (rdb_cnt==0);
-// always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
-// if(rui_rst==1'b1) rlols_db <= 1;
-// else if(rdb_cnt_max) rlols_db <= 1;
-// else if(rdb_cnt_zero) rlols_db <= 0;
-// end
-//******************************************************************************
-
-// ------------ Debouncing rlol
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) rlol_db_cnt <= lrdb_max;
- else if(rlol_p2==1) begin
- if(!rlol_db_cnt_max) rlol_db_cnt <= rlol_db_cnt+1;
- end
- else if(!rlol_db_cnt_zero) rlol_db_cnt <= rlol_db_cnt-1;
- end
- assign rlol_db_cnt_max = (rlol_db_cnt==lrdb_max);
- assign rlol_db_cnt_zero = (rlol_db_cnt==0);
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) rlol_db <= 1;
- else if(rlol_db_cnt_max) rlol_db <= 1;
- else if(rlol_db_cnt_zero) rlol_db <= 0;
- end
-
-// ------------ Debouncing rlos
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) rlos_db_cnt <= lrdb_max;
- else if(rlos_p2==1) begin
- if(!rlos_db_cnt_max) rlos_db_cnt <= rlos_db_cnt+1;
- end
- else if(!rlos_db_cnt_zero) rlos_db_cnt <= rlos_db_cnt-1;
- end
- assign rlos_db_cnt_max = (rlos_db_cnt==lrdb_max);
- assign rlos_db_cnt_zero = (rlos_db_cnt==0);
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) rlos_db <= 1;
- else if(rlos_db_cnt_max) rlos_db <= 1;
- else if(rlos_db_cnt_zero) rlos_db <= 0;
- end
-
-// ------------ Calib time trigger
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- wait_calib <= 1'd1;
- end
- else begin
- if (rlol1_cnt_tc) begin
- if (rlol_db)
- wait_calib <= 1'd1;
- else
- wait_calib <= 1'd0;
- end
- else if (rlos_redge)
- wait_calib <= 1'd0;
- else if (rlos_fedge) begin
- wait_calib <= 1'd1;
- end
- end
- end
-
- //***************************************************************************
- // Total calibration time counter
- // - this covers the band calibration time (256 cycles * 64) and
- // DAC calibration time (16384 cycles * 10 bits)
- //---------------------------------------------------------------------------
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- rlol1_cnt <= 'd0; // Counting when Rx LOL is 1 and Rx LOS is 0
- end
- else begin
- if(rxs_rst || rlol1_cnt_tc || rlos_redge)
- rlol1_cnt <= 'd0;
- else if (wait_calib)
- rlol1_cnt <= rlol1_cnt+1;
- end
- end
- assign rlol1_cnt_tc = (rlol1_cnt==wait_b4_rrst);
-
-// ------------ rdo_rx_serdes_rst_c
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- rxs_cnt <= 'd0; // rx serdes reset pulse count
- rxs_rst <= 1'b0; // rx serdes reset
- end
- else begin
- if (rlos_db)
- rxs_rst <= 1'b0;
- else if (rlol1_cnt_tc && rlol_db)
- rxs_rst <= 1'b1;
- else if (rxs_cnt_tc==1) begin
- rxs_rst <= 1'b0;
- end
-
- if (rxs_cnt_tc)
- rxs_cnt <= 'd0;
- else
- if (rxs_rst==1)
- rxs_cnt <= rxs_cnt+1;
- end
- end
- assign rxs_cnt_tc = (rxs_cnt==lreset_pwidth)?1'b1:1'b0;
-
- //***************************************************************************
- // [ES:05.03.17] Unused logic from CPRI rrst_wait
- //---------------------------------------------------------------------------
- // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- // if(rui_rst==1'b1)
- // rrst_cnt <= 'd0;
- // else if(rlol1_cnt_tc)
- // rrst_cnt <= 'd0;
- // else if(rrst_wait)
- // rrst_cnt <= rrst_cnt+1;
- // end
- // assign rrst_cnt_tc = (rrst_cnt==lwait_after_rrst) ? 1'b1 : 1'b0;
- // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- // if(rui_rst==1'b1)
- // rrst_wait <= 0;
- // else if(pprotocol != "CPRI")
- // rrst_wait <= 0;
- // else if(rlol1_cnt_tc)
- // rrst_wait <= 1;
- // else if(rrst_cnt_tc==1)
- // rrst_wait <= 0;
- // end
- //***************************************************************************
-
- genvar j;
- for(j=0;j<pnum_channels;j=j+1) begin :jfor
- assign rdo_rx_serdes_rst_c[j] = (rsl_enable&rxs_rst)| rui_rx_serdes_rst_c[j];
- end
- if(pnum_channels==1)
- assign rdo_rx_serdes_rst_c[3:1] = 3'b000;
- else if(pnum_channels==2)
- assign rdo_rx_serdes_rst_c[3:2] = 2'b00;
-
-// ------------ rdo_rx_pcs_rst_c
- //assign rlols_fedge = ~rlols_db & rlols_db_p1;
- //assign rlols_redge = rlols_db & ~rlols_db_p1;
-
- assign rlol_fedge = ~rlol_db & rlol_db_p1;
- assign rlol_redge = rlol_db & ~rlol_db_p1;
- assign rlos_fedge = ~rlos_db & rlos_db_p1;
- assign rlos_redge = rlos_db & ~rlos_db_p1;
-
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- waita_rlols0 <= 1'd0;
- end
- else begin
- if ((rlos_fedge && ~rlol_db) || (rlol_fedge && ~rlos_db))
- waita_rlols0 <= 1'b1;
- else if (rlos_redge || rlol_redge)
- waita_rlols0 <= 1'd0;
- else if (rlols0_cnt_tc==1)
- waita_rlols0 <= 1'd0;
- end
- end
-
- //***************************************************************************
- // Post RLOL check before pcs_rst deassertion
- // - allowance of 2-4 DAC calibration cycles + 1024 cycles for WA module
- // (word alignment).
- //---------------------------------------------------------------------------
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- rlols0_cnt <= 'd0;
- end
- else begin
- if (rlol_redge || rlos_redge || rlols0_cnt_tc)
- rlols0_cnt <= 'd0;
- else if (waita_rlols0==1)
- rlols0_cnt <= rlols0_cnt+1;
- end
- end
- assign rlols0_cnt_tc = (rlols0_cnt == wait_after_lols);
- assign rx_any_serd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c);
-
- //***************************************************************************
- // [ES:05.03.17] Unused registers for clean-up
- //---------------------------------------------------------------------------
- // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- // if(rui_rst==1'b1)
- // rlolsz_cnt <= 'd0; // Counting when both Rx LOL is 0 and Rx LOS is 0
- // else if((rlol_db|rx_any_serd_rst)||(rlolsz_cnt_tc==1))
- // rlolsz_cnt <= 'd0;
- // else if((rlolsz_cnt_tc==0)&&(rlol_db==0))
- // rlolsz_cnt <= rlolsz_cnt+1;
- // end
- // assign rlolsz_cnt_tc = (rlolsz_cnt==wait_after_lols);
- //***************************************************************************
-
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- rxp_cnt2 <= 'd0; // pcs serdes reset pulse count
- rxp_rst2 <= 1'b1; // rx pcs reset
- end
- else begin
- if (rx_any_serd_rst || rlos_redge) begin
- rxp_rst2 <= 1'b1;
- end
- else if (rlols0_cnt_tc) begin
- rxp_rst2 <= 1'b0;
- end
- //***********************************************************************
- // [ES:05.03.17] No need for pulse width
- //-----------------------------------------------------------------------
- // else if(rxp_cnt2_tc==1) begin
- // rxp_cnt2 <= 'd0;
- // rxp_rst2 <= 1'b0;
- // end
- //***********************************************************************
- // [ES:05.03.17] No need for pulse width
- //-----------------------------------------------------------------------
- // else if (rxp_rst2==1)
- // rxp_cnt2 <= rxp_cnt2+1;
- //***********************************************************************
- end // else: !if(rui_rst==1'b1)
- end // always @ (posedge rui_rx_ref_clk or posedge rui_rst)
- //assign rxp_cnt2_tc = (rxp_cnt2==lreset_pwidth)?1'b1:1'b0;
-
- //***************************************************************************
- // [ES:05.03.17] No need for pulse width
- //---------------------------------------------------------------------------
- //else begin
- // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- // if(rui_rst==1'b1)
- // rxp_rst2 <= 1'b1; // rx pcs reset
- // else if(rx_any_serd_rst)
- // rxp_rst2 <= 1'b1;
- // else if(rlolsz_cnt_tc==1)
- // rxp_rst2 <= 1'b0;
- // end
- //end
- //***************************************************************************
-
- genvar k;
- for(k=0;k<pnum_channels;k=k+1) begin: kfor
- assign rdo_rx_pcs_rst_c[k] = (rsl_enable&rxp_rst2)| rui_rx_pcs_rst_c[k];
- end
- if(pnum_channels==1)
- assign rdo_rx_pcs_rst_c[3:1] = 3'b000;
- else if(pnum_channels==2)
- assign rdo_rx_pcs_rst_c[3:2] = 2'b00;
-
-// ------------ ruo_rx_rdy
- if(pport_rx_rdy=="ENABLED") begin
- assign dual_or_rserd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c[pnum_channels-1:0]);
- assign rx_any_pcs_rst = rdo_rst_dual_c|(|rdo_rx_pcs_rst_c[pnum_channels-1:0]);
- assign rx_any_rst = dual_or_rserd_rst | rx_any_pcs_rst;
-
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxsdr_appd <= 1'b1; // Serdes dual reset (macro reset) applied
- else if(rdo_serdes_rst_dual_c==1)
- rxsdr_appd <= 1'b1;
- end
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxdpr_appd <= 1'b0; // Rx dual PCS reset (dual reset) applied
- else if(~rx_all_well|dual_or_rserd_rst)
- rxdpr_appd <= 1'b0;
- else if(rdo_rst_dual_c==1)
- rxdpr_appd <= 1'b1;
- end
-
- genvar l;
- for(l=0;l<pnum_channels;l=l+1) begin : lfor
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxsr_appd[l] <= 1'b0; // rx serdes reset applied
- else if(rdo_rx_serdes_rst_c[l]==1)
- rxsr_appd[l] <= 1'b1;
- end
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxpr_appd[l] <= 1'b0; // rx pcs reset applied
- else if(rdi_rx_los_low_s[l]|rdi_rx_cdr_lol_s[l]|rdo_serdes_rst_dual_c|rdo_rx_serdes_rst_c[l])
- rxpr_appd[l] <= 1'b0;
- else if(rxsdr_or_sr_appd&(~rx_all_well)&rdo_rx_pcs_rst_c[l])
- rxpr_appd[l] <= 1'b1;
- end
- end
-
- assign rxsdr_or_sr_appd = rxsdr_appd|(&rxsr_appd);
-
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxr_wt_en <= 0; // rx ready wait counter enable
- //else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1))
- else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1)||(rx_all_well==0)) // BM, 2/4/16
- rxr_wt_en <= 0;
- else if(~ruo_rx_rdyr&rx_all_well&((&rxpr_appd)|rxdpr_appd))
- rxr_wt_en <= 1;
- end
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxr_wt_cnt <= 'd0; // rx ready wait count
- //else if((rxr_wt_tc==1)||(rx_any_rst==1))
- else if((rxr_wt_tc==1)||(rx_any_rst==1)||(rx_all_well==0)) // BM, 2/4/16
- rxr_wt_cnt <= 'd0;
- else if(rxr_wt_en==1)
- rxr_wt_cnt <= rxr_wt_cnt+1;
- end
- assign rxr_wt_tc = (rxr_wt_cnt==pwait_rx_rdy)?1'b1:1'b0;
-
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- ruo_rx_rdyr <= 1'b0; // rx serdes reset applied
- else if((rx_any_rst==1)||(rx_all_well==0))
- ruo_rx_rdyr <= 1'b0;
- else if(rxr_wt_tc==1)
- ruo_rx_rdyr <= 1'b1;
- end
- assign ruo_rx_rdy = ruo_rx_rdyr;
- end // if pport_rx_rdy
- else
- assign ruo_rx_rdy = 1'b0;
- end // if ((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
-
- else begin // generate else (Tx only)
- assign rdo_rx_serdes_rst_c = 4'd0;
- assign rdo_rx_pcs_rst_c = 4'd0;
- assign ruo_rx_rdy = 1'b0;
- end // else: !if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
-
- endgenerate
-
-endmodule
-
-
// ===========================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// ---------------------------------------------------------------------------
jspc29 / TOMcat.git / commitdiff