]> jspc29.x-matter.uni-frankfurt.de Git - ctsaddon.git/commitdiff
new files
authorhadaq <hadaq>
Fri, 20 Nov 2015 12:57:21 +0000 (12:57 +0000)
committerhadaq <hadaq>
Fri, 20 Nov 2015 12:57:21 +0000 (12:57 +0000)
20140412_cts_fpga2_only_etrax.stp [new file with mode: 0644]
cts_fpga1_trb_fpga_on.stp [new file with mode: 0644]
cts_fpga1_trb_no_fpga.stp [new file with mode: 0644]
cts_fpga2_trb_no_fpga.stp [new file with mode: 0644]
cts_simulation_tb.cr.mti [new file with mode: 0644]
cts_witdh_rom_simulation.vhd [new file with mode: 0644]
fifo12bit_synch.vhd [new file with mode: 0644]
fifo48bit_synch.vhd [new file with mode: 0644]
fifo52bit_synch.vhd [new file with mode: 0644]
fifo64bit_synch.vhd [new file with mode: 0644]

diff --git a/20140412_cts_fpga2_only_etrax.stp b/20140412_cts_fpga2_only_etrax.stp
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/cts_fpga1_trb_fpga_on.stp b/cts_fpga1_trb_fpga_on.stp
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/cts_fpga1_trb_no_fpga.stp b/cts_fpga1_trb_no_fpga.stp
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/cts_fpga2_trb_no_fpga.stp b/cts_fpga2_trb_no_fpga.stp
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/cts_simulation_tb.cr.mti b/cts_simulation_tb.cr.mti
new file mode 100644 (file)
index 0000000..0534728
--- /dev/null
@@ -0,0 +1,2401 @@
+/home/marek/trbv2/up_down_counter.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbv2/up_down_counter.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Compiling entity up_down_counter
+-- Compiling architecture up_down_counter of up_down_counter
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net_fifo_16bit_bram_dualport
+-- Compiling architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_dualport
+
+} {} {}} /home/marek/trbnet/basics/ram.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/basics/ram.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity ram
+-- Compiling architecture ram_arch of ram
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_19x16_obuf
+-- Compiling architecture structure of fifo_19x16_obuf
+-- Compiling configuration structure_con
+-- Loading entity fifo_19x16_obuf
+-- Loading architecture structure of fifo_19x16_obuf
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity pdpw16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/basics/ram_16x8_dp.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/basics/ram_16x8_dp.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity ram_16x8_dp
+-- Compiling architecture ram_16x8_dp_arch of ram_16x8_dp
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_simple_data_transport.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_simple_data_transport.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity cts_simple_data_transport
+-- Compiling architecture cts_simple_data_transport of cts_simple_data_transport
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_readout_data_buff.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_readout_data_buff.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity cts_readout_data_buff
+-- Compiling architecture structure of cts_readout_data_buff
+-- Compiling configuration structure_con
+-- Loading entity cts_readout_data_buff
+-- Loading architecture structure of cts_readout_data_buff
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity pdp16ka
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity vlo
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+
+} {} {}} /home/marek/trbnet/special/spi_master.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/special/spi_master.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity spi_master
+-- Compiling architecture behavioral of spi_master
+
+} {} {}} /home/marek/trbnet/trb_net_priority_arbiter.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net_priority_arbiter.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net_priority_arbiter
+-- Compiling architecture trb_net_priority_arbiter_arch of trb_net_priority_arbiter
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_cal_screset_gen.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_cal_screset_gen.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Compiling entity cts_cal_screset_gen
+-- Compiling architecture cts_cal_screset_gen of cts_cal_screset_gen
+
+} {} {}} /home/marek/ctsaddon/simulation/ram_register.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/ram_register.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity ram_register
+-- Compiling architecture structure of ram_register
+-- Compiling configuration structure_con
+-- Loading entity ram_register
+-- Loading architecture structure of ram_register
+-- Loading package vital_timing
+-- Loading entity vhi
+-- Loading entity vlo
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity pdp16ka
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/trb_net_clock_generator.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/trb_net_clock_generator.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net_clock_generator
+-- Compiling architecture trb_net_clock_generator_arch of trb_net_clock_generator
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_dualclock_width_16_reg
+-- Compiling architecture structure of fifo_dualclock_width_16_reg
+-- Compiling configuration structure_con
+-- Loading entity fifo_dualclock_width_16_reg
+-- Loading architecture structure of fifo_dualclock_width_16_reg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity or2
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3bx
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3dx
+-- Loading entity fd1s3bx
+-- Loading entity fadd2b
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity ageb2
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/trb_net_sbuf6.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net_sbuf6.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net_sbuf6
+-- Compiling architecture trb_net_sbuf6_arch of trb_net_sbuf6
+
+} {} {}} /home/marek/ctsaddon/fifo12bit_synch.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/fifo12bit_synch.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity fifo12bit_synch
+-- Compiling architecture structure of fifo12bit_synch
+-- Compiling configuration structure_con
+-- Loading entity fifo12bit_synch
+-- Loading architecture structure of fifo12bit_synch
+-- Loading package vital_timing
+-- Loading entity vhi
+-- Loading entity vlo
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity fifo16ka
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga2_reg_interface.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga2_reg_interface.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_fpga2_reg_interface
+-- Compiling architecture cts_fpga2_reg_interface of cts_fpga2_reg_interface
+
+} {} {}} /home/marek/trbnet/trb_net_dummy_fifo.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net_dummy_fifo.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_signed
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net_dummy_fifo
+-- Compiling architecture arch_trb_net_dummy_fifo of trb_net_dummy_fifo
+
+} {} {}} /home/marek/ctsaddon/simulation/delay.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/delay.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Compiling entity delay
+-- Compiling architecture behavioral of delay
+
+} {} {}} /home/marek/trbnet/special/handler_trigger_and_data.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/special/handler_trigger_and_data.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Compiling entity handler_trigger_and_data
+-- Compiling architecture handler_trigger_and_data_arch of handler_trigger_and_data
+
+} {} {}} /home/marek/trbnet/trb_net16_term.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_term.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net16_term
+-- Compiling architecture trb_net16_term_arch of trb_net16_term
+
+} {} {}} /home/marek/trbnet/trb_net_sbuf.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net_sbuf.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net_sbuf
+-- Compiling architecture trb_net_sbuf_arch of trb_net_sbuf
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga1_to_fpga2.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga1_to_fpga2.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_fpga1_to_fpga2
+-- Compiling architecture cts_fpga1_to_fpga2 of cts_fpga1_to_fpga2
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_36x512_oreg
+-- Compiling architecture structure of fifo_36x512_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_36x512_oreg
+-- Loading architecture structure of fifo_36x512_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity pdpw16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/dll_in100_out100.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/dll_in100_out100.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity dll_in100_out100
+-- Compiling architecture structure of dll_in100_out100
+-- Compiling configuration structure_con
+-- Loading entity dll_in100_out100
+-- Loading architecture structure of dll_in100_out100
+-- Loading package vital_timing
+-- Loading entity vlo
+-- Loading entity vhi
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package global
+-- Loading package mem3
+-- Loading entity ciddlla
+
+} {} {}} /home/marek/ctsaddon/fifo52bit_synch.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/fifo52bit_synch.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity fifo52bit_synch
+-- Compiling architecture structure of fifo52bit_synch
+-- Compiling configuration structure_con
+-- Loading entity fifo52bit_synch
+-- Loading architecture structure of fifo52bit_synch
+-- Loading package vital_timing
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity fifo16ka
+-- Loading entity vhi
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/trb_net16_endpoint_hades_full_handler.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_endpoint_hades_full_handler.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_endpoint_hades_full_handler
+-- Compiling architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_hades_full_handler
+
+} {} {}} /home/marek/ctsaddon/simulation/pll_in200_out40.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/pll_in200_out40.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity pll_in200_out40
+-- Compiling architecture structure of pll_in200_out40
+-- Compiling configuration structure_con
+-- Loading entity pll_in200_out40
+-- Loading architecture structure of pll_in200_out40
+-- Loading package vital_timing
+-- Loading entity vlo
+-- Loading entity vhi
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package global
+-- Loading package mem3
+-- Loading entity ehxplla
+
+} {} {}} /home/marek/ctsaddon/simulation/ddr2_16inputs.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/ddr2_16inputs.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity ddr2_16inputs
+-- Compiling architecture structure of ddr2_16inputs
+-- Compiling configuration structure_con
+-- Loading entity ddr2_16inputs
+-- Loading architecture structure of ddr2_16inputs
+-- Loading package vital_timing
+-- Loading package vital_primitives
+-- Loading entity iddrx2a
+-- Loading entity vlo
+-- Loading package global
+-- Loading entity clkdiv
+-- Loading entity ib
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_width_rom.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_width_rom.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity cts_width_rom
+-- Compiling architecture structure of cts_width_rom
+-- Compiling configuration structure_con
+-- Loading entity cts_width_rom
+-- Loading architecture structure of cts_width_rom
+-- Loading package vital_timing
+-- Loading entity vhi
+-- Loading entity vlo
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16ka
+
+} {} {}} /home/marek/trbnet/special/handler_lvl1.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/special/handler_lvl1.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Compiling entity handler_lvl1
+-- Compiling architecture handler_lvl1_arch of handler_lvl1
+
+} {} {}} /home/marek/trbnet/trb_net16_sbuf.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_sbuf.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_sbuf
+-- Compiling architecture trb_net16_sbuf_arch of trb_net16_sbuf
+
+} {} {}} /home/marek/trbv2/f_divider.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbv2/f_divider.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Compiling entity f_divider
+-- Compiling architecture arch_f_divider of f_divider
+-- Compiling entity edge_to_pulse
+-- Compiling architecture arch_edge_to_pulse of edge_to_pulse
+-- Compiling package support
+
+} {} {}} /home/marek/ctsaddon/simulation/scm_fifo_16bit_to_32bit.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/scm_fifo_16bit_to_32bit.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity scm_fifo_16bit_to_32bit
+-- Compiling architecture structure of scm_fifo_16bit_to_32bit
+-- Compiling configuration structure_con
+-- Loading entity scm_fifo_16bit_to_32bit
+-- Loading architecture structure of scm_fifo_16bit_to_32bit
+-- Loading package vital_timing
+-- Loading entity vhi
+-- Loading entity vlo
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity fifo16ka
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga2.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga2.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Loading package version
+-- Compiling entity cts_fpga2
+-- Compiling architecture cts_fpga2_arch of cts_fpga2
+
+} {} {}} /home/marek/trbnet/trb_net16_obuf_nodata.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_obuf_nodata.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net16_obuf_nodata
+-- Compiling architecture trb_net16_obuf_nodata_arch of trb_net16_obuf_nodata
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga2_to_fpga1.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga2_to_fpga1.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_fpga2_to_fpga1
+-- Compiling architecture cts_fpga2_to_fpga1 of cts_fpga2_to_fpga1
+-- Loading entity delay
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_eb_ip_switch.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_eb_ip_switch.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_eb_ip_switch
+-- Compiling architecture cts_eb_ip_switch of cts_eb_ip_switch
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_witdh_rom_simulation.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_witdh_rom_simulation.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_width_rom_simulation
+-- Compiling architecture cts_width_rom_simulation of cts_width_rom_simulation
+
+} {} {}} /home/marek/trbnet/special/spi_databus_memory.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/special/spi_databus_memory.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity spi_databus_memory
+-- Compiling architecture behavioral of spi_databus_memory
+
+} {} {}} /home/marek/trbnet/special/spi_slim.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/special/spi_slim.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity spi_slim
+-- Compiling architecture behavioral of spi_slim
+
+} {} {}} /home/marek/trbnet/trb_net16_term_buf.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_term_buf.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net16_term_buf
+-- Compiling architecture trb_net16_term_buf_arch of trb_net16_term_buf
+
+} {} {}} /home/marek/trbnet/basics/pulse_stretch.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/basics/pulse_stretch.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Compiling entity pulse_stretch
+-- Compiling architecture behavioral of pulse_stretch
+
+} {} {}} /home/marek/trbnet/trb_net16_iobuf.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_iobuf.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_iobuf
+-- Compiling architecture trb_net16_iobuf_arch of trb_net16_iobuf
+
+} {} {}} /home/marek/trbnet/trb_net16_ibuf.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_ibuf.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_ibuf
+-- Compiling architecture trb_net16_ibuf_arch of trb_net16_ibuf
+
+} {} {}} /home/marek/trbnet/trb_net16_regIO.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_regIO.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_regio
+-- Compiling architecture trb_net16_regio_arch of trb_net16_regio
+
+} {} {}} /home/marek/ctsaddon/simulation/trb_net16_med_ecp_sfp_gbe.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/trb_net16_med_ecp_sfp_gbe.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_med_ecp_sfp_gbe
+-- Compiling architecture med_ecp_sfp of trb_net16_med_ecp_sfp_gbe
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_beam_structure.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_beam_structure.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_beam_structure
+-- Compiling architecture cts_beam_structure of cts_beam_structure
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_18x256_oreg
+-- Compiling architecture structure of fifo_18x256_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_18x256_oreg
+-- Loading architecture structure of fifo_18x256_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/trb_net16_ipudata.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_ipudata.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net16_ipudata
+-- Compiling architecture trb_net16_ipudata_arch of trb_net16_ipudata
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga2_trig_gen.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga2_trig_gen.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_fpga2_trig_gen
+-- Compiling architecture cts_fpga2_trig_gen of cts_fpga2_trig_gen
+
+} {} {}} /home/marek/ctsaddon/simulation/ddr2_busses.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/ddr2_busses.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity ddr2_busses
+-- Compiling architecture ddr2_busses of ddr2_busses
+
+} {} {}} /home/marek/trbnet/trb_net_CRC.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net_CRC.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net_crc
+-- Compiling architecture trb_net_crc_arch of trb_net_crc
+
+} {} {}} /home/marek/trbnet/trb_net16_io_multiplexer.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_io_multiplexer.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_io_multiplexer
+-- Compiling architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity spi_dpram_32_to_8
+-- Compiling architecture structure of spi_dpram_32_to_8
+-- Compiling configuration structure_con
+-- Loading entity spi_dpram_32_to_8
+-- Loading architecture structure of spi_dpram_32_to_8
+-- Loading package vital_timing
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity vhi
+-- Loading entity vlo
+
+} {} {}} /home/marek/ctsaddon/simulation/delay_fifo.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/delay_fifo.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity delay_fifo
+-- Compiling architecture structure of delay_fifo
+-- Compiling configuration structure_con
+-- Loading entity delay_fifo
+-- Loading architecture structure of delay_fifo
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity pdp16ka
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity vlo
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+
+} {} {}} /home/marek/ctsaddon/simulation/ddr2_3out_clkdiv.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/ddr2_3out_clkdiv.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity ddr2_3out_clkdiv
+-- Compiling architecture structure of ddr2_3out_clkdiv
+-- Compiling configuration structure_con
+-- Loading entity ddr2_3out_clkdiv
+-- Loading architecture structure of ddr2_3out_clkdiv
+-- Loading package vital_timing
+-- Loading package vital_primitives
+-- Loading entity oddrx2a
+-- Loading package global
+-- Loading entity clkdiv
+-- Loading entity ob
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_polarity_check.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_polarity_check.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity cts_polarity_check
+-- Compiling architecture cts_polarity_check of cts_polarity_check
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_delay_large.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_delay_large.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity cts_delay_large
+-- Compiling architecture cts_delay_large of cts_delay_large
+
+} {} {}} /home/marek/trbnet/trb_net16_api_base.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_api_base.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_api_base
+-- Compiling architecture trb_net16_api_base_arch of trb_net16_api_base
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_18x16_media_interface
+-- Compiling architecture structure of fifo_18x16_media_interface
+-- Compiling configuration structure_con
+-- Loading entity fifo_18x16_media_interface
+-- Loading architecture structure of fifo_18x16_media_interface
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity vlo
+-- Loading package mem1
+-- Loading entity dpr16x4a
+
+} {} {}} /home/marek/ctsaddon/simulation/pll_in200_out400.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/pll_in200_out400.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity pll_in200_out400
+-- Compiling architecture structure of pll_in200_out400
+-- Compiling configuration structure_con
+-- Loading entity pll_in200_out400
+-- Loading architecture structure of pll_in200_out400
+-- Loading package vital_timing
+-- Loading entity vlo
+-- Loading entity vhi
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package global
+-- Loading package mem3
+-- Loading entity ehxplla
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga2_reg_mem.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga2_reg_mem.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity cts_fpga2_reg_mem
+-- Compiling architecture structure of cts_fpga2_reg_mem
+-- Compiling configuration structure_con
+-- Loading entity cts_fpga2_reg_mem
+-- Loading architecture structure of cts_fpga2_reg_mem
+-- Loading package vital_timing
+-- Loading entity vhi
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity vlo
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_readout.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_readout.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_readout
+-- Compiling architecture cts_readout of cts_readout
+
+} {} {}} /home/marek/trbnet/trb_net16_endpoint_hades_cts.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_endpoint_hades_cts.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_endpoint_hades_cts
+-- Compiling architecture trb_net16_endpoint_hades_cts_arch of trb_net16_endpoint_hades_cts
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_18x1k_oreg
+-- Compiling architecture structure of fifo_18x1k_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_18x1k_oreg
+-- Loading architecture structure of fifo_18x1k_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Compiling entity pcsc
+-- Compiling architecture pcsc_arch of pcsc
+-- Loading package components
+-- Loading package textio
+-- Compiling entity serdes_gbe_all
+-- Compiling architecture serdes_gbe_all_arch of serdes_gbe_all
+
+} {} {}} /home/marek/trbnet/trb_net16_dummy_fifo.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_dummy_fifo.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_signed
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net16_dummy_fifo
+-- Compiling architecture arch_trb_net16_dummy_fifo of trb_net16_dummy_fifo
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_set_width_large.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_set_width_large.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity cts_set_width_large
+-- Compiling architecture cts_set_width_large of cts_set_width_large
+
+} {} {}} /home/marek/trbnet/trb_net_onewire_listener.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net_onewire_listener.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net_onewire_listener
+-- Compiling architecture arch of trb_net_onewire_listener
+
+} {} {}} /home/marek/ctsaddon/simulation/ecp2m_lvl2_trigger_buffer_fifo_1kW.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/ecp2m_lvl2_trigger_buffer_fifo_1kW.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity ecp2m_lvl2_trigger_buffer_fifo_1kw
+-- Compiling architecture structure of ecp2m_lvl2_trigger_buffer_fifo_1kw
+-- Compiling configuration structure_con
+-- Loading entity ecp2m_lvl2_trigger_buffer_fifo_1kw
+-- Loading architecture structure of ecp2m_lvl2_trigger_buffer_fifo_1kw
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity pdpw16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vlo
+-- Loading entity vhi
+
+} {} {}} /home/marek/ctsaddon/simulation/dll_in400_out200.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/dll_in400_out200.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity dll_in400_out200
+-- Compiling architecture structure of dll_in400_out200
+-- Compiling configuration structure_con
+-- Loading entity dll_in400_out200
+-- Loading architecture structure of dll_in400_out200
+-- Loading package vital_timing
+-- Loading entity vlo
+-- Loading entity vhi
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package global
+-- Loading package mem3
+-- Loading entity ciddlla
+
+} {} {}} /home/marek/trbnet/trb_net_pattern_gen.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net_pattern_gen.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net_pattern_gen
+-- Compiling architecture trb_net_pattern_gen_arch of trb_net_pattern_gen
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_components.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_components.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Compiling package cts_components
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_36x4k_oreg
+-- Compiling architecture structure of fifo_36x4k_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_36x4k_oreg
+-- Loading architecture structure of fifo_36x4k_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity mux21
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/special/trb_net_reset_handler.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/special/trb_net_reset_handler.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Compiling entity trb_net_reset_handler
+-- Compiling architecture behavioral of trb_net_reset_handler
+
+} {} {}} /home/marek/ctsaddon/simulation/fifo_1bit_to_32bit.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/fifo_1bit_to_32bit.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_1bit_to_32bit
+-- Compiling architecture structure of fifo_1bit_to_32bit
+-- Compiling configuration structure_con
+-- Loading entity fifo_1bit_to_32bit
+-- Loading architecture structure of fifo_1bit_to_32bit
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity or2
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3bx
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3dx
+-- Loading entity fd1s3bx
+-- Loading entity fadd2b
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity ageb2
+-- Loading entity vlo
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga2_lvl2.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga2_lvl2.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity cts_fpga2_lvl2
+-- Compiling architecture cts_fpga2_lvl2 of cts_fpga2_lvl2
+
+} {} {}} /home/marek/ctsaddon/simulation/beam_structure_fifo.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/beam_structure_fifo.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity beam_structure_fifo
+-- Compiling architecture structure of beam_structure_fifo
+-- Compiling configuration structure_con
+-- Loading entity beam_structure_fifo
+-- Loading architecture structure of beam_structure_fifo
+-- Loading package vital_timing
+-- Loading entity vlo
+-- Loading entity vhi
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity fifo16ka
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity lattice_ecp2m_fifo_18x1k
+-- Compiling architecture structure of lattice_ecp2m_fifo_18x1k
+-- Compiling configuration structure_con
+-- Loading entity lattice_ecp2m_fifo_18x1k
+-- Loading architecture structure of lattice_ecp2m_fifo_18x1k
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity vlo
+
+} {} {}} /home/marek/ctsaddon/simulation/fifo_2bit_to_32bit.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/fifo_2bit_to_32bit.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_2bit_to_32bit
+-- Compiling architecture structure of fifo_2bit_to_32bit
+-- Compiling configuration structure_con
+-- Loading entity fifo_2bit_to_32bit
+-- Loading architecture structure of fifo_2bit_to_32bit
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity or2
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3bx
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3dx
+-- Loading entity fd1s3bx
+-- Loading entity fadd2b
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity ageb2
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/trb_net_onewire.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net_onewire.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net_onewire
+-- Compiling architecture trb_net_onewire_arch of trb_net_onewire
+
+} {} {}} /home/marek/trbv2/etrax_write_read_tb.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbv2/etrax_write_read_tb.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Loading package trb_net_std
+-- Compiling entity etrax_write_read_tb
+-- Compiling architecture etrax_write_read_tb of etrax_write_read_tb
+
+} {} {}} /home/marek/trbnet/basics/ram_dp.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/basics/ram_dp.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity ram_dp
+-- Compiling architecture ram_dp_arch of ram_dp
+
+} {} {}} /home/marek/ctsaddon/simulation/scm_fifo_1bit_to_32bit.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/scm_fifo_1bit_to_32bit.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity scm_fifo_1bit_to_32bit
+-- Compiling architecture structure of scm_fifo_1bit_to_32bit
+-- Compiling configuration structure_con
+-- Loading entity scm_fifo_1bit_to_32bit
+-- Loading architecture structure of scm_fifo_1bit_to_32bit
+-- Loading package vital_timing
+-- Loading entity vhi
+-- Loading entity vlo
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity fifo16ka
+
+} {} {}} /home/marek/ctsaddon/simulation/ddr_lvl1_trigger.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/ddr_lvl1_trigger.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity ddr_lvl1_trigger
+-- Compiling architecture ddr_lvl1_trigger of ddr_lvl1_trigger
+
+} {} {}} /home/marek/trbnet/trb_net16_regio_bus_handler.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_regio_bus_handler.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_regio_bus_handler
+-- Compiling architecture regio_bus_handler_arch of trb_net16_regio_bus_handler
+
+} {} {}} /home/marek/ctsaddon/simulation/scm_fifo_2bit_to_32bit.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/scm_fifo_2bit_to_32bit.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity scm_fifo_2bit_to_32bit
+-- Compiling architecture structure of scm_fifo_2bit_to_32bit
+-- Compiling configuration structure_con
+-- Loading entity scm_fifo_2bit_to_32bit
+-- Loading architecture structure of scm_fifo_2bit_to_32bit
+-- Loading package vital_timing
+-- Loading entity vhi
+-- Loading entity vlo
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity fifo16ka
+
+} {} {}} /home/marek/ctsaddon/simulation/fifo_4bit_to_32bit.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/fifo_4bit_to_32bit.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_4bit_to_32bit
+-- Compiling architecture structure of fifo_4bit_to_32bit
+-- Compiling configuration structure_con
+-- Loading entity fifo_4bit_to_32bit
+-- Loading architecture structure of fifo_4bit_to_32bit
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity or2
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3bx
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3dx
+-- Loading entity fd1s3bx
+-- Loading entity fadd2b
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity ageb2
+-- Loading entity vlo
+
+} {} {}} /home/marek/ctsaddon/cts_fpga1_test.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/cts_fpga1_test.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_fpga1_test
+-- Compiling architecture cts_fpga1_test of cts_fpga1_test
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_36x8k_oreg
+-- Compiling architecture structure of fifo_36x8k_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_36x8k_oreg
+-- Loading architecture structure of fifo_36x8k_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity mux41
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Compiling entity pcsc
+-- Compiling architecture pcsc_arch of pcsc
+-- Loading package components
+-- Loading package textio
+-- Compiling entity serdes_gbe_0
+-- Compiling architecture serdes_gbe_0_arch of serdes_gbe_0
+
+} {} {}} /home/marek/ctsaddon/simulation/scm_fifo_4bit_to_32bit.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/scm_fifo_4bit_to_32bit.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity scm_fifo_4bit_to_32bit
+-- Compiling architecture structure of scm_fifo_4bit_to_32bit
+-- Compiling configuration structure_con
+-- Loading entity scm_fifo_4bit_to_32bit
+-- Loading architecture structure of scm_fifo_4bit_to_32bit
+-- Loading package vital_timing
+-- Loading entity vhi
+-- Loading entity vlo
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity fifo16ka
+
+} {} {}} /home/marek/trbnet/trb_net_sbuf5.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net_sbuf5.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Compiling entity trb_net_sbuf5
+-- Compiling architecture trb_net_sbuf5_arch of trb_net_sbuf5
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling package lattice_ecp2m_fifo
+
+} {} {}} /home/marek/trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_med_ecp_sfp_4_gbe
+-- Compiling architecture med_ecp_sfp_4 of trb_net16_med_ecp_sfp_4_gbe
+
+} {} {}} /home/marek/trbnet/special/handler_ipu.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/special/handler_ipu.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Compiling entity handler_ipu
+-- Compiling architecture handler_ipu_arch of handler_ipu
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_36x256_oreg
+-- Compiling architecture structure of fifo_36x256_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_36x256_oreg
+-- Loading architecture structure of fifo_36x256_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity pdpw16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/ctsaddon/simulation/fifo16bit_synch.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/fifo16bit_synch.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity fifo16bit_synch
+-- Compiling architecture structure of fifo16bit_synch
+-- Compiling configuration structure_con
+-- Loading entity fifo16bit_synch
+-- Loading architecture structure of fifo16bit_synch
+-- Loading package vital_timing
+-- Loading entity vhi
+-- Loading entity vlo
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity fifo16ka
+
+} {} {}} /home/marek/ctsaddon/simulation/version.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/version.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling package version
+
+} {} {}} /home/marek/ctsaddon/ddr2_13out_clkdiv.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/ddr2_13out_clkdiv.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity ddr2_13out_clkdiv
+-- Compiling architecture structure of ddr2_13out_clkdiv
+-- Compiling configuration structure_con
+-- Loading entity ddr2_13out_clkdiv
+-- Loading architecture structure of ddr2_13out_clkdiv
+-- Loading package vital_timing
+-- Loading package vital_primitives
+-- Loading entity oddrx2a
+-- Loading package global
+-- Loading entity clkdiv
+-- Loading entity ob
+
+} {} {}} /home/marek/ctsaddon/simulation/fifo_8bit_to_32bit.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/fifo_8bit_to_32bit.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_8bit_to_32bit
+-- Compiling architecture structure of fifo_8bit_to_32bit
+-- Compiling configuration structure_con
+-- Loading entity fifo_8bit_to_32bit
+-- Loading architecture structure of fifo_8bit_to_32bit
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity or2
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3bx
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3dx
+-- Loading entity fd1s3bx
+-- Loading entity fadd2b
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity ageb2
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_8b_16b_dualport.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_8b_16b_dualport.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity lattice_ecp2m_fifo_8b_16b_dualport
+-- Compiling architecture structure of lattice_ecp2m_fifo_8b_16b_dualport
+-- Compiling configuration structure_con
+-- Loading entity lattice_ecp2m_fifo_8b_16b_dualport
+-- Loading architecture structure of lattice_ecp2m_fifo_8b_16b_dualport
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity or2
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3bx
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3dx
+-- Loading entity fd1s3bx
+-- Loading entity fadd2b
+-- Loading entity cu2
+-- Loading entity fsub2b
+-- Loading entity vhi
+-- Loading entity ageb2
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_36x32k_oreg
+-- Compiling architecture structure of fifo_36x32k_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_36x32k_oreg
+-- Loading architecture structure of fifo_36x32k_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity mux161
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/ctsaddon/simulation/scm_fifo_8bit_to_32bit.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/scm_fifo_8bit_to_32bit.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity scm_fifo_8bit_to_32bit
+-- Compiling architecture structure of scm_fifo_8bit_to_32bit
+-- Compiling configuration structure_con
+-- Loading entity scm_fifo_8bit_to_32bit
+-- Loading architecture structure of scm_fifo_8bit_to_32bit
+-- Loading package vital_timing
+-- Loading entity vhi
+-- Loading entity vlo
+-- Loading package vital_primitives
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package global
+-- Loading package mem3
+-- Loading entity fifo16ka
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_lvl2_fifo.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_lvl2_fifo.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_fpga2_lvl1_lvl2_fifo
+-- Compiling architecture cts_fpga2_lvl1_lvl2_fifo of cts_fpga2_lvl1_lvl2_fifo
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_downscale.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_downscale.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity cts_downscale
+-- Compiling architecture cts_downscale of cts_downscale
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga1_test_set_width.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga1_test_set_width.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_fpga1_test_set_width
+-- Compiling architecture cts_fpga1_test_set_width of cts_fpga1_test_set_width
+
+} {} {}} /home/marek/trbnet/trb_net_priority_encoder.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net_priority_encoder.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net_priority_encoder
+-- Compiling architecture trb_net_priority_encoder_arch of trb_net_priority_encoder
+
+} {} {}} /home/marek/trbnet/trb_net16_obuf.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_obuf.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_obuf
+-- Compiling architecture trb_net16_obuf_arch of trb_net16_obuf
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_align_signals.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_align_signals.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_align_signals
+-- Compiling architecture cts_align_signals of cts_align_signals
+
+} {} {}} /home/marek/trbnet/trb_net16_term_ibuf.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_term_ibuf.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net16_term_ibuf
+-- Compiling architecture trb_net16_term_ibuf_arch of trb_net16_term_ibuf
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_36x1k_oreg
+-- Compiling architecture structure of fifo_36x1k_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_36x1k_oreg
+-- Loading architecture structure of fifo_36x1k_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga1_tb.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga1_tb.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package textio
+-- Loading package std_logic_textio
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Compiling entity cts_fpga1_tb
+-- Compiling architecture behavior of cts_fpga1_tb
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_18x2k_oreg
+-- Compiling architecture structure of fifo_18x2k_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_18x2k_oreg
+-- Loading architecture structure of fifo_18x2k_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/basics/ram_16x16_dp.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/basics/ram_16x16_dp.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Compiling entity ram_16x16_dp
+-- Compiling architecture ram_16x16_dp_arch of ram_16x16_dp
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_data_downscale.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_data_downscale.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_fpga2_lvl1_data_downscale
+-- Compiling architecture cts_fpga2_lvl1_data_downscale of cts_fpga2_lvl1_data_downscale
+
+} {} {}} /home/marek/ctsaddon/simulation/etrax_reg_mem.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/etrax_reg_mem.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package textio
+-- Loading package std_logic_textio
+-- Compiling entity etrax_reg_mem
+-- Compiling architecture etrax_reg_mem of etrax_reg_mem
+
+} {} {}} /home/marek/ctsaddon/simulation/dll_edge.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/dll_edge.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity dll_edge
+-- Compiling architecture structure of dll_edge
+-- Compiling configuration structure_con
+-- Loading entity dll_edge
+-- Loading architecture structure of dll_edge
+-- Loading package vital_timing
+-- Loading entity vlo
+-- Loading entity vhi
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package global
+-- Loading package mem3
+-- Loading entity ciddlla
+
+} {} {}} /home/marek/ctsaddon/simulation/trb_net16_lsm_sfp.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/trb_net16_lsm_sfp.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net16_lsm_sfp
+-- Compiling architecture lsm_sfp of trb_net16_lsm_sfp
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_fpga1.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_fpga1.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package cts_components
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity cts_fpga1
+-- Compiling architecture cts_fpga1_arch of cts_fpga1
+
+} {} {}} /home/marek/trbnet/basics/signal_sync.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/basics/signal_sync.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Compiling entity signal_sync
+-- Compiling architecture behavioral of signal_sync
+
+} {} {}} /home/marek/ctsaddon/simulation/multiplicity.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/multiplicity.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity multiplicity
+-- Compiling architecture multiplicity of multiplicity
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_trigger_logic.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_trigger_logic.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Compiling entity cts_trigger_logic
+-- Compiling architecture cts_trigger_logic of cts_trigger_logic
+
+} {} {}} /home/marek/trbnet/basics/ram_dp_rw.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/basics/ram_dp_rw.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity ram_dp_rw
+-- Compiling architecture ram_dp_rw_arch of ram_dp_rw
+
+} {} {}} /home/marek/ctsaddon/simulation/ddr2_12out_clkdiv.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/ddr2_12out_clkdiv.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package conversion
+-- Loading package components
+-- Compiling entity ddr2_12out_clkdiv
+-- Compiling architecture structure of ddr2_12out_clkdiv
+-- Compiling configuration structure_con
+-- Loading entity ddr2_12out_clkdiv
+-- Loading architecture structure of ddr2_12out_clkdiv
+-- Loading package vital_timing
+-- Loading package vital_primitives
+-- Loading entity oddrx2a
+-- Loading package global
+-- Loading entity clkdiv
+-- Loading entity ob
+
+} {} {}} /home/marek/ctsaddon/simulation/trb_net_components.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/trb_net_components.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling package trb_net_components
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_signed
+-- Loading package numeric_std
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net16_fifo
+-- Compiling architecture arch_trb_net16_fifo of trb_net16_fifo
+
+} {} {}} /home/marek/trbnet/trb_net16_trigger.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_trigger.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net16_trigger
+-- Compiling architecture trb_net16_trigger_arch of trb_net16_trigger
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity lattice_ecp2m_fifo_16bit_dualport
+-- Compiling architecture structure of lattice_ecp2m_fifo_16bit_dualport
+-- Compiling configuration structure_con
+-- Loading entity lattice_ecp2m_fifo_16bit_dualport
+-- Loading architecture structure of lattice_ecp2m_fifo_16bit_dualport
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity or2
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3bx
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3dx
+-- Loading entity fd1s3bx
+-- Loading entity fadd2b
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity ageb2
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/pll_in100_out100.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/pll_in100_out100.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity pll_in100_out100
+-- Compiling architecture structure of pll_in100_out100
+-- Compiling configuration structure_con
+-- Loading entity pll_in100_out100
+-- Loading architecture structure of pll_in100_out100
+-- Loading package vital_timing
+-- Loading entity vlo
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading entity eplld
+
+} {} {}} /home/marek/trbnet/trb_net16_endpoint_hades_full.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_endpoint_hades_full.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package numeric_std
+-- Loading package trb_net_components
+-- Compiling entity trb_net16_endpoint_hades_full
+-- Compiling architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_one_clock.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_one_clock.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity cts_one_clock
+-- Compiling architecture cts_one_clock of cts_one_clock
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_delay.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_delay.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity cts_delay
+-- Compiling architecture cts_delay of cts_delay
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Loading package lattice_ecp2m_fifo
+-- Compiling entity fifo_var_oreg
+-- Compiling architecture fifo_var_oreg_arch of fifo_var_oreg
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_18x512_oreg
+-- Compiling architecture structure of fifo_18x512_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_18x512_oreg
+-- Loading architecture structure of fifo_18x512_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity pdpw16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/special/handler_data.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/special/handler_data.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package numeric_std
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Loading package trb_net_components
+-- Loading package lattice_ecp2m_fifo
+-- Compiling entity handler_data
+-- Compiling architecture handler_data_arch of handler_data
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_36x16k_oreg
+-- Compiling architecture structure of fifo_36x16k_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_36x16k_oreg
+-- Loading architecture structure of fifo_36x16k_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity mux81
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/trbnet/basics/rom_16x8.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/basics/rom_16x8.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity rom_16x8
+-- Compiling architecture rom_16x8_arch of rom_16x8
+
+} {} {}} /home/marek/trbnet/trb_net_std.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net_std.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Compiling package trb_net_std
+-- Compiling package body trb_net_std
+-- Loading package trb_net_std
+
+} {} {}} /home/marek/ctsaddon/simulation/cts_set_width.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/cts_set_width.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity cts_set_width
+-- Compiling architecture cts_set_width of cts_set_width
+
+} {} {}} /home/marek/trbnet/trb_net16_addresses.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/trb_net16_addresses.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package trb_net_std
+-- Compiling entity trb_net16_addresses
+-- Compiling architecture trb_net16_addresses_arch of trb_net16_addresses
+
+} {} {}} /home/marek/ctsaddon/cts_polarity_check.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/cts_polarity_check.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package numeric_std
+-- Loading package version
+-- Compiling entity cts_polarity_check
+-- Compiling architecture cts_polarity_check of cts_polarity_check
+
+} {} {}} /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_36x2k_oreg
+-- Compiling architecture structure of fifo_36x2k_oreg
+-- Compiling configuration structure_con
+-- Loading entity fifo_36x2k_oreg
+-- Loading architecture structure of fifo_36x2k_oreg
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3bx
+-- Loading entity fd1s3dx
+-- Loading entity fd1p3bx
+-- Loading entity fadd2b
+-- Loading entity cb2
+-- Loading entity aleb2
+-- Loading entity ageb2
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity vlo
+
+} {} {}} /home/marek/ctsaddon/simulation/fifo_16bit_to_32bit.vhd {1 {vcom -work work -2002 -explicit -vopt /home/marek/ctsaddon/simulation/fifo_16bit_to_32bit.vhd
+Model Technology ModelSim SE vcom 6.6b Compiler 2010.05 May 21 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package components
+-- Compiling entity fifo_16bit_to_32bit
+-- Compiling architecture structure of fifo_16bit_to_32bit
+-- Compiling configuration structure_con
+-- Loading entity fifo_16bit_to_32bit
+-- Loading architecture structure of fifo_16bit_to_32bit
+-- Loading package vital_timing
+-- Loading entity and2
+-- Loading entity inv
+-- Loading entity or2
+-- Loading entity xor2
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Loading package vital_primitives
+-- Loading package mem2
+-- Loading entity rom16x1
+-- Loading package global
+-- Loading package mem3
+-- Loading entity dp16kb
+-- Loading entity fd1p3bx
+-- Loading entity fd1p3dx
+-- Loading entity fd1s3dx
+-- Loading entity fd1s3bx
+-- Loading entity fadd2b
+-- Loading entity cu2
+-- Loading entity vhi
+-- Loading entity fsub2b
+-- Loading entity ageb2
+-- Loading entity vlo
+
+} {} {}}
diff --git a/cts_witdh_rom_simulation.vhd b/cts_witdh_rom_simulation.vhd
new file mode 100644 (file)
index 0000000..b394352
--- /dev/null
@@ -0,0 +1,40 @@
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+entity cts_width_rom_simulation is
+  port (
+    ADDRESS                    : in std_logic_vector(8 downto 0);
+    OutClock                   : in  std_logic;
+    OutClockEn                 : in std_logic;
+    RESET                      : in  std_logic;
+    Q                          : out std_logic_vector(35 downto 0)
+  );
+end cts_width_rom_simulation;
+
+architecture cts_width_rom_simulation of cts_width_rom_simulation is
+signal initval : std_logic_vector(64*80*4-1 downto 0) := x"000000000000000000000000000000000003FFFF3FFFF3FFFF3FFFF1FFFF0FFFF07FFF03FFF00000000000000000000000000000000000000003FFFF3FFFF3FFFF1FFFF0FFFF07FFF03FFF01FFF00000000000000000000000000000000000000003FFFF3FFFF1FFFF0FFFF07FFF03FFF01FFF00FFF00000000000000000000000000000000000000003FFFF1FFFF0FFFF07FFF03FFF01FFF00FFF007FF00000000000000000000000000000000000000001FFFF0FFFF07FFF03FFF01FFF00FFF007FF003FF00000000000000000000000000000000000000000FFFF07FFF03FFF01FFF00FFF007FF003FF001FF000000000000000000000000000000000000000007FFF03FFF01FFF00FFF007FF003FF001FF000FF000000000000000000000000000000000000000003FFF01FFF00FFF007FF003FF001FF000FF0007F000000000000000000000000000000000000000001FFF00FFF007FF003FF001FF000FF0007F0003F000000000000000000000000000000000000000000FFF007FF003FF001FF000FF0007F0003F0001F0000000000000000000000000000000000000000007FF003FF001FF000FF0007F0003F0001F0000F0000000000000000000000000000000000000000003FF001FF000FF0007F0003F0001F0000F000070000000000000000000000000000000000000000001FF000FF0007F0003F0001F0000F00007000030000000000000000000000000000000000000000000FF0007F0003F0001F0000F00007000030000100000000000000000000000000000000000000000007F0003F0001F0000F0000700003000010000000000000000000000000000000000000000000000003F0001F0000F000070000300001000000000000000000000000000000000000000000000000000001F0000F00007000030000100000000000000000000000000000000000000000000000000000000000F00007000030000100000000000000000000000000000000000000000000000000000000000000007000030000100000000000000000000000000000000000000000000000000000000000000000000030000100000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE1FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC1FFFE0FFFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF81FFFC0FFFE07FFF00000000000000000000000000000000000000003FF803FFC03FFE03FFF01FFF80FFFC07FFE03FFF00000000000000000000000000000000000000003FF803FFC03FFE01FFF00FFF807FFC03FFE01FFF00000000000000000000000000000000000000003FF803FFC01FFE00FFF007FF803FFC01FFE00FFF00000000000000000000000000000000000000003FF801FFC00FFE007FF003FF801FFC00FFE007FF00000000000000000000000000000000000000001FF800FFC007FE003FF001FF800FFC007FE003FF00000000000000000000000000000000000000000FF8007FC003FE001FF000FF8007FC003FE001FF000000000000000000000000000000000000000007F8003FC001FE000FF0007F8003FC001FE000FF000000000000000000000000000000000000000003F8001FC000FE0007F0003F8001FC000FE0007F000000000000000000000000000000000000000001F8000FC0007E0003F0001F8000FC0007E0003F000000000000000000000000000000000000000000F80007C0003E0001F0000F80007C0003E0001F000000000000000000000000000000000000000000780003C0001E0000F0000780003C0001E0000F000000000000000000000000000000000000000000380001C0000E000070000380001C0000E00007000000000000000000000000000000000000000000180000C00006000030000180000C00006000030000000000000000000000000000000000000000000800004000020000100000800004000020000100000";
+
+
+begin
+
+  SEND_DATA : process (OutClock, RESET)
+  begin
+if rising_edge(OutClock) then
+  if RESET = '1' then
+        q <= (others => '0');
+      else
+        q <=  x"0000" & initval( (conv_integer(ADDRESS)+1)*4*5-1 downto conv_integer(ADDRESS)*4*5);
+      end if;   
+    end if;
+  end process SEND_DATA;
+  
+
+end cts_width_rom_simulation;
+
+       
diff --git a/fifo12bit_synch.vhd b/fifo12bit_synch.vhd
new file mode 100644 (file)
index 0000000..3d8e581
--- /dev/null
@@ -0,0 +1,180 @@
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module  Version: 5.4
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo12bit_synch -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 12 -rwidth 12 -regout -no_enable -pe 10 -pf 508 -sync_reset -e 
+
+-- Wed Feb 15 13:42:03 2012
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo12bit_synch is
+    port (
+        Data: in  std_logic_vector(11 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(11 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostEmpty: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo12bit_synch;
+
+architecture Structure of fifo12bit_synch is
+
+    -- internal signal declarations
+    signal Empty_int: std_logic;
+    signal Full_int: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component FIFO16KA
+    -- synopsys translate_off
+        generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); 
+                FULLPOINTER : in std_logic_vector(14 downto 0); 
+                AFPOINTER1 : in std_logic_vector(14 downto 0); 
+                AEPOINTER1 : in std_logic_vector(14 downto 0); 
+                AFPOINTER : in std_logic_vector(14 downto 0); 
+                AEPOINTER : in std_logic_vector(14 downto 0); 
+                CSDECODE_R : in std_logic_vector(1 downto 0); 
+                CSDECODE_W : in std_logic_vector(1 downto 0); 
+                RESETMODE : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+    -- synopsys translate_on
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            FULLI: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; EMPTYI: in  std_logic; 
+            CSR0: in  std_logic; CSR1: in  std_logic; WE: in  std_logic; 
+            RE: in  std_logic; CLKW: in  std_logic; CLKR: in  std_logic; 
+            RST: in  std_logic; RPRST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic; 
+            EF: out  std_logic; AEF: out  std_logic; AFF: out  std_logic; 
+            FF: out  std_logic);
+    end component;
+    attribute FULLPOINTER1 : string; 
+    attribute FULLPOINTER : string; 
+    attribute AFPOINTER1 : string; 
+    attribute AFPOINTER : string; 
+    attribute AEPOINTER1 : string; 
+    attribute AEPOINTER : string; 
+    attribute RESETMODE : string; 
+    attribute REGMODE : string; 
+    attribute CSDECODE_R : string; 
+    attribute CSDECODE_W : string; 
+    attribute DATA_WIDTH_R : string; 
+    attribute DATA_WIDTH_W : string; 
+    attribute FULLPOINTER1 of fifo12bit_synch_0_0 : label is "0b011111111000001";
+    attribute FULLPOINTER of fifo12bit_synch_0_0 : label is "0b011111111100001";
+    attribute AFPOINTER1 of fifo12bit_synch_0_0 : label is "0b011111101000001";
+    attribute AFPOINTER of fifo12bit_synch_0_0 : label is "0b011111101100001";
+    attribute AEPOINTER1 of fifo12bit_synch_0_0 : label is "0b000000101111111";
+    attribute AEPOINTER of fifo12bit_synch_0_0 : label is "0b000000101011111";
+    attribute RESETMODE of fifo12bit_synch_0_0 : label is "SYNC";
+    attribute REGMODE of fifo12bit_synch_0_0 : label is "OUTREG";
+    attribute CSDECODE_R of fifo12bit_synch_0_0 : label is "0b11";
+    attribute CSDECODE_W of fifo12bit_synch_0_0 : label is "0b11";
+    attribute DATA_WIDTH_R of fifo12bit_synch_0_0 : label is "36";
+    attribute DATA_WIDTH_W of fifo12bit_synch_0_0 : label is "36";
+    attribute syn_keep : boolean;
+
+begin
+    -- component instantiation statements
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    fifo12bit_synch_0_0: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", 
+        AFPOINTER1=> "011111101000001", AFPOINTER=> "011111101100001", 
+        AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111", 
+        RESETMODE=> "SYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        -- synopsys translate_on
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo, 
+            DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo, 
+            DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo, 
+            DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo, 
+            DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo, 
+            DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, 
+            DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, 
+            DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, 
+            FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, 
+            EMPTYI=>Empty_int, CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn, 
+            RE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, 
+            RPRST=>RPReset, DO0=>open, DO1=>open, DO2=>open, DO3=>open, 
+            DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open, 
+            DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open, 
+            DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), 
+            DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), 
+            DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), 
+            DO29=>Q(11), DO30=>open, DO31=>open, DO32=>open, DO33=>open, 
+            DO34=>open, DO35=>open, EF=>Empty_int, AEF=>AlmostEmpty, 
+            AFF=>AlmostFull, FF=>Full_int);
+
+    Empty <= Empty_int;
+    Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo12bit_synch is
+    for Structure
+        for all:VHI use entity SCM.VHI(V); end for;
+        for all:VLO use entity SCM.VLO(V); end for;
+        for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/fifo48bit_synch.vhd b/fifo48bit_synch.vhd
new file mode 100644 (file)
index 0000000..748afd8
--- /dev/null
@@ -0,0 +1,226 @@
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module  Version: 5.4
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo48bit_synch -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 48 -rwidth 48 -regout -no_enable -pe 10 -pf 508 -sync_reset -e 
+
+-- Tue Feb 14 12:26:50 2012
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo48bit_synch is
+    port (
+        Data: in  std_logic_vector(47 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(47 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostEmpty: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo48bit_synch;
+
+architecture Structure of fifo48bit_synch is
+
+    -- internal signal declarations
+    signal Empty_int: std_logic;
+    signal Full_int: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component FIFO16KA
+    -- synopsys translate_off
+        generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); 
+                FULLPOINTER : in std_logic_vector(14 downto 0); 
+                AFPOINTER1 : in std_logic_vector(14 downto 0); 
+                AEPOINTER1 : in std_logic_vector(14 downto 0); 
+                AFPOINTER : in std_logic_vector(14 downto 0); 
+                AEPOINTER : in std_logic_vector(14 downto 0); 
+                CSDECODE_R : in std_logic_vector(1 downto 0); 
+                CSDECODE_W : in std_logic_vector(1 downto 0); 
+                RESETMODE : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+    -- synopsys translate_on
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            FULLI: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; EMPTYI: in  std_logic; 
+            CSR0: in  std_logic; CSR1: in  std_logic; WE: in  std_logic; 
+            RE: in  std_logic; CLKW: in  std_logic; CLKR: in  std_logic; 
+            RST: in  std_logic; RPRST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic; 
+            EF: out  std_logic; AEF: out  std_logic; AFF: out  std_logic; 
+            FF: out  std_logic);
+    end component;
+    attribute FULLPOINTER1 : string; 
+    attribute FULLPOINTER : string; 
+    attribute AFPOINTER1 : string; 
+    attribute AFPOINTER : string; 
+    attribute AEPOINTER1 : string; 
+    attribute AEPOINTER : string; 
+    attribute RESETMODE : string; 
+    attribute REGMODE : string; 
+    attribute CSDECODE_R : string; 
+    attribute CSDECODE_W : string; 
+    attribute DATA_WIDTH_R : string; 
+    attribute DATA_WIDTH_W : string; 
+    attribute FULLPOINTER1 of fifo48bit_synch_0_1 : label is "0b011111111000001";
+    attribute FULLPOINTER of fifo48bit_synch_0_1 : label is "0b011111111100001";
+    attribute AFPOINTER1 of fifo48bit_synch_0_1 : label is "0b011111101000001";
+    attribute AFPOINTER of fifo48bit_synch_0_1 : label is "0b011111101100001";
+    attribute AEPOINTER1 of fifo48bit_synch_0_1 : label is "0b000000101111111";
+    attribute AEPOINTER of fifo48bit_synch_0_1 : label is "0b000000101011111";
+    attribute RESETMODE of fifo48bit_synch_0_1 : label is "SYNC";
+    attribute REGMODE of fifo48bit_synch_0_1 : label is "OUTREG";
+    attribute CSDECODE_R of fifo48bit_synch_0_1 : label is "0b11";
+    attribute CSDECODE_W of fifo48bit_synch_0_1 : label is "0b11";
+    attribute DATA_WIDTH_R of fifo48bit_synch_0_1 : label is "36";
+    attribute DATA_WIDTH_W of fifo48bit_synch_0_1 : label is "36";
+    attribute FULLPOINTER1 of fifo48bit_synch_1_0 : label is "0b000000000000000";
+    attribute FULLPOINTER of fifo48bit_synch_1_0 : label is "0b111111111111111";
+    attribute AFPOINTER1 of fifo48bit_synch_1_0 : label is "0b000000000000000";
+    attribute AFPOINTER of fifo48bit_synch_1_0 : label is "0b111111111111111";
+    attribute AEPOINTER1 of fifo48bit_synch_1_0 : label is "0b000000000000000";
+    attribute AEPOINTER of fifo48bit_synch_1_0 : label is "0b111111111111111";
+    attribute RESETMODE of fifo48bit_synch_1_0 : label is "SYNC";
+    attribute REGMODE of fifo48bit_synch_1_0 : label is "OUTREG";
+    attribute CSDECODE_R of fifo48bit_synch_1_0 : label is "0b11";
+    attribute CSDECODE_W of fifo48bit_synch_1_0 : label is "0b11";
+    attribute DATA_WIDTH_R of fifo48bit_synch_1_0 : label is "36";
+    attribute DATA_WIDTH_W of fifo48bit_synch_1_0 : label is "36";
+    attribute syn_keep : boolean;
+
+begin
+    -- component instantiation statements
+    fifo48bit_synch_0_1: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", 
+        AFPOINTER1=> "011111101000001", AFPOINTER=> "011111101100001", 
+        AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111", 
+        RESETMODE=> "SYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        -- synopsys translate_on
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), 
+            DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), 
+            FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, 
+            EMPTYI=>Empty_int, CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn, 
+            RE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, 
+            RPRST=>RPReset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), 
+            DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), 
+            DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), 
+            DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), 
+            DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), 
+            DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), 
+            DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), 
+            DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), 
+            DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, AEF=>AlmostEmpty, 
+            AFF=>AlmostFull, FF=>Full_int);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    fifo48bit_synch_1_0: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111", 
+        AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111", 
+        AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111", 
+        RESETMODE=> "SYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        -- synopsys translate_on
+        port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), 
+            DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), 
+            DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), 
+            DI11=>Data(47), DI12=>scuba_vlo, DI13=>scuba_vlo, 
+            DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo, 
+            DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo, 
+            DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo, 
+            DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo, 
+            DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo, 
+            DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo, 
+            DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, 
+            DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>RdEn, 
+            CSR1=>scuba_vhi, WE=>WrEn, RE=>scuba_vhi, CLKW=>WrClock, 
+            CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>open, 
+            DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open, 
+            DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open, 
+            DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open, 
+            DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37), 
+            DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), 
+            DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), 
+            DO28=>Q(46), DO29=>Q(47), DO30=>open, DO31=>open, DO32=>open, 
+            DO33=>open, DO34=>open, DO35=>open, EF=>open, AEF=>open, 
+            AFF=>open, FF=>open);
+
+    Empty <= Empty_int;
+    Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo48bit_synch is
+    for Structure
+        for all:VHI use entity SCM.VHI(V); end for;
+        for all:VLO use entity SCM.VLO(V); end for;
+        for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/fifo52bit_synch.vhd b/fifo52bit_synch.vhd
new file mode 100644 (file)
index 0000000..cd4ebd7
--- /dev/null
@@ -0,0 +1,226 @@
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module  Version: 5.4
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo52bit_synch -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 52 -rwidth 52 -regout -no_enable -pe 10 -pf 508 -sync_reset -e 
+
+-- Fri Feb 17 19:26:21 2012
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo52bit_synch is
+    port (
+        Data: in  std_logic_vector(51 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(51 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostEmpty: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo52bit_synch;
+
+architecture Structure of fifo52bit_synch is
+
+    -- internal signal declarations
+    signal Empty_int: std_logic;
+    signal Full_int: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component FIFO16KA
+    -- synopsys translate_off
+        generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); 
+                FULLPOINTER : in std_logic_vector(14 downto 0); 
+                AFPOINTER1 : in std_logic_vector(14 downto 0); 
+                AEPOINTER1 : in std_logic_vector(14 downto 0); 
+                AFPOINTER : in std_logic_vector(14 downto 0); 
+                AEPOINTER : in std_logic_vector(14 downto 0); 
+                CSDECODE_R : in std_logic_vector(1 downto 0); 
+                CSDECODE_W : in std_logic_vector(1 downto 0); 
+                RESETMODE : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+    -- synopsys translate_on
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            FULLI: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; EMPTYI: in  std_logic; 
+            CSR0: in  std_logic; CSR1: in  std_logic; WE: in  std_logic; 
+            RE: in  std_logic; CLKW: in  std_logic; CLKR: in  std_logic; 
+            RST: in  std_logic; RPRST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic; 
+            EF: out  std_logic; AEF: out  std_logic; AFF: out  std_logic; 
+            FF: out  std_logic);
+    end component;
+    attribute FULLPOINTER1 : string; 
+    attribute FULLPOINTER : string; 
+    attribute AFPOINTER1 : string; 
+    attribute AFPOINTER : string; 
+    attribute AEPOINTER1 : string; 
+    attribute AEPOINTER : string; 
+    attribute RESETMODE : string; 
+    attribute REGMODE : string; 
+    attribute CSDECODE_R : string; 
+    attribute CSDECODE_W : string; 
+    attribute DATA_WIDTH_R : string; 
+    attribute DATA_WIDTH_W : string; 
+    attribute FULLPOINTER1 of fifo52bit_synch_0_1 : label is "0b011111111000001";
+    attribute FULLPOINTER of fifo52bit_synch_0_1 : label is "0b011111111100001";
+    attribute AFPOINTER1 of fifo52bit_synch_0_1 : label is "0b011111101000001";
+    attribute AFPOINTER of fifo52bit_synch_0_1 : label is "0b011111101100001";
+    attribute AEPOINTER1 of fifo52bit_synch_0_1 : label is "0b000000101111111";
+    attribute AEPOINTER of fifo52bit_synch_0_1 : label is "0b000000101011111";
+    attribute RESETMODE of fifo52bit_synch_0_1 : label is "SYNC";
+    attribute REGMODE of fifo52bit_synch_0_1 : label is "OUTREG";
+    attribute CSDECODE_R of fifo52bit_synch_0_1 : label is "0b11";
+    attribute CSDECODE_W of fifo52bit_synch_0_1 : label is "0b11";
+    attribute DATA_WIDTH_R of fifo52bit_synch_0_1 : label is "36";
+    attribute DATA_WIDTH_W of fifo52bit_synch_0_1 : label is "36";
+    attribute FULLPOINTER1 of fifo52bit_synch_1_0 : label is "0b000000000000000";
+    attribute FULLPOINTER of fifo52bit_synch_1_0 : label is "0b111111111111111";
+    attribute AFPOINTER1 of fifo52bit_synch_1_0 : label is "0b000000000000000";
+    attribute AFPOINTER of fifo52bit_synch_1_0 : label is "0b111111111111111";
+    attribute AEPOINTER1 of fifo52bit_synch_1_0 : label is "0b000000000000000";
+    attribute AEPOINTER of fifo52bit_synch_1_0 : label is "0b111111111111111";
+    attribute RESETMODE of fifo52bit_synch_1_0 : label is "SYNC";
+    attribute REGMODE of fifo52bit_synch_1_0 : label is "OUTREG";
+    attribute CSDECODE_R of fifo52bit_synch_1_0 : label is "0b11";
+    attribute CSDECODE_W of fifo52bit_synch_1_0 : label is "0b11";
+    attribute DATA_WIDTH_R of fifo52bit_synch_1_0 : label is "36";
+    attribute DATA_WIDTH_W of fifo52bit_synch_1_0 : label is "36";
+    attribute syn_keep : boolean;
+
+begin
+    -- component instantiation statements
+    fifo52bit_synch_0_1: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", 
+        AFPOINTER1=> "011111101000001", AFPOINTER=> "011111101100001", 
+        AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111", 
+        RESETMODE=> "SYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        -- synopsys translate_on
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), 
+            DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), 
+            FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, 
+            EMPTYI=>Empty_int, CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn, 
+            RE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, 
+            RPRST=>RPReset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), 
+            DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), 
+            DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), 
+            DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), 
+            DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), 
+            DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), 
+            DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), 
+            DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), 
+            DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, AEF=>AlmostEmpty, 
+            AFF=>AlmostFull, FF=>Full_int);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    fifo52bit_synch_1_0: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111", 
+        AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111", 
+        AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111", 
+        RESETMODE=> "SYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        -- synopsys translate_on
+        port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), 
+            DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), 
+            DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), 
+            DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), 
+            DI14=>Data(50), DI15=>Data(51), DI16=>scuba_vlo, 
+            DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo, 
+            DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo, 
+            DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo, 
+            DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo, 
+            DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo, 
+            DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, 
+            DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>RdEn, 
+            CSR1=>scuba_vhi, WE=>WrEn, RE=>scuba_vhi, CLKW=>WrClock, 
+            CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>open, 
+            DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open, 
+            DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open, 
+            DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open, 
+            DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37), 
+            DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), 
+            DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), 
+            DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), 
+            DO32=>Q(50), DO33=>Q(51), DO34=>open, DO35=>open, EF=>open, 
+            AEF=>open, AFF=>open, FF=>open);
+
+    Empty <= Empty_int;
+    Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo52bit_synch is
+    for Structure
+        for all:VHI use entity SCM.VHI(V); end for;
+        for all:VLO use entity SCM.VLO(V); end for;
+        for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/fifo64bit_synch.vhd b/fifo64bit_synch.vhd
new file mode 100644 (file)
index 0000000..2ec099c
--- /dev/null
@@ -0,0 +1,226 @@
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module  Version: 5.4
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo64bit_synch -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 64 -rwidth 64 -regout -no_enable -pe 10 -pf 508 -sync_reset -e 
+
+-- Tue Feb 14 12:22:43 2012
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo64bit_synch is
+    port (
+        Data: in  std_logic_vector(63 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(63 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostEmpty: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo64bit_synch;
+
+architecture Structure of fifo64bit_synch is
+
+    -- internal signal declarations
+    signal Empty_int: std_logic;
+    signal Full_int: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component FIFO16KA
+    -- synopsys translate_off
+        generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); 
+                FULLPOINTER : in std_logic_vector(14 downto 0); 
+                AFPOINTER1 : in std_logic_vector(14 downto 0); 
+                AEPOINTER1 : in std_logic_vector(14 downto 0); 
+                AFPOINTER : in std_logic_vector(14 downto 0); 
+                AEPOINTER : in std_logic_vector(14 downto 0); 
+                CSDECODE_R : in std_logic_vector(1 downto 0); 
+                CSDECODE_W : in std_logic_vector(1 downto 0); 
+                RESETMODE : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+    -- synopsys translate_on
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            FULLI: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; EMPTYI: in  std_logic; 
+            CSR0: in  std_logic; CSR1: in  std_logic; WE: in  std_logic; 
+            RE: in  std_logic; CLKW: in  std_logic; CLKR: in  std_logic; 
+            RST: in  std_logic; RPRST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic; 
+            EF: out  std_logic; AEF: out  std_logic; AFF: out  std_logic; 
+            FF: out  std_logic);
+    end component;
+    attribute FULLPOINTER1 : string; 
+    attribute FULLPOINTER : string; 
+    attribute AFPOINTER1 : string; 
+    attribute AFPOINTER : string; 
+    attribute AEPOINTER1 : string; 
+    attribute AEPOINTER : string; 
+    attribute RESETMODE : string; 
+    attribute REGMODE : string; 
+    attribute CSDECODE_R : string; 
+    attribute CSDECODE_W : string; 
+    attribute DATA_WIDTH_R : string; 
+    attribute DATA_WIDTH_W : string; 
+    attribute FULLPOINTER1 of fifo64bit_synch_0_1 : label is "0b011111111000001";
+    attribute FULLPOINTER of fifo64bit_synch_0_1 : label is "0b011111111100001";
+    attribute AFPOINTER1 of fifo64bit_synch_0_1 : label is "0b011111101000001";
+    attribute AFPOINTER of fifo64bit_synch_0_1 : label is "0b011111101100001";
+    attribute AEPOINTER1 of fifo64bit_synch_0_1 : label is "0b000000101111111";
+    attribute AEPOINTER of fifo64bit_synch_0_1 : label is "0b000000101011111";
+    attribute RESETMODE of fifo64bit_synch_0_1 : label is "SYNC";
+    attribute REGMODE of fifo64bit_synch_0_1 : label is "OUTREG";
+    attribute CSDECODE_R of fifo64bit_synch_0_1 : label is "0b11";
+    attribute CSDECODE_W of fifo64bit_synch_0_1 : label is "0b11";
+    attribute DATA_WIDTH_R of fifo64bit_synch_0_1 : label is "36";
+    attribute DATA_WIDTH_W of fifo64bit_synch_0_1 : label is "36";
+    attribute FULLPOINTER1 of fifo64bit_synch_1_0 : label is "0b000000000000000";
+    attribute FULLPOINTER of fifo64bit_synch_1_0 : label is "0b111111111111111";
+    attribute AFPOINTER1 of fifo64bit_synch_1_0 : label is "0b000000000000000";
+    attribute AFPOINTER of fifo64bit_synch_1_0 : label is "0b111111111111111";
+    attribute AEPOINTER1 of fifo64bit_synch_1_0 : label is "0b000000000000000";
+    attribute AEPOINTER of fifo64bit_synch_1_0 : label is "0b111111111111111";
+    attribute RESETMODE of fifo64bit_synch_1_0 : label is "SYNC";
+    attribute REGMODE of fifo64bit_synch_1_0 : label is "OUTREG";
+    attribute CSDECODE_R of fifo64bit_synch_1_0 : label is "0b11";
+    attribute CSDECODE_W of fifo64bit_synch_1_0 : label is "0b11";
+    attribute DATA_WIDTH_R of fifo64bit_synch_1_0 : label is "36";
+    attribute DATA_WIDTH_W of fifo64bit_synch_1_0 : label is "36";
+    attribute syn_keep : boolean;
+
+begin
+    -- component instantiation statements
+    fifo64bit_synch_0_1: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", 
+        AFPOINTER1=> "011111101000001", AFPOINTER=> "011111101100001", 
+        AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111", 
+        RESETMODE=> "SYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        -- synopsys translate_on
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), 
+            DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), 
+            FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, 
+            EMPTYI=>Empty_int, CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn, 
+            RE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, 
+            RPRST=>RPReset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), 
+            DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), 
+            DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), 
+            DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), 
+            DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), 
+            DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), 
+            DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), 
+            DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), 
+            DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, AEF=>AlmostEmpty, 
+            AFF=>AlmostFull, FF=>Full_int);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    fifo64bit_synch_1_0: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111", 
+        AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111", 
+        AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111", 
+        RESETMODE=> "SYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        -- synopsys translate_on
+        port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), 
+            DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), 
+            DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), 
+            DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), 
+            DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), 
+            DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), 
+            DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), 
+            DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), 
+            DI26=>Data(62), DI27=>Data(63), DI28=>scuba_vlo, 
+            DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo, 
+            DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, 
+            DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>RdEn, 
+            CSR1=>scuba_vhi, WE=>WrEn, RE=>scuba_vhi, CLKW=>WrClock, 
+            CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>Q(54), 
+            DO1=>Q(55), DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), 
+            DO6=>Q(60), DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>open, 
+            DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open, 
+            DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37), 
+            DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), 
+            DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), 
+            DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), 
+            DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53), EF=>open, 
+            AEF=>open, AFF=>open, FF=>open);
+
+    Empty <= Empty_int;
+    Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo64bit_synch is
+    for Structure
+        for all:VHI use entity SCM.VHI(V); end for;
+        for all:VLO use entity SCM.VLO(V); end for;
+        for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on