Invert polarity ADC signals

diff --git a/ADC/sim/dummyADC.vhd b/ADC/sim/dummyADC.vhd
index b8f711d6b0aabec8425ba39b4565945c35aabc37..34225093bf9ac1f43444709110f13585fd98c22f 100644 (file)
--- a/ADC/sim/dummyADC.vhd
+++ b/ADC/sim/dummyADC.vhd
@@ -35,6 +35,7 @@ variable random1, random2, random3, random4         : unsigned(9 downto 0);
 variable l              : line;
 variable s              : std_logic_vector(47 downto 0);
 variable toggle         : std_logic := '0';
+variable t1, t2, t3, t4 : integer;
 variable s1, s2, s3, s4 : std_logic_vector(9 downto 0);
 variable cnt : unsigned(9 downto 0) := (others => '0');
  file stimulus: TEXT;   
@@ -54,13 +55,18 @@ begin
      UNIFORM(seed1, seed2, rand);
      random4 := to_unsigned(INTEGER(TRUNC(rand*randrange*2.0)),10); 
 
-     s1 := std_logic_vector(unsigned(s( 9 downto  0))+random1-to_unsigned(integer(randrange),10));
-     s2 := std_logic_vector(unsigned(s(21 downto 12))+random2-to_unsigned(integer(randrange),10));
-     s3 := std_logic_vector(unsigned(s(33 downto 24))+random3-to_unsigned(integer(randrange),10));
-     s4 := std_logic_vector(unsigned(s(45 downto 36))+random4-to_unsigned(integer(randrange),10));
+     t1 := 1024-to_integer(unsigned(s( 9 downto  0)));
+     t2 := 1024-to_integer(unsigned(s(21 downto 12)));
+     t3 := 1024-to_integer(unsigned(s(33 downto 24)));
+     t4 := 1024-to_integer(unsigned(s(45 downto 36)));
      
-     s1 := std_logic_vector(cnt);
-     cnt := cnt + 1;
+     s1 := std_logic_vector(to_unsigned(t1,10)+random1-to_unsigned(integer(randrange),10));
+     s2 := std_logic_vector(to_unsigned(t2,10)+random2-to_unsigned(integer(randrange),10));
+     s3 := std_logic_vector(to_unsigned(t3,10)+random3-to_unsigned(integer(randrange),10));
+     s4 := std_logic_vector(to_unsigned(t4,10)+random4-to_unsigned(integer(randrange),10));
+     
+     --s1 := std_logic_vector(cnt);
+     --cnt := cnt + 1;
      
      DATA <= s4 & s3 & s2 & s1;
      VALID <= '1';
@@ -78,4 +84,4 @@ begin
    file_close(stimulus);
 
  end process receive_data;
-end architecture;
\ No newline at end of file
+end architecture;