execute($c);
system("rm $TOPNAME.ncd");
-
+system("rm $TOPNAME.dir/*");
$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|;
execute($c);
+system("cp -a ${TOPNAME}.dir/*.ncd ./${TOPNAME}.ncd");
+
# IOR IO Timing Report
$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
execute($c);
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="adc_ddr_generic" module="DDR_GENERIC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 02 04 14:33:12.396" version="5.4" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="adc_ddr_generic" module="DDR_GENERIC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 01 16:42:36.655" version="5.3" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="adc_ddr_generic.lpc" type="lpc" modified="2014 02 04 14:33:08.000"/>
- <File name="adc_ddr_generic.vhd" type="top_level_vhdl" modified="2014 02 04 14:33:08.000"/>
- <File name="adc_ddr_generic_tmpl.vhd" type="template_vhdl" modified="2014 02 04 14:33:08.000"/>
+ <File name="adc_ddr_generic.lpc" type="lpc" modified="2014 05 01 16:42:34.000"/>
+ <File name="adc_ddr_generic.vhd" type="top_level_vhdl" modified="2014 05 01 16:42:34.000"/>
+ <File name="adc_ddr_generic_tmpl.vhd" type="template_vhdl" modified="2014 05 01 16:42:34.000"/>
</Package>
</DiamondModule>
CoreType=LPM
CoreStatus=Demo
CoreName=DDR_GENERIC
-CoreRevision=5.4
+CoreRevision=5.3
ModuleName=adc_ddr_generic
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=02/04/2014
-Time=14:33:08
+Date=05/01/2014
+Time=16:42:34
[Parameters]
Verilog=0
--- VHDL netlist generated by SCUBA Diamond_3.0_Production (94)
--- Module Version: 5.4
---/usr/local/opt/lattice_diamond/diamond/3.0/ispfpga/bin/lin64/scuba -w -n adc_ddr_generic -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 187.5 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module Version: 5.3
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n adc_ddr_generic -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 187.5 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e
--- Tue Feb 4 14:33:08 2014
+-- Thu May 1 16:42:34 2014
library IEEE;
use IEEE.std_logic_1164.all;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="dynamic_shift_register8x64" module="RAM_Based_Shift_Register" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 18 13:07:37.726" version="4.1" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="" type="mem" modified="2014 04 18 13:07:37.000"/>
+ <File name="dynamic_shift_register8x64.lpc" type="lpc" modified="2014 04 18 13:07:29.000"/>
+ <File name="dynamic_shift_register8x64.vhd" type="top_level_vhdl" modified="2014 04 18 13:07:29.000"/>
+ <File name="dynamic_shift_register8x64_tmpl.vhd" type="template_vhdl" modified="2014 04 18 13:07:29.000"/>
+ <File name="tb_dynamic_shift_register8x64_tmpl.vhd" type="testbench_vhdl" modified="2014 04 18 13:07:29.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_Based_Shift_Register
+CoreRevision=4.1
+ModuleName=dynamic_shift_register8x64
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/18/2014
+Time=13:07:29
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+DataWidth=8
+Type=VarLossless
+NoOfShifts=16
+MaxLossyShifts=16
+MaxLosslessShifts=64
+EOR=1
+MemFile=
+MemFormat=orca
+RamType=dram
+
+[FilesGenerated]
+=mem
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module Version: 4.1
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n dynamic_shift_register8x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type shiftreg -width 8 -depth 64 -mode 2 -pipe_final_output -e
+
+-- Fri Apr 18 13:07:29 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity dynamic_shift_register8x64 is
+ port (
+ Din: in std_logic_vector(7 downto 0);
+ Addr: in std_logic_vector(5 downto 0);
+ Clock: in std_logic;
+ ClockEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(7 downto 0));
+end dynamic_shift_register8x64;
+
+architecture Structure of dynamic_shift_register8x64 is
+
+ -- internal signal declarations
+ signal shreg_addr_w5_inv: std_logic;
+ signal shreg_addr_w4_inv: std_logic;
+ signal Reset_inv: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ishreg_addr_w0: std_logic;
+ signal ishreg_addr_w1: std_logic;
+ signal sreg_0_ctr_1_ci: std_logic;
+ signal ishreg_addr_w2: std_logic;
+ signal ishreg_addr_w3: std_logic;
+ signal co0: std_logic;
+ signal ishreg_addr_w4: std_logic;
+ signal ishreg_addr_w5: std_logic;
+ signal co2: std_logic;
+ signal co1: std_logic;
+ signal low_inv: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal shreg_addr_w4: std_logic;
+ signal co2_1: std_logic;
+ signal shreg_addr_w5: std_logic;
+ signal scuba_vlo: std_logic;
+ signal Q7_ffin: std_logic;
+ signal Q6_ffin: std_logic;
+ signal Q5_ffin: std_logic;
+ signal Q4_ffin: std_logic;
+ signal Q3_ffin: std_logic;
+ signal Q2_ffin: std_logic;
+ signal Q1_ffin: std_logic;
+ signal Q0_ffin: std_logic;
+ signal shreg_addr_r5: std_logic;
+ signal shreg_addr_r4: std_logic;
+ signal mdL0_0_7: std_logic;
+ signal mdL0_0_6: std_logic;
+ signal mdL0_0_5: std_logic;
+ signal mdL0_0_4: std_logic;
+ signal mdL0_0_3: std_logic;
+ signal mdL0_0_2: std_logic;
+ signal mdL0_0_1: std_logic;
+ signal mdL0_0_0: std_logic;
+ signal dec0_wre3: std_logic;
+ signal mdL0_1_7: std_logic;
+ signal mdL0_1_6: std_logic;
+ signal mdL0_1_5: std_logic;
+ signal mdL0_1_4: std_logic;
+ signal mdL0_1_3: std_logic;
+ signal mdL0_1_2: std_logic;
+ signal mdL0_1_1: std_logic;
+ signal mdL0_1_0: std_logic;
+ signal dec1_wre7: std_logic;
+ signal mdL0_2_7: std_logic;
+ signal mdL0_2_6: std_logic;
+ signal mdL0_2_5: std_logic;
+ signal mdL0_2_4: std_logic;
+ signal mdL0_2_3: std_logic;
+ signal mdL0_2_2: std_logic;
+ signal mdL0_2_1: std_logic;
+ signal mdL0_2_0: std_logic;
+ signal dec2_wre11: std_logic;
+ signal mdL0_3_7: std_logic;
+ signal mdL0_3_6: std_logic;
+ signal mdL0_3_5: std_logic;
+ signal mdL0_3_4: std_logic;
+ signal mdL0_3_3: std_logic;
+ signal mdL0_3_2: std_logic;
+ signal mdL0_3_1: std_logic;
+ signal mdL0_3_0: std_logic;
+ signal shreg_addr_r3: std_logic;
+ signal shreg_addr_r2: std_logic;
+ signal shreg_addr_r1: std_logic;
+ signal shreg_addr_r0: std_logic;
+ signal dec3_wre15: std_logic;
+ signal shreg_addr_w3: std_logic;
+ signal shreg_addr_w2: std_logic;
+ signal shreg_addr_w1: std_logic;
+ signal shreg_addr_w0: std_logic;
+
+ -- local component declarations
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component MUX41
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
+ Z: out std_logic);
+ end component;
+ component ROM16X1A
+ generic (INITVAL : in std_logic_vector(15 downto 0));
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component DPR16X4C
+ generic (INITVAL : in String);
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; WCK: in std_logic; WRE: in std_logic;
+ RAD0: in std_logic; RAD1: in std_logic;
+ RAD2: in std_logic; RAD3: in std_logic;
+ WAD0: in std_logic; WAD1: in std_logic;
+ WAD2: in std_logic; WAD3: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute GSR : string;
+ attribute MEM_INIT_FILE : string;
+ attribute MEM_LPC_FILE : string;
+ attribute COMP : string;
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute MEM_INIT_FILE of sram_1_0_0 : label is "(0-15)(0-3)";
+ attribute MEM_LPC_FILE of sram_1_0_0 : label is "dynamic_shift_register8x64.lpc";
+ attribute COMP of sram_1_0_0 : label is "sram_1_0_0";
+ attribute MEM_INIT_FILE of sram_1_0_1 : label is "(0-15)(4-7)";
+ attribute MEM_LPC_FILE of sram_1_0_1 : label is "dynamic_shift_register8x64.lpc";
+ attribute COMP of sram_1_0_1 : label is "sram_1_0_1";
+ attribute MEM_INIT_FILE of sram_1_1_0 : label is "(16-31)(0-3)";
+ attribute MEM_LPC_FILE of sram_1_1_0 : label is "dynamic_shift_register8x64.lpc";
+ attribute COMP of sram_1_1_0 : label is "sram_1_1_0";
+ attribute MEM_INIT_FILE of sram_1_1_1 : label is "(16-31)(4-7)";
+ attribute MEM_LPC_FILE of sram_1_1_1 : label is "dynamic_shift_register8x64.lpc";
+ attribute COMP of sram_1_1_1 : label is "sram_1_1_1";
+ attribute MEM_INIT_FILE of sram_1_2_0 : label is "(32-47)(0-3)";
+ attribute MEM_LPC_FILE of sram_1_2_0 : label is "dynamic_shift_register8x64.lpc";
+ attribute COMP of sram_1_2_0 : label is "sram_1_2_0";
+ attribute MEM_INIT_FILE of sram_1_2_1 : label is "(32-47)(4-7)";
+ attribute MEM_LPC_FILE of sram_1_2_1 : label is "dynamic_shift_register8x64.lpc";
+ attribute COMP of sram_1_2_1 : label is "sram_1_2_1";
+ attribute MEM_INIT_FILE of sram_1_3_0 : label is "(48-63)(0-3)";
+ attribute MEM_LPC_FILE of sram_1_3_0 : label is "dynamic_shift_register8x64.lpc";
+ attribute COMP of sram_1_3_0 : label is "sram_1_3_0";
+ attribute MEM_INIT_FILE of sram_1_3_1 : label is "(48-63)(4-7)";
+ attribute MEM_LPC_FILE of sram_1_3_1 : label is "dynamic_shift_register8x64.lpc";
+ attribute COMP of sram_1_3_1 : label is "sram_1_3_1";
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ INV_3: INV
+ port map (A=>Reset, Z=>Reset_inv);
+
+ INV_2: INV
+ port map (A=>scuba_vlo, Z=>low_inv);
+
+ INV_1: INV
+ port map (A=>shreg_addr_w4, Z=>shreg_addr_w4_inv);
+
+ INV_0: INV
+ port map (A=>shreg_addr_w5, Z=>shreg_addr_w5_inv);
+
+ LUT4_3: ROM16X1A
+ generic map (initval=> X"8000")
+ port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv,
+ AD0=>shreg_addr_w5_inv, DO0=>dec0_wre3);
+
+ LUT4_2: ROM16X1A
+ generic map (initval=> X"8000")
+ port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4,
+ AD0=>shreg_addr_w5_inv, DO0=>dec1_wre7);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"8000")
+ port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv,
+ AD0=>shreg_addr_w5, DO0=>dec2_wre11);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"8000")
+ port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4,
+ AD0=>shreg_addr_w5, DO0=>dec3_wre15);
+
+ FF_13: FD1P3DX
+ port map (D=>ishreg_addr_w0, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>shreg_addr_w0);
+
+ FF_12: FD1P3DX
+ port map (D=>ishreg_addr_w1, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>shreg_addr_w1);
+
+ FF_11: FD1P3DX
+ port map (D=>ishreg_addr_w2, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>shreg_addr_w2);
+
+ FF_10: FD1P3DX
+ port map (D=>ishreg_addr_w3, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>shreg_addr_w3);
+
+ FF_9: FD1P3DX
+ port map (D=>ishreg_addr_w4, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>shreg_addr_w4);
+
+ FF_8: FD1P3DX
+ port map (D=>ishreg_addr_w5, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>shreg_addr_w5);
+
+ FF_7: FD1P3DX
+ port map (D=>Q7_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(7));
+
+ FF_6: FD1P3DX
+ port map (D=>Q6_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(6));
+
+ FF_5: FD1P3DX
+ port map (D=>Q5_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(5));
+
+ FF_4: FD1P3DX
+ port map (D=>Q4_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(4));
+
+ FF_3: FD1P3DX
+ port map (D=>Q3_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(3));
+
+ FF_2: FD1P3DX
+ port map (D=>Q2_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(2));
+
+ FF_1: FD1P3DX
+ port map (D=>Q1_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(1));
+
+ FF_0: FD1P3DX
+ port map (D=>Q0_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(0));
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ sreg_0_ctr_1_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>sreg_0_ctr_1_ci,
+ S0=>open, S1=>open);
+
+ sreg_0_ctr_1_0: CU2
+ port map (CI=>sreg_0_ctr_1_ci, PC0=>shreg_addr_w0,
+ PC1=>shreg_addr_w1, CO=>co0, NC0=>ishreg_addr_w0,
+ NC1=>ishreg_addr_w1);
+
+ sreg_0_ctr_1_1: CU2
+ port map (CI=>co0, PC0=>shreg_addr_w2, PC1=>shreg_addr_w3,
+ CO=>co1, NC0=>ishreg_addr_w2, NC1=>ishreg_addr_w3);
+
+ sreg_0_ctr_1_2: CU2
+ port map (CI=>co1, PC0=>shreg_addr_w4, PC1=>shreg_addr_w5,
+ CO=>co2, NC0=>ishreg_addr_w4, NC1=>ishreg_addr_w5);
+
+ raddr_sub_1_0: FSUB2B
+ port map (A0=>scuba_vlo, A1=>shreg_addr_w0, B0=>low_inv,
+ B1=>Addr(0), BI=>scuba_vlo, BOUT=>co0_1, S0=>open,
+ S1=>shreg_addr_r0);
+
+ raddr_sub_1_1: FSUB2B
+ port map (A0=>shreg_addr_w1, A1=>shreg_addr_w2, B0=>Addr(1),
+ B1=>Addr(2), BI=>co0_1, BOUT=>co1_1, S0=>shreg_addr_r1,
+ S1=>shreg_addr_r2);
+
+ raddr_sub_1_2: FSUB2B
+ port map (A0=>shreg_addr_w3, A1=>shreg_addr_w4, B0=>Addr(3),
+ B1=>Addr(4), BI=>co1_1, BOUT=>co2_1, S0=>shreg_addr_r3,
+ S1=>shreg_addr_r4);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ raddr_sub_1_3: FSUB2B
+ port map (A0=>shreg_addr_w5, A1=>scuba_vlo, B0=>Addr(5),
+ B1=>scuba_vlo, BI=>co2_1, BOUT=>open, S0=>shreg_addr_r5,
+ S1=>open);
+
+ mux_7: MUX41
+ port map (D0=>mdL0_0_7, D1=>mdL0_1_7, D2=>mdL0_2_7, D3=>mdL0_3_7,
+ SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q7_ffin);
+
+ mux_6: MUX41
+ port map (D0=>mdL0_0_6, D1=>mdL0_1_6, D2=>mdL0_2_6, D3=>mdL0_3_6,
+ SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q6_ffin);
+
+ mux_5: MUX41
+ port map (D0=>mdL0_0_5, D1=>mdL0_1_5, D2=>mdL0_2_5, D3=>mdL0_3_5,
+ SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q5_ffin);
+
+ mux_4: MUX41
+ port map (D0=>mdL0_0_4, D1=>mdL0_1_4, D2=>mdL0_2_4, D3=>mdL0_3_4,
+ SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q4_ffin);
+
+ mux_3: MUX41
+ port map (D0=>mdL0_0_3, D1=>mdL0_1_3, D2=>mdL0_2_3, D3=>mdL0_3_3,
+ SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q3_ffin);
+
+ mux_2: MUX41
+ port map (D0=>mdL0_0_2, D1=>mdL0_1_2, D2=>mdL0_2_2, D3=>mdL0_3_2,
+ SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q2_ffin);
+
+ mux_1: MUX41
+ port map (D0=>mdL0_0_1, D1=>mdL0_1_1, D2=>mdL0_2_1, D3=>mdL0_3_1,
+ SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q1_ffin);
+
+ mux_0: MUX41
+ port map (D0=>mdL0_0_0, D1=>mdL0_1_0, D2=>mdL0_2_0, D3=>mdL0_3_0,
+ SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q0_ffin);
+
+ sram_1_0_0: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7),
+ WCK=>Clock, WRE=>dec0_wre3, RAD0=>shreg_addr_r0,
+ RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2,
+ RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0,
+ WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2,
+ WAD3=>shreg_addr_w3, DO0=>mdL0_0_4, DO1=>mdL0_0_5,
+ DO2=>mdL0_0_6, DO3=>mdL0_0_7);
+
+ sram_1_0_1: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3),
+ WCK=>Clock, WRE=>dec0_wre3, RAD0=>shreg_addr_r0,
+ RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2,
+ RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0,
+ WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2,
+ WAD3=>shreg_addr_w3, DO0=>mdL0_0_0, DO1=>mdL0_0_1,
+ DO2=>mdL0_0_2, DO3=>mdL0_0_3);
+
+ sram_1_1_0: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7),
+ WCK=>Clock, WRE=>dec1_wre7, RAD0=>shreg_addr_r0,
+ RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2,
+ RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0,
+ WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2,
+ WAD3=>shreg_addr_w3, DO0=>mdL0_1_4, DO1=>mdL0_1_5,
+ DO2=>mdL0_1_6, DO3=>mdL0_1_7);
+
+ sram_1_1_1: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3),
+ WCK=>Clock, WRE=>dec1_wre7, RAD0=>shreg_addr_r0,
+ RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2,
+ RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0,
+ WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2,
+ WAD3=>shreg_addr_w3, DO0=>mdL0_1_0, DO1=>mdL0_1_1,
+ DO2=>mdL0_1_2, DO3=>mdL0_1_3);
+
+ sram_1_2_0: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7),
+ WCK=>Clock, WRE=>dec2_wre11, RAD0=>shreg_addr_r0,
+ RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2,
+ RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0,
+ WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2,
+ WAD3=>shreg_addr_w3, DO0=>mdL0_2_4, DO1=>mdL0_2_5,
+ DO2=>mdL0_2_6, DO3=>mdL0_2_7);
+
+ sram_1_2_1: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3),
+ WCK=>Clock, WRE=>dec2_wre11, RAD0=>shreg_addr_r0,
+ RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2,
+ RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0,
+ WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2,
+ WAD3=>shreg_addr_w3, DO0=>mdL0_2_0, DO1=>mdL0_2_1,
+ DO2=>mdL0_2_2, DO3=>mdL0_2_3);
+
+ sram_1_3_0: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7),
+ WCK=>Clock, WRE=>dec3_wre15, RAD0=>shreg_addr_r0,
+ RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2,
+ RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0,
+ WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2,
+ WAD3=>shreg_addr_w3, DO0=>mdL0_3_4, DO1=>mdL0_3_5,
+ DO2=>mdL0_3_6, DO3=>mdL0_3_7);
+
+ sram_1_3_1: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3),
+ WCK=>Clock, WRE=>dec3_wre15, RAD0=>shreg_addr_r0,
+ RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2,
+ RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0,
+ WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2,
+ WAD3=>shreg_addr_w3, DO0=>mdL0_3_0, DO1=>mdL0_3_1,
+ DO2=>mdL0_3_2, DO3=>mdL0_3_3);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of dynamic_shift_register8x64 is
+ for Structure
+ for all:CU2 use entity ecp3.CU2(V); end for;
+ for all:FADD2B use entity ecp3.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
+ for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+ for all:INV use entity ecp3.INV(V); end for;
+ for all:MUX41 use entity ecp3.MUX41(V); end for;
+ for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+ for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="fifo_data_stream_44to44_dc" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 15 22:11:19.583" version="5.4" type="Module" synthesis="" source_format="VHDL">
+ <Package>
+ <File name="fifo_data_stream_44to44_dc.lpc" type="lpc" modified="2014 04 15 22:11:13.000"/>
+ <File name="fifo_data_stream_44to44_dc.vhd" type="top_level_vhdl" modified="2014 04 15 22:11:13.000"/>
+ <File name="fifo_data_stream_44to44_dc_tmpl.vhd" type="template_vhdl" modified="2014 04 15 22:11:13.000"/>
+ <File name="tb_fifo_data_stream_44to44_dc_tmpl.vhd" type="testbench_vhdl" modified="2014 04 15 22:11:13.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.4
+ModuleName=fifo_data_stream_44to44_dc
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/15/2014
+Time=22:11:13
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=4
+Width=44
+RDepth=4
+RWidth=44
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module Version: 5.4
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 44 -depth 4 -rdata_width 44 -regout -no_enable -pe -1 -pf -1 -e
+
+-- Tue Apr 15 22:11:13 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity fifo_data_stream_44to44_dc is
+ port (
+ Data: in std_logic_vector(43 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(43 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_data_stream_44to44_dc;
+
+architecture Structure of fifo_data_stream_44to44_dc is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal co1: std_logic;
+ signal wcount_2: std_logic;
+ signal co0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal co1_1: std_logic;
+ signal rcount_2: std_logic;
+ signal co0_1: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r0: std_logic;
+ signal wcount_r1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1A
+ generic (INITVAL : in std_logic_vector(15 downto 0));
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component PDPW16KC
+ generic (GSR : in String; CSDECODE_R : in String;
+ CSDECODE_W : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_data_stream_44to44_dc.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_data_stream_44to44_dc.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+ attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t6: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t5: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t4: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t3: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t2: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ LUT4_7: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r1);
+
+ LUT4_6: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0);
+
+ LUT4_5: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w1);
+
+ LUT4_4: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0);
+
+ LUT4_3: ROM16X1A
+ generic map (initval=> X"0410")
+ port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1A
+ generic map (initval=> X"1004")
+ port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"0140")
+ port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"4001")
+ port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ pdp_ram_0_0_1: PDPW16KC
+ generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
+ ADW1=>wptr_1, ADW2=>scuba_vlo, ADW3=>scuba_vlo,
+ ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo,
+ ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi,
+ BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i,
+ CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
+ ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo,
+ ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo,
+ ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi,
+ CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
+ DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
+ DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
+ DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33),
+ DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
+ DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
+ DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
+ DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
+ DO34=>Q(16), DO35=>Q(17));
+
+ pdp_ram_0_1_0: PDPW16KC
+ generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
+ DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
+ DI7=>Data(43), DI8=>scuba_vlo, DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1,
+ ADW2=>scuba_vlo, ADW3=>scuba_vlo, ADW4=>scuba_vlo,
+ ADW5=>scuba_vlo, ADW6=>scuba_vlo, ADW7=>scuba_vlo,
+ ADW8=>scuba_vlo, BE0=>scuba_vhi, BE1=>scuba_vhi,
+ BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock,
+ CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
+ ADR7=>scuba_vlo, ADR8=>scuba_vlo, ADR9=>scuba_vlo,
+ ADR10=>scuba_vlo, ADR11=>scuba_vlo, ADR12=>scuba_vlo,
+ ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>RdClock,
+ CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset,
+ DO0=>open, DO1=>open, DO2=>open, DO3=>open, DO4=>open,
+ DO5=>open, DO6=>open, DO7=>open, DO8=>open, DO9=>open,
+ DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open,
+ DO15=>open, DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37),
+ DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
+ DO24=>Q(42), DO25=>Q(43), DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ FF_31: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_30: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_29: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_28: FD1P3DX
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_27: FD1P3DX
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_26: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_25: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_24: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_23: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_22: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_21: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_20: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_19: FD1P3DX
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_18: FD1P3DX
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_17: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_16: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_15: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_14: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_13: FD1S3DX
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_12: FD1S3DX
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_11: FD1S3DX
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_10: FD1S3DX
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_9: FD1S3DX
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_8: FD1S3DX
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_7: FD1S3DX
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_6: FD1S3DX
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_5: FD1S3DX
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_4: FD1S3DX
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_3: FD1S3DX
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_2: FD1S3DX
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_1: FD1S3BX
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1,
+ NC0=>iwcount_2, NC1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1,
+ NC0=>ircount_2, NC1=>open);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
+ B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
+ B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
+ B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+
+ full_cmp_1: AGEB2
+ port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
+ B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of fifo_data_stream_44to44_dc is
+ for Structure
+ for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+ for all:AND2 use entity ecp3.AND2(V); end for;
+ for all:CU2 use entity ecp3.CU2(V); end for;
+ for all:FADD2B use entity ecp3.FADD2B(V); end for;
+ for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+ for all:INV use entity ecp3.INV(V); end for;
+ for all:OR2 use entity ecp3.OR2(V); end for;
+ for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:XOR2 use entity ecp3.XOR2(V); end for;
+ for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[c1]
+system = linux
+corenum = 4
+env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[c2]
+system = linux
+corenum = 4
+env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[c3]
+system = linux
+corenum = 4
+env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[c4]
+system = linux
+corenum = 4
+env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[c5]
+system = linux
+corenum = 4
+env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[c6]
+system = linux
+corenum = 4
+env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[c7]
+system = linux
+corenum = 4
+env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
use work.nxyter_components.all;
entity adc_ad9228 is
+ generic (
+ DEBUG_ENABLE : boolean := false
+ );
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
ADC0_DATA_B_OUT : out std_logic_vector(11 downto 0);
ADC0_DATA_C_OUT : out std_logic_vector(11 downto 0);
ADC0_DATA_D_OUT : out std_logic_vector(11 downto 0);
- ADC0_DATA_VALID_OUT : out std_logic;
+ ADC0_DATA_CLK_OUT : out std_logic;
ADC1_DATA_A_OUT : out std_logic_vector(11 downto 0);
ADC1_DATA_B_OUT : out std_logic_vector(11 downto 0);
ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0);
ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0);
- ADC1_DATA_VALID_OUT : out std_logic;
- ADC0_NOTLOCK_COUNTER : out unsigned(7 downto 0);
- ADC1_NOTLOCK_COUNTER : out unsigned(7 downto 0);
+ ADC1_DATA_CLK_OUT : out std_logic;
+ ADC0_LOCKED_OUT : out std_logic;
+ ADC1_LOCKED_OUT : out std_logic;
ERROR_ADC0_OUT : out std_logic;
ERROR_ADC1_OUT : out std_logic;
end adc_ad9228;
architecture Behavioral of adc_ad9228 is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "SAMPLING_ADC_AD9228";
-
+
-- DDR Generic Handler
signal DDR_DATA_CLK : std_logic;
signal q_0_ff : std_logic_vector(19 downto 0);
signal q_1_f : std_logic_vector(19 downto 0);
signal q_1 : std_logic_vector(19 downto 0);
- -- NotLock Counters
- signal adc0_frame_notlocked : std_logic;
- signal adc0_frame_notlocked_p : std_logic;
- signal adc0_notlock_ctr : unsigned(7 downto 0);
-
- signal adc1_frame_notlocked : std_logic;
- signal adc1_frame_notlocked_p : std_logic;
- signal adc1_notlock_ctr : unsigned(7 downto 0);
-
-- Merge Data
- type q_map_t is array(0 to 4) of std_logic_vector(3 downto 0);
- type adc_data_buf_t is array(0 to 4) of std_logic_vector(15 downto 0);
+ type adc_data_s is array(0 to 4) of std_logic_vector(13 downto 0);
type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0);
- signal adc0_data_buf : adc_data_buf_t;
- signal adc0_frame_ctr : unsigned(2 downto 0);
- signal adc0_frame_ctr_last : unsigned(2 downto 0);
- signal adc0_bit_shift : unsigned(1 downto 0);
- signal adc0_bit_shift_last : unsigned(1 downto 0);
- signal adc0_ctr_error : std_logic;
- signal adc0_shift_error : std_logic;
- signal adc0_error_status : std_logic_vector(15 downto 0);
+ type BYTE_STATUS is (B_UNDEF,
+ B_ALIGNED,
+ B_SHIFTED
+ );
+ -- ADC0
+ signal adc0_data_shift : adc_data_s;
+
+ signal adc0_data_m : adc_data_t;
+ signal adc0_data_clk_m : std_logic;
+
+ signal adc0_byte_status : BYTE_STATUS;
+ signal adc0_byte_status_last : BYTE_STATUS;
+
+ signal adc0_frame_clk_ok : std_logic;
+ signal adc0_frame_clk_ok_hist : std_logic_vector(15 downto 0);
signal adc0_frame_locked : std_logic;
+ signal adc0_error : std_logic;
+
+ -- ADC0
+ signal adc1_data_shift : adc_data_s;
- signal adc0_new_data_t : std_logic;
- signal adc0_data_t : adc_data_t;
-
- signal adc1_data_buf : adc_data_buf_t;
- signal adc1_frame_ctr : unsigned(2 downto 0);
- signal adc1_frame_ctr_last : unsigned(2 downto 0);
- signal adc1_bit_shift : unsigned(1 downto 0);
- signal adc1_bit_shift_last : unsigned(1 downto 0);
- signal adc1_ctr_error : std_logic;
- signal adc1_shift_error : std_logic;
- signal adc1_error_status : std_logic_vector(15 downto 0);
+ signal adc1_data_m : adc_data_t;
+ signal adc1_data_clk_m : std_logic;
+
+ signal adc1_byte_status : BYTE_STATUS;
+ signal adc1_byte_status_last : BYTE_STATUS;
+
+ signal adc1_frame_clk_ok : std_logic;
+ signal adc1_frame_clk_ok_hist : std_logic_vector(15 downto 0);
signal adc1_frame_locked : std_logic;
-
- signal adc1_new_data_t : std_logic;
- signal adc1_data_t : adc_data_t;
-
+ signal adc1_error : std_logic;
+
-- Clock Transfer
signal adc0_fifo_empty : std_logic;
signal adc0_fifo_full : std_logic;
signal adc0_read_enable : std_logic;
signal adc0_read_enable_t : std_logic;
signal adc0_read_enable_tt : std_logic;
- signal adc0_fifo_reset : std_logic;
+ signal adc0_locked_ff : std_logic;
+ signal adc0_locked_f : std_logic;
+ signal adc0_locked_o : std_logic;
signal adc1_fifo_empty : std_logic;
signal adc1_fifo_full : std_logic;
signal adc1_read_enable : std_logic;
signal adc1_read_enable_t : std_logic;
signal adc1_read_enable_tt : std_logic;
- signal adc1_fifo_reset : std_logic;
-
+ signal adc1_locked_ff : std_logic;
+ signal adc1_locked_f : std_logic;
+ signal adc1_locked_o : std_logic;
+
-- Error
signal error_adc0_o : std_logic;
signal error_adc1_o : std_logic;
-- Output
- signal adc0_data_valid_o : std_logic;
+ signal adc0_data_clk_o : std_logic;
signal adc0_data_f : adc_data_t;
signal adc0_data_o : adc_data_t;
- signal adc1_data_valid_o : std_logic;
+ signal adc1_data_clk_o : std_logic;
signal adc1_data_f : adc_data_t;
signal adc1_data_o : adc_data_t;
-
- -- Resets
- signal RESET_CLK_ADCDAT_IN : std_logic;
- signal RESET_DDR_DATA_CLK : std_logic;
-
+ -- RESET Handler
+ type R_STATES is (R_IDLE,
+ R_WAIT_CLKDIV,
+ R_WAIT_RESET_ADC,
+ R_WAIT_RESET_END
+ );
+ signal R_STATE : R_STATES;
+
+ signal startup_reset : std_logic;
+ signal timer_reset : std_logic;
+ signal wait_timer_start : std_logic;
+ signal wait_timer_done : std_logic;
+ signal RESET_CLKDIV : std_logic;
+ signal RESET_ADC0 : std_logic;
+ signal RESET_ADC1 : std_logic;
+
+ signal RESET_ADC0_CLKD_F : std_logic;
+ signal RESET_ADC0_CLKD : std_logic;
+ signal RESET_ADC1_CLKD_F : std_logic;
+ signal RESET_ADC1_CLKD : std_logic;
+
--
attribute syn_keep : boolean;
- attribute syn_keep of q_0_ff : signal is true;
- attribute syn_keep of q_0_f : signal is true;
- attribute syn_keep of q_1_ff : signal is true;
- attribute syn_keep of q_1_f : signal is true;
+ attribute syn_keep of q_0_ff : signal is true;
+ attribute syn_keep of q_0_f : signal is true;
+ attribute syn_keep of q_1_ff : signal is true;
+ attribute syn_keep of q_1_f : signal is true;
+
+ attribute syn_keep of adc0_locked_ff : signal is true;
+ attribute syn_keep of adc0_locked_f : signal is true;
+ attribute syn_keep of adc1_locked_ff : signal is true;
+ attribute syn_keep of adc1_locked_f : signal is true;
+
+ attribute syn_keep of RESET_ADC0_CLKD_F : signal is true;
+ attribute syn_keep of RESET_ADC0_CLKD : signal is true;
+ attribute syn_keep of RESET_ADC1_CLKD_F : signal is true;
+ attribute syn_keep of RESET_ADC1_CLKD : signal is true;
attribute syn_preserve : boolean;
- attribute syn_preserve of q_0_ff : signal is true;
- attribute syn_preserve of q_0_f : signal is true;
- attribute syn_preserve of q_1_ff : signal is true;
- attribute syn_preserve of q_1_f : signal is true;
-
+ attribute syn_preserve of q_0_ff : signal is true;
+ attribute syn_preserve of q_0_f : signal is true;
+ attribute syn_preserve of q_1_ff : signal is true;
+ attribute syn_preserve of q_1_f : signal is true;
-begin
+ attribute syn_preserve of adc0_locked_ff : signal is true;
+ attribute syn_preserve of adc0_locked_f : signal is true;
+ attribute syn_preserve of adc1_locked_ff : signal is true;
+ attribute syn_preserve of adc1_locked_f : signal is true;
- PROC_DEBUG: process (DEBUG_IN)
- begin
- case DEBUG_IN is
- when x"0" =>
- -- DEBUG
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= DDR_DATA_CLK;
- DEBUG_OUT(2) <= adc0_write_enable;
- DEBUG_OUT(3) <= adc0_fifo_full;
- DEBUG_OUT(4) <= adc0_fifo_empty;
- DEBUG_OUT(5) <= adc0_new_data_t;
- DEBUG_OUT(6) <= adc0_read_enable;
- DEBUG_OUT(7) <= adc0_read_enable_t;
- DEBUG_OUT(8) <= adc0_read_enable_tt;
- DEBUG_OUT(9) <= adc0_data_valid_o;
- DEBUG_OUT(10) <= adc0_ctr_error;
- DEBUG_OUT(11) <= adc0_shift_error;
- DEBUG_OUT(12) <= adc0_frame_locked;
- DEBUG_OUT(13) <= adc0_frame_notlocked;
- DEBUG_OUT(14) <= adc0_frame_notlocked_p;
- DEBUG_OUT(15) <= error_adc0_o;
-
- when x"1" =>
- DEBUG_OUT <= adc0_data_buf(0);
-
- when x"2" =>
- DEBUG_OUT <= adc0_data_buf(1);
-
- when x"3" =>
- DEBUG_OUT <= adc0_data_buf(2);
-
- when x"4" =>
- DEBUG_OUT <= adc0_data_buf(3);
-
- when x"5" =>
- DEBUG_OUT <= adc0_data_buf(4);
-
- when others =>
- DEBUG_OUT <= (others => '0');
-
- end case;
- end process PROC_DEBUG;
+ attribute syn_preserve of RESET_ADC0_CLKD_F : signal is true;
+ attribute syn_preserve of RESET_ADC0_CLKD : signal is true;
+ attribute syn_preserve of RESET_ADC1_CLKD_F : signal is true;
+ attribute syn_preserve of RESET_ADC1_CLKD : signal is true;
+
+begin
-----------------------------------------------------------------------------
- -- Reset Domain Transfer
+ -- Debug Handler
-----------------------------------------------------------------------------
- signal_async_trans_RESET_IN: signal_async_trans
- port map (
- CLK_IN => CLK_ADCDAT_IN,
- SIGNAL_A_IN => RESET_IN,
- SIGNAL_OUT => RESET_CLK_ADCDAT_IN
- );
- signal_async_trans_RESET_IN_2: signal_async_trans
- port map (
- CLK_IN => DDR_DATA_CLK,
- SIGNAL_A_IN => RESET_IN,
- SIGNAL_OUT => RESET_DDR_DATA_CLK
- );
+ DFALSE: if (DEBUG_ENABLE = false) generate
+
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= DDR_DATA_CLK;
+ DEBUG_OUT(2) <= adc0_write_enable;
+ DEBUG_OUT(3) <= adc0_fifo_full;
+ DEBUG_OUT(4) <= adc0_fifo_empty;
+ DEBUG_OUT(5) <= adc0_data_clk_m;
+ DEBUG_OUT(6) <= adc0_read_enable;
+ DEBUG_OUT(7) <= adc0_read_enable_t;
+ DEBUG_OUT(8) <= adc0_read_enable_tt;
+ DEBUG_OUT(9) <= adc0_data_clk_o;
+ DEBUG_OUT(10) <= adc0_error;
+ DEBUG_OUT(11) <= adc0_frame_locked;
+ DEBUG_OUT(12) <= adc0_frame_clk_ok;
+ DEBUG_OUT(13) <= wait_timer_done;
+ DEBUG_OUT(14) <= RESET_CLKDIV;
+ DEBUG_OUT(15) <= RESET_ADC0;
+ end generate DFALSE;
+
+ DTRUE: if (DEBUG_ENABLE = true) generate
+
+ PROC_DEBUG: process (DEBUG_IN)
+ begin
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= DDR_DATA_CLK;
+
+ case DEBUG_IN is
+
+ when x"1" =>
+ DEBUG_OUT(15 downto 2) <= adc0_data_shift(0);
+
+ when x"2" =>
+ DEBUG_OUT(15 downto 2) <= adc0_data_shift(1);
+
+ when x"3" =>
+ DEBUG_OUT(15 downto 2) <= adc0_data_shift(2);
+
+ when x"4" =>
+ DEBUG_OUT(15 downto 2) <= adc0_data_shift(3);
+
+ when x"5" =>
+ DEBUG_OUT(15 downto 2) <= adc0_data_shift(4);
+
+ when others =>
+ -- DEBUG
+ DEBUG_OUT(2) <= adc0_write_enable;
+ DEBUG_OUT(3) <= adc0_fifo_full;
+ DEBUG_OUT(4) <= adc0_fifo_empty;
+ DEBUG_OUT(5) <= adc0_data_clk_m;
+ DEBUG_OUT(6) <= adc0_read_enable;
+ DEBUG_OUT(7) <= adc0_read_enable_t;
+ DEBUG_OUT(8) <= adc0_read_enable_tt;
+ DEBUG_OUT(9) <= adc0_data_clk_o;
+ DEBUG_OUT(10) <= adc0_error;
+ DEBUG_OUT(11) <= adc0_frame_locked;
+ DEBUG_OUT(12) <= adc0_frame_clk_ok;
+ DEBUG_OUT(13) <= wait_timer_done;
+ DEBUG_OUT(14) <= RESET_CLKDIV;
+ DEBUG_OUT(15) <= RESET_ADC0;
+
+ end case;
+ end process PROC_DEBUG;
+
+ end generate DTRUE;
+
+ -----------------------------------------------------------------------------
+
+ RESET_ADC0_CLKD_F <= RESET_ADC0 when rising_edge(DDR_DATA_CLK);
+ RESET_ADC0_CLKD <= RESET_ADC0_CLKD_F when rising_edge(DDR_DATA_CLK);
+ RESET_ADC1_CLKD_F <= RESET_ADC1 when rising_edge(DDR_DATA_CLK);
+ RESET_ADC1_CLKD <= RESET_ADC1_CLKD_F when rising_edge(DDR_DATA_CLK);
+
-----------------------------------------------------------------------------
+ timer_static_RESET_TIMER: timer_static
+ generic map (
+ CTR_WIDTH => 20,
+ CTR_END => 625000 -- 5ms
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => timer_reset,
+ TIMER_START_IN => wait_timer_start,
+ TIMER_DONE_OUT => wait_timer_done
+ );
+
+ PROC_DDR_RESET_HANDLER: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN)) then
+ if (RESET_IN = '1') then
+ RESET_CLKDIV <= '1';
+ RESET_ADC0 <= '1';
+ RESET_ADC1 <= '1';
+ wait_timer_start <= '0';
+ timer_reset <= '1';
+ startup_reset <= '1';
+ R_STATE <= R_IDLE;
+ else
+ RESET_CLKDIV <= '0';
+ RESET_ADC0 <= '0';
+ RESET_ADC1 <= '0';
+ wait_timer_start <= '0';
+ timer_reset <= '0';
+ startup_reset <= '0';
+
+ case R_STATE is
+ when R_IDLE =>
+ if (startup_reset = '1') then
+ -- Start Reset
+ RESET_CLKDIV <= '1';
+ RESET_ADC0 <= '1';
+ RESET_ADC1 <= '1';
+ wait_timer_start <= '1';
+ R_STATE <= R_WAIT_CLKDIV;
+ else
+ timer_reset <= '1';
+ R_STATE <= R_IDLE;
+ end if;
+
+ when R_WAIT_CLKDIV =>
+ if (wait_timer_done = '0') then
+ RESET_CLKDIV <= '1';
+ RESET_ADC0 <= '1';
+ RESET_ADC1 <= '1';
+ R_STATE <= R_WAIT_CLKDIV;
+ else
+ -- Release RESET_CLKDIV
+ RESET_ADC0 <= '1';
+ RESET_ADC1 <= '1';
+ wait_timer_start <= '1';
+ R_STATE <= R_WAIT_RESET_ADC;
+ end if;
+
+ when R_WAIT_RESET_ADC =>
+ if (wait_timer_done = '0') then
+ RESET_ADC0 <= '1';
+ RESET_ADC1 <= '1';
+ R_STATE <= R_WAIT_RESET_ADC;
+ else
+ -- Release reset_adc
+ wait_timer_start <= '1';
+ R_STATE <= R_WAIT_RESET_END;
+ end if;
+
+ when R_WAIT_RESET_END =>
+ if (wait_timer_done = '0') then
+ R_STATE <= R_WAIT_RESET_END;
+ else
+ R_STATE <= R_IDLE;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process PROC_DDR_RESET_HANDLER;
+
+ -----------------------------------------------------------------------------
+
adc_ddr_generic_1: adc_ddr_generic
port map (
clk_0 => ADC0_DCLK_IN,
clk_1 => ADC1_DCLK_IN,
- clkdiv_reset => RESET_CLK_ADCDAT_IN,
+ clkdiv_reset => RESET_CLKDIV,
eclk => CLK_ADCDAT_IN,
- reset_0 => RESET_DDR_DATA_CLK,
- reset_1 => RESET_DDR_DATA_CLK,
+ reset_0 => RESET_ADC0,
+ reset_1 => RESET_ADC1,
sclk => DDR_DATA_CLK,
datain_0(0) => ADC0_DATA_A_IN,
datain_1(2) => ADC1_DATA_C_IN,
datain_1(3) => ADC1_DATA_D_IN,
datain_1(4) => ADC1_FCLK_IN,
-
+
q_0 => q_0_ff,
q_1 => q_1_ff
);
q_1 <= q_1_f when rising_edge(DDR_DATA_CLK);
-----------------------------------------------------------------------------
-
- PROC_MERGE_DATA0: process(DDR_DATA_CLK)
- variable q_0_map : q_map_t;
+
+ PROC_MERGE_DATA_ADC0: process(DDR_DATA_CLK)
begin
if (rising_edge(DDR_DATA_CLK)) then
- if (RESET_DDR_DATA_CLK = '1') then
- adc0_new_data_t <= '0';
- adc0_frame_ctr <= (others => '0');
- adc0_frame_ctr_last <= (others => '0');
- adc0_bit_shift <= "00";
- adc0_bit_shift_last <= "00";
- adc0_ctr_error <= '0';
- adc0_shift_error <= '0';
- adc0_error_status <= (others => '0');
- adc0_frame_locked <= '0';
-
- for I in 0 to 3 loop
- adc0_data_t(I) <= (others => '0');
+ if (RESET_ADC0_CLKD = '1') then
+ for I in 0 to 4 loop
+ adc0_data_shift(I) <= (others => '0');
end loop;
+ for I in 0 to 3 loop
+ adc0_data_m(I) <= (others => '0');
+ end loop;
+ adc0_data_clk_m <= '0';
+
+ adc0_byte_status <= B_UNDEF;
+ adc0_byte_status_last <= B_UNDEF;
+ adc0_frame_clk_ok <= '0';
+ adc0_frame_clk_ok_hist <= (others => '0');
+ adc0_frame_locked <= '0';
+ adc0_error <= '0';
else
- adc0_shift_error <= '0';
- adc0_frame_locked <= '0';
-
- -- Remap DDR Output q_value
+ -- Store new incoming Data in Shift Registers
for I in 0 to 4 loop
- q_0_map(I) := q_0(I + 0) & q_0(I + 5) & q_0(I + 10) & q_0(I + 15);
- end loop;
-
- -- Buffer new incoming Data
- for I in 0 to 4 loop
- adc0_data_buf(I)(3 downto 0) <= q_0_map(I);
- adc0_data_buf(I)(15 downto 4) <= adc0_data_buf(I)(11 downto 0);
+ adc0_data_shift(I)(3) <= q_0(I + 0);
+ adc0_data_shift(I)(2) <= q_0(I + 5);
+ adc0_data_shift(I)(1) <= q_0(I + 10);
+ adc0_data_shift(I)(0) <= q_0(I + 15);
+ adc0_data_shift(I)(13 downto 4) <= adc0_data_shift(I)(9 downto 0);
end loop;
- -- Test Frame Clock Pattern
- case adc0_data_buf(4) is -- q_0_map(4) is THE Frame Clock
- when "0000111111000000" =>
- for I in 0 to 3 loop
- adc0_data_t(I) <= adc0_data_buf(I)(11 downto 0);
- end loop;
- adc0_new_data_t <= '1';
- adc0_bit_shift <= "00";
- adc0_frame_ctr <= (others => '0');
-
- when "0001111110000001" =>
+ -- Check Frame Lock and valid Status, Index 4 is THE Frame Clock
+ case adc0_data_shift(4)(11 downto 0) is
+ when "111111000000" =>
+ -- Input Data is correct and new Frame is available
for I in 0 to 3 loop
- adc0_data_t(I) <= adc0_data_buf(I)(12 downto 1);
+ adc0_data_m(I) <= adc0_data_shift(I)(11 downto 0);
end loop;
- adc0_new_data_t <= '1';
- adc0_bit_shift <= "01";
- adc0_frame_ctr <= (others => '0');
+ adc0_data_clk_m <= '1';
+ adc0_frame_clk_ok <= '1';
+ adc0_byte_status <= B_ALIGNED;
- when "0011111100000011" =>
+ when "111100000011" =>
+ -- Input Data is correct and new Frame is available,
+ -- but byte shifted by one
for I in 0 to 3 loop
- adc0_data_t(I) <= adc0_data_buf(I)(13 downto 2);
+ adc0_data_m(I) <= adc0_data_shift(I)(13 downto 2);
end loop;
- adc0_new_data_t <= '1';
- adc0_bit_shift <= "10";
- adc0_frame_ctr <= (others => '0');
+ adc0_data_clk_m <= '1';
+ adc0_frame_clk_ok <= '1';
+ adc0_byte_status <= B_SHIFTED;
+
+ when "110000001111" | "000011111100" =>
+ -- Input Data is correct
+ adc0_data_clk_m <= '0';
+ adc0_frame_clk_ok <= '1';
+ adc0_byte_status <= B_ALIGNED;
- when "0111111000000111" =>
- for I in 0 to 3 loop
- adc0_data_t(I) <= adc0_data_buf(I)(14 downto 3);
- end loop;
- adc0_new_data_t <= '1';
- adc0_bit_shift <= "11";
- adc0_frame_ctr <= (others => '0');
+ when "000000111111" | "001111110000" =>
+ -- Input Data is correct
+ adc0_data_clk_m <= '0';
+ adc0_frame_clk_ok <= '1';
+ adc0_byte_status <= B_SHIFTED;
when others =>
- for I in 0 to 3 loop
- adc0_data_t(I) <= (others => '0');
- end loop;
- adc0_new_data_t <= '0';
- adc0_frame_ctr <= adc0_frame_ctr + 1;
+ -- Input Data is invalid, Fatal Error of DDR Data, needs reset.
+ adc0_data_clk_m <= '0';
+ adc0_frame_clk_ok <= '0';
+ adc0_byte_status <= B_UNDEF;
+
end case;
- -- Monitor ADC Lock Status
- adc0_frame_ctr_last <= adc0_frame_ctr;
- if (adc0_new_data_t = '1') then
- if (adc0_frame_ctr_last /= x"2") then
- adc0_ctr_error <= '1';
- else
- adc0_ctr_error <= '0';
- end if;
- end if;
-
- adc0_bit_shift_last <= adc0_bit_shift;
- if (adc0_bit_shift /= adc0_bit_shift_last) then
- adc0_shift_error <= '1';
- else
- adc0_shift_error <= '0';
- end if;
-
- -- Error Status
- adc0_error_status(0) <= adc0_ctr_error or adc0_shift_error;
- for X in 0 to 14 loop
- adc0_error_status(X + 1) <= adc0_error_status(X);
- end loop;
+ -- Determin ADC Frame Lock Status
+ adc0_frame_clk_ok_hist(0) <= adc0_frame_clk_ok;
+ adc0_frame_clk_ok_hist(15 downto 1) <=
+ adc0_frame_clk_ok_hist(14 downto 0);
- if (adc0_error_status = x"0000") then
+ if (adc0_frame_clk_ok_hist = x"ffff") then
adc0_frame_locked <= '1';
else
adc0_frame_locked <= '0';
end if;
+ -- Error Status
+ adc0_byte_status_last <= adc0_byte_status;
+ if ( adc0_byte_status /= adc0_byte_status_last or
+ adc0_byte_status = B_UNDEF) then
+ adc0_error <= '1';
+ else
+ adc0_error <= '0';
+ end if;
end if;
+
end if;
- end process PROC_MERGE_DATA0;
+ end process PROC_MERGE_DATA_ADC0;
-----------------------------------------------------------------------------
-
- PROC_MERGE_DATA1: process(DDR_DATA_CLK)
- variable q_1_map : q_map_t;
+
+ PROC_MERGE_DATA_ADC1: process(DDR_DATA_CLK)
begin
if (rising_edge(DDR_DATA_CLK)) then
- if (RESET_DDR_DATA_CLK = '1') then
- adc1_new_data_t <= '0';
- adc1_frame_ctr <= (others => '0');
- adc1_frame_ctr_last <= (others => '0');
- adc1_bit_shift <= "00";
- adc1_bit_shift_last <= "00";
- adc1_ctr_error <= '0';
- adc1_shift_error <= '0';
- adc1_error_status <= (others => '0');
- adc1_frame_locked <= '0';
-
- for I in 0 to 3 loop
- adc1_data_t(I) <= (others => '0');
+ if (RESET_ADC1_CLKD = '1') then
+ for I in 0 to 4 loop
+ adc1_data_shift(I) <= (others => '0');
end loop;
- else
- adc1_ctr_error <= '0';
- adc1_shift_error <= '0';
+
+ for I in 0 to 3 loop
+ adc1_data_m(I) <= (others => '0');
+ end loop;
+ adc1_data_clk_m <= '0';
- -- Remap DDR Output q_value
- for I in 0 to 4 loop
- q_1_map(I) := q_1(I + 0) & q_1(I + 5) & q_1(I + 10) & q_1(I + 15);
- end loop;
+ adc1_byte_status <= B_UNDEF;
+ adc1_byte_status_last <= B_UNDEF;
+ adc1_frame_clk_ok <= '0';
+ adc1_frame_clk_ok_hist <= (others => '0');
+ adc1_frame_locked <= '0';
+ adc1_error <= '0';
+ else
- -- Buffer new incoming Data
+ -- Store new incoming Data in Shift Registers
for I in 0 to 4 loop
- adc1_data_buf(I)(3 downto 0) <= q_1_map(I);
- adc1_data_buf(I)(15 downto 4) <= adc1_data_buf(I)(11 downto 0);
+ adc1_data_shift(I)(3) <= q_1(I + 0);
+ adc1_data_shift(I)(2) <= q_1(I + 5);
+ adc1_data_shift(I)(1) <= q_1(I + 10);
+ adc1_data_shift(I)(0) <= q_1(I + 15);
+
+ adc1_data_shift(I)(13 downto 4) <= adc1_data_shift(I)(9 downto 0);
end loop;
- -- Test Frame Clock Pattern
- case adc1_data_buf(4) is -- adc1_data_buf(4) is frame clock
- when "0000111111000000" =>
+ -- Check Frame Lock and valid Status, Index 4 is THE Frame Clock
+ case adc1_data_shift(4)(11 downto 0) is
+ when "111111000000" =>
+ -- Input Data is correct and new Frame is available
for I in 0 to 3 loop
- adc1_data_t(I) <= adc1_data_buf(I)(11 downto 0);
+ adc1_data_m(I) <= adc1_data_shift(I)(11 downto 0);
end loop;
- adc1_new_data_t <= '1';
- adc1_bit_shift <= "00";
- adc1_frame_ctr <= (others => '0');
+ adc1_data_clk_m <= '1';
+ adc1_frame_clk_ok <= '1';
+ adc1_byte_status <= B_ALIGNED;
- when "0001111110000001" =>
+ when "111100000011" =>
+ -- Input Data is correct and new Frame is available,
+ -- but byte shifted by one
for I in 0 to 3 loop
- adc1_data_t(I) <= adc1_data_buf(I)(12 downto 1);
+ adc1_data_m(I) <= adc1_data_shift(I)(13 downto 2);
end loop;
- adc1_new_data_t <= '1';
- adc1_bit_shift <= "01";
- adc1_frame_ctr <= (others => '0');
+ adc1_data_clk_m <= '1';
+ adc1_frame_clk_ok <= '1';
+ adc1_byte_status <= B_SHIFTED;
+
+ when "110000001111" | "000011111100" =>
+ -- Input Data is correct
+ adc1_data_clk_m <= '0';
+ adc1_frame_clk_ok <= '1';
+ adc1_byte_status <= B_ALIGNED;
- when "0011111100000011" =>
- for I in 0 to 3 loop
- adc1_data_t(I) <= adc1_data_buf(I)(13 downto 2);
- end loop;
- adc1_new_data_t <= '1';
- adc1_bit_shift <= "10";
- adc1_frame_ctr <= (others => '0');
-
- when "0111111000000111" =>
- for I in 0 to 3 loop
- adc1_data_t(I) <= adc1_data_buf(I)(14 downto 3);
- end loop;
- adc1_new_data_t <= '1';
- adc1_bit_shift <= "11";
- adc1_frame_ctr <= (others => '0');
+ when "000000111111" | "001111110000" =>
+ -- Input Data is correct
+ adc1_data_clk_m <= '0';
+ adc1_frame_clk_ok <= '1';
+ adc1_byte_status <= B_SHIFTED;
when others =>
- for I in 0 to 3 loop
- adc1_data_t(I) <= (others => '0');
- end loop;
- adc1_new_data_t <= '0';
- adc1_frame_ctr <= adc1_frame_ctr + 1;
+ -- Input Data is invalid, Fatal Error of DDR Data, needs reset.
+ adc1_data_clk_m <= '0';
+ adc1_frame_clk_ok <= '0';
+ adc1_byte_status <= B_UNDEF;
end case;
- -- Monitor ADC Lock Status
- adc1_frame_ctr_last <= adc1_frame_ctr;
- if (adc1_new_data_t = '1') then
- if (adc1_frame_ctr_last /= x"2") then
- adc1_ctr_error <= '1';
- else
- adc1_ctr_error <= '0';
- end if;
- end if;
-
- adc1_bit_shift_last <= adc1_bit_shift;
- if (adc1_bit_shift /= adc1_bit_shift_last) then
- adc1_shift_error <= '1';
- else
- adc1_shift_error <= '0';
- end if;
-
- -- Error Status
- adc1_error_status(0) <= adc1_ctr_error or adc1_shift_error;
- for X in 0 to 14 loop
- adc1_error_status(X + 1) <= adc1_error_status(X);
- end loop;
+ -- Determin ADC Frame Lock Status
+ adc1_frame_clk_ok_hist(0) <= adc1_frame_clk_ok;
+ adc1_frame_clk_ok_hist(15 downto 1) <=
+ adc1_frame_clk_ok_hist(14 downto 0);
- if (adc1_error_status = x"0000") then
+ if (adc1_frame_clk_ok_hist = x"ffff") then
adc1_frame_locked <= '1';
else
adc1_frame_locked <= '0';
end if;
+ -- Error Status
+ adc1_byte_status_last <= adc1_byte_status;
+ if (adc1_byte_status /= adc1_byte_status_last or
+ adc1_byte_status = B_UNDEF) then
+ adc1_error <= '1';
+ else
+ adc1_error <= '0';
+ end if;
+
end if;
end if;
- end process PROC_MERGE_DATA1;
-
+ end process PROC_MERGE_DATA_ADC1;
+
+
-----------------------------------------------------------------------------
-- Tansfer to CLK_IN
-----------------------------------------------------------------------------
fifo_adc_48to48_dc_1: fifo_adc_48to48_dc
port map (
- Data(11 downto 0) => adc0_data_t(0),
- Data(23 downto 12) => adc0_data_t(1),
- Data(35 downto 24) => adc0_data_t(2),
- Data(47 downto 36) => adc0_data_t(3),
+ Data(11 downto 0) => adc0_data_m(0),
+ Data(23 downto 12) => adc0_data_m(1),
+ Data(35 downto 24) => adc0_data_m(2),
+ Data(47 downto 36) => adc0_data_m(3),
WrClock => DDR_DATA_CLK,
RdClock => CLK_IN,
WrEn => adc0_write_enable,
RdEn => adc0_read_enable,
- Reset => RESET_IN,
- RPReset => adc0_fifo_reset,
+ Reset => RESET_ADC0_CLKD,
+ RPReset => RESET_ADC0,
Q(11 downto 0) => adc0_data_f(0),
Q(23 downto 12) => adc0_data_f(1),
Q(35 downto 24) => adc0_data_f(2),
);
-- Readout Handler
- adc0_fifo_reset <= RESET_IN;
- adc0_write_enable <= adc0_new_data_t and not adc0_fifo_full;
+ adc0_write_enable <= adc0_data_clk_m and not adc0_fifo_full;
adc0_read_enable <= not adc0_fifo_empty;
PROC_ADC0_FIFO_READ: process(CLK_IN)
begin
if (rising_edge(CLK_IN)) then
- adc0_read_enable_t <= adc0_read_enable;
- if (RESET_IN = '1') then
+ adc0_read_enable_t <= adc0_read_enable;
+ if (RESET_ADC0_CLKD = '1') then
adc0_read_enable_tt <= '0';
for I in 0 to 3 loop
adc0_data_o(I) <= (others => '0');
end loop;
- adc0_data_valid_o <= '0';
+ adc0_data_clk_o <= '0';
else
-- Read enable
adc0_read_enable_tt <= adc0_read_enable_t;
for I in 0 to 3 loop
adc0_data_o(I) <= adc0_data_f(I);
end loop;
- adc0_data_valid_o <= '1';
+ adc0_data_clk_o <= '1';
else
- adc0_data_valid_o <= '0';
+ adc0_data_clk_o <= '0';
end if;
end if;
end if;
fifo_adc_48to48_dc_2: fifo_adc_48to48_dc
port map (
- Data(11 downto 0) => adc1_data_t(0),
- Data(23 downto 12) => adc1_data_t(1),
- Data(35 downto 24) => adc1_data_t(2),
- Data(47 downto 36) => adc1_data_t(3),
+ Data(11 downto 0) => adc1_data_m(0),
+ Data(23 downto 12) => adc1_data_m(1),
+ Data(35 downto 24) => adc1_data_m(2),
+ Data(47 downto 36) => adc1_data_m(3),
WrClock => DDR_DATA_CLK,
RdClock => CLK_IN,
- WrEn => adc1_new_data_t,
+ WrEn => adc1_write_enable,
RdEn => adc1_read_enable,
- Reset => RESET_IN,
- RPReset => adc1_fifo_reset,
+ Reset => RESET_ADC1_CLKD,
+ RPReset => RESET_ADC1,
Q(11 downto 0) => adc1_data_f(0),
Q(23 downto 12) => adc1_data_f(1),
Q(35 downto 24) => adc1_data_f(2),
);
-- Readout Handler
- adc1_fifo_reset <= RESET_IN;
- adc1_write_enable <= adc1_new_data_t and not adc1_fifo_full;
+ adc1_write_enable <= adc1_data_clk_m and not adc1_fifo_full;
adc1_read_enable <= not adc1_fifo_empty;
PROC_ADC1_FIFO_READ: process(CLK_IN)
begin
if (rising_edge(CLK_IN)) then
- if (RESET_IN = '1') then
+ if (RESET_ADC1_CLKD = '1') then
adc1_read_enable_t <= '0';
adc1_read_enable_tt <= '0';
for I in 0 to 3 loop
adc1_data_o(I) <= (others => '0');
end loop;
- adc1_data_valid_o <= '0';
+ adc1_data_clk_o <= '0';
else
-- Read enable
adc1_read_enable_t <= adc1_read_enable;
for I in 0 to 3 loop
adc1_data_o(I) <= adc1_data_f(I);
end loop;
- adc1_data_valid_o <= '1';
+ adc1_data_clk_o <= '1';
else
- adc1_data_valid_o <= '0';
+ adc1_data_clk_o <= '0';
end if;
end if;
end if;
end process PROC_ADC1_FIFO_READ;
- -----------------------------------------------------------------------------
- -- Lock Monitor
- -----------------------------------------------------------------------------
- signal_async_trans_1: signal_async_trans
- port map (
- CLK_IN => CLK_IN,
- SIGNAL_A_IN => not adc0_frame_locked,
- SIGNAL_OUT => adc0_frame_notlocked
- );
+ -- Domain Transfer
+ adc0_locked_ff <= adc0_frame_locked when rising_edge(CLK_IN);
+ adc0_locked_f <= adc0_locked_ff when rising_edge(CLK_IN);
+ adc0_locked_o <= adc0_locked_f when rising_edge(CLK_IN);
+
+ adc1_locked_ff <= adc1_frame_locked when rising_edge(CLK_IN);
+ adc1_locked_f <= adc1_locked_ff when rising_edge(CLK_IN);
+ adc1_locked_o <= adc1_locked_f when rising_edge(CLK_IN);
- signal_async_trans_2: signal_async_trans
+ pulse_dtrans_ADC0_ERROR: pulse_dtrans
+ generic map (
+ CLK_RATIO => 2
+ )
port map (
- CLK_IN => CLK_IN,
- SIGNAL_A_IN => not adc1_frame_locked,
- SIGNAL_OUT => adc1_frame_notlocked
+ CLK_A_IN => DDR_DATA_CLK,
+ RESET_A_IN => '0',
+ PULSE_A_IN => adc0_error,
+ CLK_B_IN => CLK_IN,
+ RESET_B_IN => '0',
+ PULSE_B_OUT => error_adc0_o
);
-
- level_to_pulse_1: level_to_pulse
+
+ pulse_dtrans_ADC1_ERROR: pulse_dtrans
+ generic map (
+ CLK_RATIO => 2
+ )
port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- LEVEL_IN => adc0_frame_notlocked,
- PULSE_OUT => adc0_frame_notlocked_p
+ CLK_A_IN => DDR_DATA_CLK,
+ RESET_A_IN => '0',
+ PULSE_A_IN => adc1_error,
+ CLK_B_IN => CLK_IN,
+ RESET_B_IN => '0',
+ PULSE_B_OUT => error_adc1_o
);
- level_to_pulse_2: level_to_pulse
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- LEVEL_IN => adc1_frame_notlocked,
- PULSE_OUT => adc1_frame_notlocked_p
- );
-
- PROC_NOTLOCK_COUNTER: process(CLK_IN)
- begin
- if (rising_edge(CLK_IN)) then
- if (RESET_IN = '1') then
- adc0_notlock_ctr <= (others => '0');
- adc1_notlock_ctr <= (others => '0');
- else
- if (adc0_frame_notlocked_p = '1') then
- adc0_notlock_ctr <= adc0_notlock_ctr + 1;
- end if;
-
- if (adc1_frame_notlocked_p = '1') then
- adc1_notlock_ctr <= adc1_notlock_ctr + 1;
- end if;
- end if;
- end if;
- end process PROC_NOTLOCK_COUNTER;
-
- PROC_ERROR: process(CLK_IN)
- begin
- if (rising_edge(CLK_IN)) then
- if (RESET_IN = '1') then
- error_adc0_o <= '0';
- error_adc1_o <= '0';
- else
- error_adc0_o <= '0';
- error_adc1_o <= '0';
-
- if (adc0_frame_notlocked = '1') then
- error_adc0_o <= '1';
- end if;
-
- if (adc1_frame_notlocked = '1') then
- error_adc1_o <= '1';
- end if;
- end if;
- end if;
- end process PROC_ERROR;
-
-- Output
-
ADC0_SCLK_OUT <= ADC0_SCLK_IN;
ADC1_SCLK_OUT <= ADC1_SCLK_IN;
ADC0_DATA_B_OUT <= adc0_data_o(1);
ADC0_DATA_C_OUT <= adc0_data_o(2);
ADC0_DATA_D_OUT <= adc0_data_o(3);
- ADC0_DATA_VALID_OUT <= adc0_data_valid_o;
+ ADC0_DATA_CLK_OUT <= adc0_data_clk_o;
ADC1_DATA_A_OUT <= adc1_data_o(0);
ADC1_DATA_B_OUT <= adc1_data_o(1);
ADC1_DATA_C_OUT <= adc1_data_o(2);
ADC1_DATA_D_OUT <= adc1_data_o(3);
- ADC1_DATA_VALID_OUT <= adc1_data_valid_o;
+ ADC1_DATA_CLK_OUT <= adc1_data_clk_o;
- ADC0_NOTLOCK_COUNTER <= adc0_notlock_ctr;
- ADC1_NOTLOCK_COUNTER <= adc1_notlock_ctr;
+ ADC0_LOCKED_OUT <= adc0_locked_o;
+ ADC1_LOCKED_OUT <= adc1_locked_o;
ERROR_ADC0_OUT <= error_adc0_o;
ERROR_ADC1_OUT <= error_adc1_o;
signal frame_word_delay_set : std_logic;
-- ADC Ckl Generator
- signal adc_clk_skip : std_logic;
+ signal adc_sclk_skip : std_logic;
signal adc_sampling_clk : std_logic;
signal johnson_ff_0 : std_logic;
signal johnson_ff_1 : std_logic;
signal johnson_counter_sync : std_logic_vector(1 downto 0);
- signal adc_clk_ok : std_logic;
- signal adc_clk_ok_c100 : std_logic;
+ signal adc_sclk_ok : std_logic;
+ signal adc_sclk_ok_f : std_logic;
+ signal adc_sclk_ok_c100 : std_logic;
signal pll_adc_sampling_clk_o : std_logic;
signal pll_adc_sampling_clk_lock : std_logic;
signal pll_adc_not_lock_ctr_clear : std_logic;
-- ADC RESET
- signal adc_clk_ok_last : std_logic;
+ signal adc_sclk_ok_last : std_logic;
signal adc_reset_sync_s : std_logic;
signal adc_reset_sync : std_logic;
signal adc_reset_ctr : unsigned(11 downto 0);
signal adc_data : std_logic_vector(11 downto 0);
signal adc_data_clk : std_logic;
signal adc_data_clk_c100 : std_logic;
+ signal adc_locked : std_logic;
+ signal adc_locked_c100 : std_logic;
+ signal adc_notlocked_p : std_logic;
signal adc_data_s : std_logic_vector(11 downto 0);
signal adc_data_s_clk : std_logic;
signal adc_notlock_ctr : unsigned(7 downto 0);
signal ADC_DEBUG : std_logic_vector(15 downto 0);
+ signal adc_debug_type_f : std_logic_vector(3 downto 0);
signal adc_debug_type : std_logic_vector(3 downto 0);
-- Merge Data Streams
signal rate_timer_ctr : unsigned(27 downto 0);
-- Error
- signal error_adc0_o : std_logic;
- signal error_adc1_o : std_logic;
+ signal adc_error_i : std_logic;
signal error_o : std_logic;
- signal error_status_bits : std_logic_vector(11 downto 0);
+ signal error_status_bits : std_logic_vector(15 downto 0);
+ signal adc_notlock_counter : unsigned(27 downto 0);
+ signal adc_error_counter : unsigned(27 downto 0);
-- Rate Errors
signal nx_frame_rate_offline_last : std_logic;
-----------------------------------------------------------------------------
-- NX FIFO READ ENABLE
- signal fifo_reset_i : std_logic;
- signal fifo_write_enable : std_logic;
- signal fifo_read_enable : std_logic;
- signal fifo_empty : std_logic;
- signal fifo_full : std_logic;
- signal fifo_data_clk_tt : std_logic;
- signal fifo_data_clk_t : std_logic;
- signal fifo_data_clk : std_logic;
-
- signal fifo_data : std_logic_vector(43 downto 0);
-
- -- Slave Bus
- signal slv_data_out_o : std_logic_vector(31 downto 0);
- signal slv_no_more_data_o : std_logic;
-
- signal slv_unknown_addr_o : std_logic;
- signal slv_ack_o : std_logic;
-
- signal reset_resync_ctr : std_logic;
- signal reset_parity_error_ctr : std_logic;
- signal debug_mode : std_logic_vector(2 downto 0);
- signal reset_handler_start_r : std_logic;
- signal adc_bit_shift : unsigned(3 downto 0);
- signal johnson_counter_sync_r : unsigned(1 downto 0);
- signal pll_adc_sample_clk_dphase_r : unsigned(3 downto 0);
+ signal fifo_reset_i : std_logic;
+ signal fifo_write_enable : std_logic;
+ signal fifo_read_enable : std_logic;
+ signal fifo_empty : std_logic;
+ signal fifo_full : std_logic;
+ signal fifo_data_clk_tt : std_logic;
+ signal fifo_data_clk_t : std_logic;
+ signal fifo_data_clk : std_logic;
+
+ signal fifo_data : std_logic_vector(43 downto 0);
+
+ -- Slave Bus
+ signal slv_data_out_o : std_logic_vector(31 downto 0);
+ signal slv_no_more_data_o : std_logic;
+
+ signal slv_unknown_addr_o : std_logic;
+ signal slv_ack_o : std_logic;
+
+ signal reset_resync_ctr : std_logic;
+ signal reset_parity_error_ctr : std_logic;
+ signal debug_mode : std_logic_vector(2 downto 0);
+ signal reset_handler_start_r : std_logic;
+ signal adc_bit_shift : unsigned(3 downto 0);
+ signal johnson_counter_sync_r : unsigned(1 downto 0);
+ signal pll_adc_sample_clk_dphase_r : unsigned(3 downto 0);
signal pll_adc_sample_clk_finedelb_r : unsigned(3 downto 0);
- signal nx_timestamp_delay_r : unsigned(2 downto 0);
- signal nx_frame_word_delay_r : unsigned(1 downto 0);
- signal fifo_full_r : std_logic;
- signal fifo_empty_r : std_logic;
- signal new_adc_dt_error_ctr_r : unsigned(11 downto 0);
- signal new_timestamp_dt_error_ctr_r : unsigned(11 downto 0);
- signal adc_notlock_ctr_r : unsigned(7 downto 0);
- signal merge_error_ctr_r : unsigned(11 downto 0);
- signal nx_frame_synced_r : std_logic;
- signal disable_adc_r : std_logic;
+ signal nx_timestamp_delay_r : unsigned(2 downto 0);
+ signal nx_frame_word_delay_r : unsigned(1 downto 0);
+ signal fifo_full_rr : std_logic;
+ signal fifo_full_r : std_logic;
+ signal fifo_empty_rr : std_logic;
+ signal fifo_empty_r : std_logic;
+ signal new_adc_dt_error_ctr_r : unsigned(11 downto 0);
+ signal new_timestamp_dt_error_ctr_r : unsigned(11 downto 0);
+ signal adc_notlock_ctr_r : unsigned(7 downto 0);
+ signal merge_error_ctr_r : unsigned(11 downto 0);
+ signal nx_frame_synced_rr : std_logic;
+ signal nx_frame_synced_r : std_logic;
+ signal disable_adc_r : std_logic;
+ signal adc_debug_type_r : std_logic_vector(3 downto 0);
-----------------------------------------------------------------------------
-- Reset Handler
-----------------------------------------------------------------------------
signal nx_online_ii : std_logic;
signal nx_online_i : std_logic;
- signal error_adc0_ff : std_logic;
- signal error_adc0_f : std_logic;
- signal error_adc0 : std_logic;
+ signal adc_error : std_logic;
signal startup_reset : std_logic;
signal rs_wait_timer_start : std_logic;
signal rs_wait_timer_done : std_logic;
R_WAIT_ADC_OK,
R_WAIT_DATA_HANDLER_OK
);
- signal R_STATE : R_STATES;
+ signal R_STATE : R_STATES;
signal frame_rates_reset : std_logic;
signal pll_adc_sampling_clk_reset : std_logic;
signal adc_reset_handler : std_logic;
signal adc_reset_p : std_logic;
signal output_handler_reset : std_logic;
- signal disable_adc_n : std_logic;
+ signal disable_adc_f : std_logic;
+ signal disable_adc : std_logic;
signal reset_handler_counter : unsigned(15 downto 0);
signal reset_handler_busy : std_logic;
signal reset_timeout_flag : std_logic;
+
+ signal adc_reset_handler_cnx_ff : std_logic;
+ signal adc_reset_handler_cnx_f : std_logic;
+ signal adc_reset_handler_cnx : std_logic;
-- Resync Counter Process
signal resync_counter : unsigned(11 downto 0);
signal resync_ctr_inc : std_logic;
signal reset_nx_timestamp_clk_in_f : std_logic;
signal RESET_NX_TIMESTAMP_CLK_IN : std_logic;
- signal debug_state : std_logic_vector(3 downto 0);
- signal debug_frame_on : std_logic;
-
+ signal debug_state : std_logic_vector(3 downto 0);
+ signal debug_frame_on : std_logic;
+
-- Keep FlipFlops, do not change to shift registers -----------
-
attribute syn_keep : boolean;
- attribute syn_keep of nx_frame_word_ff : signal is true;
- attribute syn_keep of nx_frame_word_f : signal is true;
attribute syn_keep of reset_nx_timestamp_clk_in_ff : signal is true;
attribute syn_keep of reset_nx_timestamp_clk_in_f : signal is true;
-
+
+ attribute syn_keep of adc_reset_handler_cnx_ff : signal is true;
+ attribute syn_keep of adc_reset_handler_cnx_f : signal is true;
+
attribute syn_keep of nx_frame_clk_delayed_t : signal is true;
attribute syn_keep of nx_frame_word_delayed_t : signal is true;
- attribute syn_keep of error_adc0_ff : signal is true;
- attribute syn_keep of error_adc0_f : signal is true;
-
attribute syn_keep of nx_online_ii : signal is true;
attribute syn_keep of nx_online_i : signal is true;
+
+ attribute syn_keep of disable_adc_f : signal is true;
+ attribute syn_keep of disable_adc : signal is true;
+
+ attribute syn_keep of adc_debug_type_f : signal is true;
+ attribute syn_keep of adc_debug_type : signal is true;
attribute syn_preserve : boolean;
- attribute syn_preserve of nx_frame_word_ff : signal is true;
- attribute syn_preserve of nx_frame_word_f : signal is true;
-
attribute syn_preserve of reset_nx_timestamp_clk_in_ff : signal is true;
attribute syn_preserve of reset_nx_timestamp_clk_in_f : signal is true;
-
+
+ attribute syn_preserve of adc_reset_handler_cnx_ff : signal is true;
+ attribute syn_preserve of adc_reset_handler_cnx_f : signal is true;
+
attribute syn_preserve of nx_frame_clk_delayed_t : signal is true;
attribute syn_preserve of nx_frame_word_delayed_t : signal is true;
- attribute syn_preserve of error_adc0_ff : signal is true;
- attribute syn_preserve of error_adc0_f : signal is true;
-
attribute syn_preserve of nx_online_ii : signal is true;
attribute syn_preserve of nx_online_i : signal is true;
+
+ attribute syn_preserve of disable_adc_f : signal is true;
+ attribute syn_preserve of disable_adc : signal is true;
+
+ attribute syn_preserve of adc_debug_type_f : signal is true;
+ attribute syn_preserve of adc_debug_type : signal is true;
begin
PROC_DEBUG_MULT: process(debug_mode,
adc_data,
adc_data_clk,
- adc_clk_ok,
- adc_clk_ok_last,
- adc_clk_skip,
+ adc_sclk_ok,
+ adc_sclk_skip,
adc_reset_sync,
adc_reset_sync_s,
ADC_RESET_AD9228,
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(1) <= nx_frame_clk;
DEBUG_OUT(2) <= adc_data_clk_c100; --clk_skip;
- DEBUG_OUT(3) <= adc_clk_ok;
+ DEBUG_OUT(3) <= adc_sclk_ok;
DEBUG_OUT(4) <= adc_reset_sync;
DEBUG_OUT(5) <= adc_reset_handler;
DEBUG_OUT(6) <= ADC_RESET_AD9228;
DEBUG_OUT(5) <= nx_frame_rate_offline;
DEBUG_OUT(6) <= nx_frame_rate_error;
DEBUG_OUT(7) <= pll_adc_not_lock;
- DEBUG_OUT(8) <= error_adc0_o;
+ DEBUG_OUT(8) <= adc_error;
DEBUG_OUT(9) <= adc_frame_rate_error;
DEBUG_OUT(10) <= fifo_reset_handler;
DEBUG_OUT(11) <= pll_adc_sampling_clk_reset;
end process PROC_DEBUG_MULT;
--- PROC_SAMPLE_CLOCK: process(NX_TIMESTAMP_CLK_IN)
--- begin
--- if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
--- if (NX_TIMESTAMP_IN = x"06" and
--- nx_frame_word_ff = x"7f") then
--- debug_frame_on <= '1';
--- else
--- debug_frame_on <= '0';
--- end if;
--- end if;
--- end process PROC_SAMPLE_CLOCK;
-
end generate DTRUE;
-----------------------------------------------------------------------------
timer_static_RESET_TIMER: timer_static
generic map (
CTR_WIDTH => 20,
- CTR_END => 500000 -- 1ms
+ CTR_END => 500000 -- 5ms
)
port map (
CLK_IN => CLK_IN,
RESET_B_IN => RESET_IN,
PULSE_B_OUT => adc_reset_sync
);
-
- signal_async_trans_ADC_CLK_OK: signal_async_trans
+
+ signal_async_trans_ADC_LOCKED: signal_async_trans
port map (
CLK_IN => CLK_IN,
- SIGNAL_A_IN => adc_clk_ok,
- SIGNAL_OUT => adc_clk_ok_c100
+ SIGNAL_A_IN => adc_locked,
+ SIGNAL_OUT => adc_locked_c100
);
-- ADC Sampling Clock Generator using a Johnson Counter
PROC_ADC_SAMPLING_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
- if (adc_clk_skip = '0') then
+ if (adc_sclk_skip = '0') then
johnson_ff_0 <= not johnson_ff_1;
johnson_ff_1 <= johnson_ff_0;
end if;
-- Adjust johnson_counter_sync to show optimal value at 0
PROC_ADC_SAMPLING_CLK_SYNC: process(NX_TIMESTAMP_CLK_IN)
- variable adc_clk_state : std_logic_vector(1 downto 0);
+ variable adc_sclk_state : std_logic_vector(1 downto 0);
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
johnson_counter_sync <= std_logic_vector(johnson_counter_sync_r);
- adc_clk_state := johnson_ff_1 & johnson_ff_0;
- adc_clk_skip <= '0';
+ adc_sclk_state := johnson_ff_1 & johnson_ff_0;
+ adc_sclk_skip <= '0';
if (nx_frame_clk = '1') then
- if (adc_clk_state /= johnson_counter_sync) then
- adc_clk_skip <= '1';
- adc_clk_ok <= '0';
+ if (adc_sclk_state /= johnson_counter_sync) then
+ adc_sclk_skip <= '1';
+ adc_sclk_ok <= '0';
else
- adc_clk_ok <= '1';
+ adc_sclk_ok <= '1';
end if;
end if;
end if;
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
- adc_clk_ok_last <= '0';
+ adc_sclk_ok_last <= '0';
adc_reset_sync_s <= '0';
else
adc_reset_sync_s <= '0';
- adc_clk_ok_last <= adc_clk_ok;
- if (adc_clk_ok_last = '0' and adc_clk_ok = '1') then
+ adc_sclk_ok_last <= adc_sclk_ok;
+ if (adc_sclk_ok_last = '0' and adc_sclk_ok = '1') then
adc_reset_sync_s <= '1';
end if;
end if;
-- NX Timestamp Handler
-----------------------------------------------------------------------------
- -- First use two FFs for NX_TIMESTAMP_IN
- PROC_INPUT_FF: process(NX_TIMESTAMP_CLK_IN)
- begin
- if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
- nx_frame_word_ff <= NX_TIMESTAMP_IN;
- nx_frame_word_f <= nx_frame_word_ff;
- end if;
- end process PROC_INPUT_FF;
-
+ -- First use two FFs for NX_TIMESTAMP_IN
+ nx_frame_word_ff <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN);
+ nx_frame_word_f <= nx_frame_word_ff when rising_edge(NX_TIMESTAMP_CLK_IN);
+
-- Second delay NX_TIMESTAMP_IN relatively to ADC Clock
dynamic_shift_register8x64_1: dynamic_shift_register8x64
port map (
frame_word_delay_change <= '0';
frame_word_delay_set <= '0';
- if (disable_adc_n = '1') then
+ if (disable_adc = '1') then
nx_frame_word_delay_f <= "10";
frame_word_delay_set <= '1';
else
-- ADC Input Handler
-----------------------------------------------------------------------------
- ADC_RESET_AD9228 <= RESET_NX_TIMESTAMP_CLK_IN or adc_reset_handler;
+ adc_reset_handler_cnx_ff <= adc_reset_handler
+ when rising_edge(NX_TIMESTAMP_CLK_IN);
+ adc_reset_handler_cnx_f <= adc_reset_handler_cnx_ff
+ when rising_edge(NX_TIMESTAMP_CLK_IN);
+ adc_reset_handler_cnx <= adc_reset_handler_cnx_f
+ when rising_edge(NX_TIMESTAMP_CLK_IN);
+
+ ADC_RESET_AD9228 <= RESET_NX_TIMESTAMP_CLK_IN or
+ adc_reset_handler_cnx;
+
+
+ adc_debug_type_f <= adc_debug_type_r
+ when rising_edge(NX_TIMESTAMP_CLK_IN);
+ adc_debug_type <= adc_debug_type_f
+ when rising_edge(NX_TIMESTAMP_CLK_IN);
+
adc_ad9228_1: adc_ad9228
+ generic map (
+ DEBUG_ENABLE => false
+ )
port map (
CLK_IN => NX_TIMESTAMP_CLK_IN,
RESET_IN => ADC_RESET_AD9228,
ADC0_DATA_B_OUT => open,
ADC0_DATA_C_OUT => open,
ADC0_DATA_D_OUT => open,
- ADC0_DATA_VALID_OUT => adc_data_clk,
+ ADC0_DATA_CLK_OUT => adc_data_clk,
ADC1_DATA_A_OUT => open,
ADC1_DATA_B_OUT => open,
ADC1_DATA_C_OUT => open,
ADC1_DATA_D_OUT => open,
- ADC1_DATA_VALID_OUT => open,
+ ADC1_DATA_CLK_OUT => open,
- ADC0_NOTLOCK_COUNTER => adc_notlock_ctr,
- ADC1_NOTLOCK_COUNTER => open,
+ ADC0_LOCKED_OUT => adc_locked,
+ ADC1_LOCKED_OUT => open,
- ERROR_ADC0_OUT => error_adc0_o,
- ERROR_ADC1_OUT => error_adc1_o,
+ ERROR_ADC0_OUT => adc_error_i,
+ ERROR_ADC1_OUT => open,
DEBUG_IN => adc_debug_type,
DEBUG_OUT => ADC_DEBUG
);
-----------------------------------------------------------------------------
-- Merge Data Streams Timestamps and ADC Value
-----------------------------------------------------------------------------
- merge_handler_reset_i <= output_handler_reset
- when rising_edge(NX_TIMESTAMP_CLK_IN);
- merge_handler_reset <= merge_handler_reset_i
- when rising_edge(NX_TIMESTAMP_CLK_IN);
- disable_adc_n <= disable_adc_r when rising_edge(NX_TIMESTAMP_CLK_IN);
+ merge_handler_reset_i <= output_handler_reset
+ when rising_edge(NX_TIMESTAMP_CLK_IN);
+ merge_handler_reset <= merge_handler_reset_i
+ when rising_edge(NX_TIMESTAMP_CLK_IN);
+ disable_adc_f <= disable_adc_r when rising_edge(NX_TIMESTAMP_CLK_IN);
+ disable_adc <= disable_adc_f when rising_edge(NX_TIMESTAMP_CLK_IN);
PROC_DATA_MERGE_HANDLER: process(NX_TIMESTAMP_CLK_IN)
begin
merge_error_ctr <= (others => '0');
else
if (nx_timestamp_delayed_clk = '1' and
- (adc_data_s_clk = '1' or disable_adc_n = '1')
+ (adc_data_s_clk = '1' or disable_adc = '1')
) then
data_frame(31 downto 0) <= nx_timestamp_delayed;
- if (disable_adc_n = '0') then
+ if (disable_adc = '0') then
data_frame(43 downto 32) <= adc_data_s;
else
data_frame(43 downto 32) <= x"dea";
-- Reset Handler
-----------------------------------------------------------------------------
- error_adc0_ff <= error_adc0_o when rising_edge(CLK_IN);
- error_adc0_f <= error_adc0_ff when rising_edge(CLK_IN);
- error_adc0 <= error_adc0_f when rising_edge(CLK_IN);
-
- nx_online_ii <= NX_ONLINE_IN when rising_edge(CLK_IN);
- nx_online_i <= nx_online_ii when rising_edge(CLK_IN);
+ nx_online_ii <= NX_ONLINE_IN when rising_edge(CLK_IN);
+ nx_online_i <= nx_online_ii when rising_edge(CLK_IN);
PROC_RESET_HANDLER: process(CLK_IN)
begin
debug_state <= x"6";
when R_WAIT_ADC_OK =>
- if (error_adc0 = '0' and
+ if (adc_locked_c100 = '1' and
adc_frame_rate_error = '0') then
-- Next: Release Output Handler and Clock Domain transfer Fifo
-- Resets
-----------------------------------------------------------------------------
-- Error Status
-----------------------------------------------------------------------------
+ level_to_pulse_ADC_NOTLOCKED: level_to_pulse
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ LEVEL_IN => not adc_locked_c100,
+ PULSE_OUT => adc_notlocked_p
+ );
+
+ pulse_dtrans_ADC_ERROR: pulse_dtrans
+ generic map (
+ CLK_RATIO => 2
+ )
+ port map (
+ CLK_A_IN => NX_TIMESTAMP_CLK_IN,
+ RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN,
+ PULSE_A_IN => adc_error_i,
+ CLK_B_IN => CLK_IN,
+ RESET_B_IN => RESET_IN,
+ PULSE_B_OUT => adc_error
+ );
+
+
PROC_ERROR_STATUS: process(CLK_IN)
begin
if (rising_edge(CLK_IN)) then
+ adc_sclk_ok_f <= adc_sclk_ok;
if (RESET_IN = '1') then
- error_status_bits <= (others => '0');
- error_o <= '0';
+ adc_sclk_ok_c100 <= '0';
+ error_status_bits <= (others => '0');
+ error_o <= '0';
+ adc_notlock_counter <= (others => '0');
+ adc_error_counter <= (others => '0');
else
- error_status_bits(0) <= nx_frame_rate_offline;
- error_status_bits(1) <= frame_rate_error;
- error_status_bits(2) <= nx_frame_rate_error;
- error_status_bits(3) <= adc_frame_rate_error;
- error_status_bits(4) <= parity_rate_error;
- error_status_bits(5) <= not nx_frame_synced_r;
- error_status_bits(6) <= error_adc0;
- error_status_bits(7) <= pll_adc_not_lock;
- error_status_bits(8) <= not adc_clk_ok_c100;
- error_status_bits(9) <= timestamp_dt_error;
- error_status_bits(10) <= adc_dt_error;
- error_status_bits(11) <= reset_handler_busy;
+ adc_sclk_ok_c100 <= adc_sclk_ok_f;
+
+ error_status_bits(0) <= nx_frame_rate_offline;
+ error_status_bits(1) <= frame_rate_error;
+ error_status_bits(2) <= nx_frame_rate_error;
+ error_status_bits(3) <= adc_frame_rate_error;
+ error_status_bits(4) <= parity_rate_error;
+ error_status_bits(5) <= not nx_frame_synced_r;
+ error_status_bits(6) <= adc_error;
+ error_status_bits(7) <= pll_adc_not_lock;
+ error_status_bits(8) <= not adc_sclk_ok_c100;
+ error_status_bits(9) <= not adc_locked_c100;
+ error_status_bits(10) <= timestamp_dt_error;
+ error_status_bits(11) <= adc_dt_error;
+ error_status_bits(12) <= reset_handler_busy;
+ error_status_bits(15 downto 13) <= (others => '0');
- if (error_status_bits = x"000") then
- error_o <= '0';
+ if (error_status_bits = x"0000") then
+ error_o <= '0';
else
- error_o <= '1';
+ error_o <= '1';
+ end if;
+
+ if (adc_notlocked_p = '1') then
+ adc_notlock_counter <= adc_notlock_counter + 1;
end if;
+
+ if (adc_error = '1') then
+ adc_error_counter <= adc_error_counter + 1;
+ end if;
+
end if;
end if;
end process PROC_ERROR_STATUS;
PROC_SLAVE_BUS_BUFFER: process(CLK_IN)
begin
if (rising_edge(CLK_IN) ) then
- fifo_full_r <= fifo_full;
- fifo_empty_r <= fifo_empty;
- new_adc_dt_error_ctr_r <= new_adc_dt_error_ctr;
- new_timestamp_dt_error_ctr_r <= new_timestamp_dt_error_ctr;
- adc_notlock_ctr_r <= adc_notlock_ctr;
- merge_error_ctr_r <= merge_error_ctr;
- nx_frame_synced_r <= nx_frame_synced;
+ fifo_full_rr <= fifo_full;
+ fifo_empty_rr <= fifo_empty;
+ nx_frame_synced_rr <= nx_frame_synced;
+ if (RESET_IN = '1') then
+ fifo_full_r <= '0';
+ fifo_empty_r <= '0';
+ nx_frame_synced_r <= '0';
+ new_adc_dt_error_ctr_r <= (others => '0');
+ new_timestamp_dt_error_ctr_r <= (others => '0');
+ adc_notlock_ctr_r <= (others => '0');
+ merge_error_ctr_r <= (others => '0');
+ else
+ fifo_full_r <= fifo_full_rr;
+ fifo_empty_r <= fifo_empty_rr;
+ nx_frame_synced_r <= nx_frame_synced_rr;
+ new_adc_dt_error_ctr_r <= new_adc_dt_error_ctr;
+ new_timestamp_dt_error_ctr_r <= new_timestamp_dt_error_ctr;
+ adc_notlock_ctr_r <= adc_notlock_ctr;
+ merge_error_ctr_r <= merge_error_ctr;
+ end if;
end if;
end process PROC_SLAVE_BUS_BUFFER;
nx_timestamp_delay_r <= "010";
reset_handler_start_r <= '0';
adc_bit_shift <= x"0";
- adc_debug_type <= (others => '0');
+ adc_debug_type_r <= (others => '0');
debug_mode <= (others => '0');
disable_adc_r <= '0';
else
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
- slv_data_out_o(11 downto 0) <= error_status_bits;
- slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_data_out_o(15 downto 0) <= error_status_bits;
+ slv_data_out_o(31 downto 16) <= (others => '0');
slv_ack_o <= '1';
when x"0001" =>
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
+ when x"0016" =>
+ slv_data_out_o(27 downto 0) <=
+ std_logic_vector(adc_notlock_counter);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0017" =>
+ slv_data_out_o(27 downto 0) <=
+ std_logic_vector(adc_error_counter);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
when x"001e" =>
slv_data_out_o(2 downto 0) <= debug_mode;
slv_data_out_o(31 downto 3) <= (others => '0');
slv_ack_o <= '1';
when x"001f" =>
- slv_data_out_o(3 downto 0) <= adc_debug_type;
+ slv_data_out_o(3 downto 0) <= adc_debug_type_r;
slv_data_out_o(31 downto 4) <= (others => '0');
slv_ack_o <= '1';
-
+
when others =>
slv_unknown_addr_o <= '1';
end case;
adc_bit_shift <=
unsigned(SLV_DATA_IN(3 downto 0));
slv_ack_o <= '1';
-
+
when x"001e" =>
debug_mode <= SLV_DATA_IN(2 downto 0);
slv_ack_o <= '1';
when x"001f" =>
- adc_debug_type <=
+ adc_debug_type_r <=
unsigned(SLV_DATA_IN(3 downto 0));
slv_ack_o <= '1';
CLK_IN : in std_logic;
RESET_IN : in std_logic;
-
NUM_AVERAGES_IN : in unsigned(2 downto 0);
AVERAGE_ENABLE_IN : in std_logic;
CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
-- Hist Fill/Ctr Handler
type H_STATES is (H_IDLE,
H_WRITEADD_CHANNEL,
- H_WRITE_CHANNEL
+ H_WRITE_CHANNEL,
+ H_ERASE,
+ H_ERASE_CHANNEL
);
signal H_STATE, H_NEXT_STATE : H_STATES;
signal write_enable : std_logic;
signal channel_write_busy_o : std_logic;
+
+ signal erase_counter_x : unsigned(BUS_WIDTH - 1 downto 0);
+ signal erase_counter : unsigned(BUS_WIDTH - 1 downto 0);
-- Hist Read Handler
signal read_address : std_logic_vector(BUS_WIDTH - 1 downto 0);
DEBUG_OUT(5) <= CHANNEL_READ_IN;
DEBUG_OUT(6) <= read_enable;
DEBUG_OUT(7) <= channel_data_valid_o;
- DEBUG_OUT(15 downto 8) <= channel_data_o(7 downto 0);
+ DEBUG_OUT(8) <= RESET_IN;
+ DEBUG_OUT(15 downto 9) <= channel_data_o(6 downto 0);
-----------------------------------------------------------------------------
if( RESET_IN = '1' ) then
address_hist_m <= (others => '0');
data_hist_m <= (others => '0');
- H_STATE <= H_IDLE;
+ erase_counter <= (others => '0');
+ H_STATE <= H_ERASE;
else
address_hist_m <= address_hist_m_x;
data_hist_m <= data_hist_m_x;
+ erase_counter <= erase_counter_x;
H_STATE <= H_NEXT_STATE;
end if;
end if;
begin
address_hist_m_x <= address_hist_m;
data_hist_m_x <= data_hist_m;
+ erase_counter_x <= erase_counter;
case H_STATE is
when H_IDLE =>
channel_write_busy_o <= '1';
H_NEXT_STATE <= H_IDLE;
+ when H_ERASE =>
+ write_address_hist <= (others => '0');
+ write_data_hist <= (others => '0');
+ write_data_ctr_hist <= (others => '0');
+ write_enable_hist <= '0';
+ write_address <= (others => '0');
+ write_data <= (others => '0');
+ write_enable <= '0';
+ erase_counter_x <= erase_counter + 1;
+ read_address_hist <= (others => '0');
+ read_enable_hist <= '0';
+ address_hist_m_x <= std_logic_vector(erase_counter);
+ data_hist_m_x <= (others => '0');
+ channel_write_busy_o <= '1';
+ H_NEXT_STATE <= H_ERASE_CHANNEL;
+
+ when H_ERASE_CHANNEL =>
+ new_data := unsigned(data_hist_m);
+ read_address_hist <= (others => '0');
+ read_enable_hist <= '0';
+ write_address_hist <= address_hist_m;
+ write_data_hist <= new_data;
+ write_data_ctr_hist <= (others => '0');
+ write_enable_hist <= '1';
+
+ write_address <= address_hist_m;
+ write_data <= new_data;
+ write_enable <= '1';
+ channel_write_busy_o <= '1';
+ if (erase_counter > 0) then
+ H_NEXT_STATE <= H_ERASE;
+ else
+ H_NEXT_STATE <= H_IDLE;
+ end if;
+
end case;
end process PROC_HIST_HANDLER;
signal ovfl_read_data_valid : std_logic;
-- ADC Value Histogram
- signal adc_num_averages : unsigned(2 downto 0);
- signal adc_average_enable : std_logic;
- signal adc_write_busy : std_logic;
- signal adc_read_busy : std_logic;
-
- signal adc_write_id : std_logic_vector(6 downto 0);
- signal adc_write_data : std_logic_vector(31 downto 0);
- signal adc_write : std_logic;
- signal adc_add : std_logic;
-
- signal adc_read_id : std_logic_vector(6 downto 0);
- signal adc_read : std_logic;
- signal adc_read_data : std_logic_vector(31 downto 0);
- signal adc_read_data_valid : std_logic;
-
- -- Slave Bus
+ signal adc_num_averages : unsigned(2 downto 0);
+ signal adc_average_enable : std_logic;
+ signal adc_write_busy : std_logic;
+ signal adc_read_busy : std_logic;
+
+ signal adc_write_id : std_logic_vector(6 downto 0);
+ signal adc_write_data : std_logic_vector(31 downto 0);
+ signal adc_write : std_logic;
+ signal adc_add : std_logic;
+
+ signal adc_read_id : std_logic_vector(6 downto 0);
+ signal adc_read : std_logic;
+ signal adc_read_data : std_logic_vector(31 downto 0);
+ signal adc_read_data_valid : std_logic;
+
+ -- Reset Hists
+ signal RESET_HISTS : std_logic;
+
+ -- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
signal slv_unknown_addr_o : std_logic;
-----------------------------------------------------------------------------
+ RESET_HISTS <= RESET_IN or RESET_HISTS_IN;
+
nx_histogram_hits: nx_histogram
port map (
CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
+ RESET_IN => RESET_HISTS,
NUM_AVERAGES_IN => hit_num_averages,
AVERAGE_ENABLE_IN => hit_average_enable,
nx_histogram_adc: nx_histogram
port map (
CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
+ RESET_IN => RESET_HISTS,
NUM_AVERAGES_IN => adc_num_averages,
AVERAGE_ENABLE_IN => adc_average_enable,
nx_histogram_pileup: nx_histogram
port map (
CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
+ RESET_IN => RESET_HISTS,
NUM_AVERAGES_IN => pileup_num_averages,
AVERAGE_ENABLE_IN => pileup_average_enable,
nx_histogram_ovfl: nx_histogram
port map (
CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
+ RESET_IN => RESET_HISTS,
NUM_AVERAGES_IN => ovfl_num_averages,
AVERAGE_ENABLE_IN => ovfl_average_enable,
PROC_FILL_HISTOGRAMS: process(CLK_IN)
begin
if (rising_edge(CLK_IN)) then
- if (RESET_IN = '1') then
+ if (RESET_HISTS = '1') then
hit_write_id <= (others => '0');
hit_write_data <= (others => '0');
hit_write <= '0';
PROC_HISTOGRAMS_READ: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' ) then
+ if (RESET_HISTS = '1') then
slv_data_out_o <= (others => '0');
slv_no_more_data_o <= '0';
slv_unknown_addr_o <= '0';
end entity;
architecture Behavioral of nx_trigger_handler is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "NX_TRIGGER_HANDLER";
-- Timing Trigger Handler
constant NUM_FF : integer := 10;
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
-
+
-- Inputs
DATA_CLK_IN : in std_logic;
TIMESTAMP_IN : in std_logic_vector(13 downto 0);
ADC_DATA_IN : in std_logic_vector(11 downto 0); -- 1: Pileup
NX_TOKEN_RETURN_IN : in std_logic; -- 0: Ovfl
NX_NOMORE_DATA_IN : in std_logic;
-
+
TRIGGER_IN : in std_logic;
TRIGGER_BUSY_IN : in std_logic;
FAST_CLEAR_IN : in std_logic;
TRIGGER_BUSY_OUT : out std_logic;
TIMESTAMP_FPGA_IN : in unsigned(11 downto 0);
DATA_FIFO_DELAY_OUT : out std_logic_vector(7 downto 0);
-
+
-- Event Buffer I/O
DATA_OUT : out std_logic_vector(31 downto 0);
DATA_CLK_OUT : out std_logic;
EVT_BUFFER_FULL_IN : in std_logic;
-- Histogram
+ HISTOGRAM_RESET_OUT : out std_logic;
HISTOGRAM_FILL_OUT : out std_logic;
HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0);
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic;
-
+
DEBUG_OUT : out std_logic_vector(15 downto 0)
);
architecture Behavioral of nx_trigger_validate is
-
constant S_PARITY : integer := 2;
constant S_PILEUP : integer := 1;
constant S_OVFL : integer := 0;
CS_SET_HIT,
CS_SET_DONE,
CS_NONE
- );
+ );
signal channel_status_cmd : CS_CMDS;
-- Process Calculate Trigger Window
signal window_hit_ctr_r : unsigned(15 downto 0);
signal out_of_window_h_ctr_r : unsigned(15 downto 0);
signal validation_busy : std_logic_vector(1 downto 0);
-
+ signal histogram_trigger_filter : std_logic;
+
-- Rate Calculations
signal data_rate_ctr_nr : unsigned(31 downto 0);
signal data_rate_ctr : unsigned(27 downto 0);
signal data_rate : unsigned(27 downto 0);
signal rate_timer_ctr : unsigned(27 downto 0);
-
+
-- Self Trigger Mode
signal self_trigger_mode : std_logic;
signal timer_reset : std_logic;
signal wait_timer_done : std_logic;
signal wait_timer_done_ns : std_logic;
-
+
-- Histogram
+
signal histogram_trigger_all : std_logic;
signal histogram_fill_o : std_logic;
signal histogram_bin_o : std_logic_vector(6 downto 0);
signal histogram_adc_o : std_logic_vector(11 downto 0);
signal histogram_pileup_o : std_logic;
signal histogram_ovfl_o : std_logic;
-
+
-- Data FIFO Delay
signal data_fifo_delay_o : unsigned(7 downto 0);
signal slv_no_more_data_o : std_logic;
signal slv_unknown_addr_o : std_logic;
signal slv_ack_o : std_logic;
-
+
signal readout_mode_r : std_logic_vector(3 downto 0);
- signal histogram_trigger_all_r : std_logic;
+ signal histogram_trigger_filter_r : std_logic;
signal out_of_window_error_ctr_clear : std_logic;
signal histogram_limits : std_logic;
signal histogram_lower_limit : unsigned(13 downto 0);
signal histogram_upper_limit : unsigned(13 downto 0);
+ signal reset_hists_r : std_logic;
+ signal reset_hists_o : std_logic;
-- Timestamp Trigger Window Settings
signal nxyter_cv_time : unsigned(11 downto 0);
begin
-- Debug Line
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= TRIGGER_IN;
- DEBUG_OUT(2) <= trigger_busy_o;
- DEBUG_OUT(3) <= DATA_CLK_IN;
- DEBUG_OUT(4) <= out_of_window_l;
- DEBUG_OUT(5) <= out_of_window_h;
- DEBUG_OUT(6) <= NX_TOKEN_RETURN_IN;
- DEBUG_OUT(7) <= NX_NOMORE_DATA_IN;
- DEBUG_OUT(8) <= channel_all_done;
- DEBUG_OUT(9) <= store_to_fifo;
- DEBUG_OUT(10) <= data_clk_o;
- DEBUG_OUT(11) <= out_of_window_error or EVT_BUFFER_FULL_IN;
- DEBUG_OUT(12) <= TIMESTAMP_STATUS_IN(S_PARITY);-- token_update; --TRIGGER_BUSY_IN; --wait_timer_done;
- DEBUG_OUT(13) <= min_val_time_expired;
- DEBUG_OUT(14) <= token_update;
- DEBUG_OUT(15) <= nomore_data_o;
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= TRIGGER_IN;
+ DEBUG_OUT(2) <= trigger_busy_o;
+ DEBUG_OUT(3) <= DATA_CLK_IN;
+ DEBUG_OUT(4) <= out_of_window_l;
+ DEBUG_OUT(5) <= out_of_window_h;
+ DEBUG_OUT(6) <= NX_TOKEN_RETURN_IN;
+ DEBUG_OUT(7) <= NX_NOMORE_DATA_IN;
+ DEBUG_OUT(8) <= channel_all_done;
+ DEBUG_OUT(9) <= store_to_fifo;
+ DEBUG_OUT(10) <= data_clk_o;
+ DEBUG_OUT(11) <= out_of_window_error or EVT_BUFFER_FULL_IN;
+ DEBUG_OUT(12) <= TIMESTAMP_STATUS_IN(S_PARITY);
+ DEBUG_OUT(13) <= min_val_time_expired;
+ DEBUG_OUT(14) <= token_update;
+ DEBUG_OUT(15) <= nomore_data_o;
-- Timer
timer_1: timer
begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
- d_data_o <= (others => '0');
- d_data_clk_o <= '0';
- out_of_window_l <= '0';
- out_of_window_h <= '0';
- window_hit <= '0';
- out_of_window_error <= '0';
- fifo_delay_time <= (others => '0');
- out_of_window_error_ctr <= (others => '0');
+ d_data_o <= (others => '0');
+ d_data_clk_o <= '0';
+ out_of_window_l <= '0';
+ out_of_window_h <= '0';
+ window_hit <= '0';
+ out_of_window_error <= '0';
+ fifo_delay_time <= (others => '0');
+ out_of_window_error_ctr <= (others => '0');
+ histogram_trigger_filter <= '0';
else
- d_data_o <= (others => '0');
- d_data_clk_o <= '0';
- out_of_window_l <= '0';
- out_of_window_h <= '0';
- window_hit <= '0';
- out_of_window_error <= '0';
- fifo_delay_time <= (others => '0');
- ch_status_cmd_pr <= CS_NONE;
+ d_data_o <= (others => '0');
+ d_data_clk_o <= '0';
+ out_of_window_l <= '0';
+ out_of_window_h <= '0';
+ window_hit <= '0';
+ out_of_window_error <= '0';
+ fifo_delay_time <= (others => '0');
+ ch_status_cmd_pr <= CS_NONE;
- histogram_fill_o <= '0';
- histogram_bin_o <= (others => '0');
- histogram_adc_o <= (others => '0');
- histogram_pileup_o <= '0';
- histogram_ovfl_o <= '0';
- histogram_trigger_all <= histogram_trigger_all_r;
+ histogram_fill_o <= '0';
+ histogram_bin_o <= (others => '0');
+ histogram_adc_o <= (others => '0');
+ histogram_pileup_o <= '0';
+ histogram_ovfl_o <= '0';
+ histogram_trigger_filter <= histogram_trigger_filter_r;
-----------------------------------------------------------------------
-- Calculate Thresholds and values for FIFO Delay
if (store_data = '1') then
case readout_mode(1 downto 0) is
-
+
when "00" =>
-- Default Mode
if (TIMESTAMP_STATUS_IN(S_PARITY) = '0') then
out_of_window_l_ctr <= (others => '0');
window_hit_ctr <= (others => '0');
out_of_window_l_ctr <= (others => '0');
-
+
when "01"=> -- Start validation
out_of_window_l_ctr <= (others => '0');
window_hit_ctr <= (others => '0');
out_of_window_l_ctr <= (others => '0');
-
+
when "10"=> -- End validation
out_of_window_l_ctr_r <= out_of_window_l_ctr;
window_hit_ctr_r <= window_hit_ctr;
end if;
min_validation_time_r <= min_validation_time;
wait_for_data_time_r <= wait_for_data_time;
-
+
-- Check Token Return
token_return_last <= NX_TOKEN_RETURN_IN;
if (store_to_fifo = '1' and -- min_val_time handled by TK-UPDATE
when S_TEST_SELF_TRIGGER =>
state_d <= "00";
-
+
if (self_trigger_mode = '1') then
-- Wait End of LVL2 Trigger Cycle
if (TRIGGER_BUSY_IN = '1') then
min_val_time_expired <= '0';
STATE <= S_IDLE;
end if;
-
+
when S_IDLE =>
state_d <= "01";
when CS_SET_DONE =>
channel_done(to_integer(unsigned(channel_index))) <= '1';
-
+
when CS_NONE => null;
end case;
data_fifo_delay_o <= x"01";
else
-- nxyter delay assumed to be 400ns
- nx_cvt := nxyter_cv_time / 4;
+ nx_cvt := nxyter_cv_time / 4;
if (fifo_delay_time > nx_cvt and fifo_delay_time < 1000) then
fifo_delay := (fifo_delay_time - nx_cvt) / 8;
data_fifo_delay_o <= fifo_delay(7 downto 0);
slv_ack_o <= '0';
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
-
+
ts_window_offset <= (others => '0');
ts_window_width <= "0000110010"; -- 50
cts_trigger_delay <= x"0c8";
readout_mode_r <= "0000";
readout_time_max <= x"3e8";
- histogram_trigger_all_r <= '1';
+ histogram_trigger_filter_r <= '1';
fpga_timestamp_offset <= (others => '0');
out_of_window_error_ctr_clear <= '0';
skip_wait_for_data <= '0';
nxyter_cv_time <= x"190"; -- 400ns
+ reset_hists_r <= '0';
else
- slv_data_out_o <= (others => '0');
- slv_unknown_addr_o <= '0';
- slv_no_more_data_o <= '0';
+ slv_data_out_o <= (others => '0');
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
cts_trigger_delay(11 downto 10) <= (others => '0');
readout_time_max(11 downto 10) <= (others => '0');
out_of_window_error_ctr_clear <= '0';
+ reset_hists_r <= '0';
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
slv_data_out_o( 3 downto 0) <= readout_mode_r;
- slv_data_out_o(30 downto 5) <= (others => '0');
- slv_data_out_o(31) <= histogram_trigger_all_r;
+ slv_data_out_o(31 downto 5) <= (others => '0');
slv_ack_o <= '1';
when x"0001" =>
std_logic_vector(cts_trigger_delay(9 downto 0));
slv_data_out_o(31 downto 10) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"0004" =>
slv_data_out_o(9 downto 0) <=
std_logic_vector(readout_time_max(9 downto 0));
slv_data_out_o(31 downto 8) <= (others => '0');
slv_ack_o <= '1';
- -- 4x Channel WAIT
-
+ -- 4x Channel WAIT
+
when x"000b" =>
slv_data_out_o <=
std_logic_vector(channel_wait_r(31 downto 0));
slv_data_out_o(31 downto 16) <= (others => '0');
slv_ack_o <= '1';
- --when x"001e" =>
- -- slv_data_out_o(15 downto 0) <=
- -- std_logic_vector(out_of_window_h_ctr_r);
- -- slv_data_out_o(31 downto 16) <= (others => '0');
- -- slv_ack_o <= '1';
+ --when x"001e" =>
+ -- slv_data_out_o(15 downto 0) <=
+ -- std_logic_vector(out_of_window_h_ctr_r);
+ -- slv_data_out_o(31 downto 16) <= (others => '0');
+ -- slv_ack_o <= '1';
when x"001e" =>
slv_data_out_o(27 downto 0) <= std_logic_vector(data_rate);
when x"001f" =>
slv_data_out_o(13 downto 0) <=
std_logic_vector(histogram_lower_limit);
- slv_data_out_o(15 downto 14) <= (others => '0');
- slv_data_out_o(29 downto 16) <=
+ slv_data_out_o(28 downto 15) <=
std_logic_vector(histogram_upper_limit);
- slv_data_out_o(30) <= '0';
- slv_data_out_o(31) <= histogram_limits;
+ slv_data_out_o(29) <= '0';
+ slv_data_out_o(30) <= histogram_limits;
+ slv_data_out_o(31) <= histogram_trigger_filter_r;
slv_ack_o <= '1';
when others =>
case SLV_ADDR_IN is
when x"0000" =>
readout_mode_r <= SLV_DATA_IN(3 downto 0);
- histogram_trigger_all_r <= SLV_DATA_IN(31);
slv_ack_o <= '1';
-
+
when x"0001" =>
if ((signed(SLV_DATA_IN(11 downto 0)) > -2048) and
(signed(SLV_DATA_IN(11 downto 0)) < 2048)) then
signed(SLV_DATA_IN(11 downto 0));
end if;
slv_ack_o <= '1';
-
+
when x"0002" =>
ts_window_width <=
unsigned(SLV_DATA_IN(9 downto 0));
when x"001f" =>
histogram_lower_limit <= SLV_DATA_IN(13 downto 0);
- histogram_upper_limit <= SLV_DATA_IN(29 downto 16);
- histogram_limits <= SLV_DATA_IN(31);
+ histogram_upper_limit <= SLV_DATA_IN(28 downto 15);
+ reset_hists_r <= SLV_DATA_IN(29);
+ histogram_limits <= SLV_DATA_IN(30);
+ histogram_trigger_filter_r <= SLV_DATA_IN(31);
slv_ack_o <= '1';
when others =>
-- Output Signals
-----------------------------------------------------------------------------
- data_clk_o <= d_data_clk_o or t_data_clk_o;
- data_o <= d_data_o or t_data_o;
+ pulse_to_level_RESET_HISTS: pulse_to_level
+ generic map (
+ NUM_CYCLES => 15
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ PULSE_IN => reset_hists_r,
+ LEVEL_OUT => reset_hists_o
+ );
+
+ data_clk_o <= d_data_clk_o or t_data_clk_o;
+ data_o <= d_data_o or t_data_o;
+
+ -----------------------------------------------------------------------------
TRIGGER_BUSY_OUT <= trigger_busy_o;
DATA_OUT <= data_o or t_data_o;
NOMORE_DATA_OUT <= nomore_data_o;
DATA_FIFO_DELAY_OUT <= std_logic_vector(data_fifo_delay_o);
EVT_BUFFER_CLEAR_OUT <= evt_buffer_clear_o;
-
+
+ HISTOGRAM_RESET_OUT <= reset_hists_o;
HISTOGRAM_FILL_OUT <= histogram_fill_o;
HISTOGRAM_BIN_OUT <= histogram_bin_o;
HISTOGRAM_ADC_OUT <= histogram_adc_o;
-------------------------------------------------------------------------------
component adc_ad9228
+ generic (
+ DEBUG_ENABLE : boolean
+ );
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
ADC0_DATA_B_OUT : out std_logic_vector(11 downto 0);
ADC0_DATA_C_OUT : out std_logic_vector(11 downto 0);
ADC0_DATA_D_OUT : out std_logic_vector(11 downto 0);
- ADC0_DATA_VALID_OUT : out std_logic;
+ ADC0_DATA_CLK_OUT : out std_logic;
ADC1_DATA_A_OUT : out std_logic_vector(11 downto 0);
ADC1_DATA_B_OUT : out std_logic_vector(11 downto 0);
ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0);
ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0);
- ADC1_DATA_VALID_OUT : out std_logic;
-
- ADC0_NOTLOCK_COUNTER : out unsigned(7 downto 0);
- ADC1_NOTLOCK_COUNTER : out unsigned(7 downto 0);
+ ADC1_DATA_CLK_OUT : out std_logic;
+ ADC0_LOCKED_OUT : out std_logic;
+ ADC1_LOCKED_OUT : out std_logic;
ERROR_ADC0_OUT : out std_logic;
ERROR_ADC1_OUT : out std_logic;
+
DEBUG_IN : in std_logic_vector(3 downto 0);
DEBUG_OUT : out std_logic_vector(15 downto 0)
);
NOMORE_DATA_OUT : out std_logic;
EVT_BUFFER_CLEAR_OUT : out std_logic;
EVT_BUFFER_FULL_IN : in std_logic;
+ HISTOGRAM_RESET_OUT : out std_logic;
HISTOGRAM_FILL_OUT : out std_logic;
HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0);
component signal_async_trans
generic (
- NUM_FF : integer range 2 to 4
+ NUM_FF : integer range 2 to 5
);
port (
CLK_IN : in std_logic;
signal trigger_validate_adc : std_logic_vector(11 downto 0);
signal trigger_validate_pileup : std_logic;
signal trigger_validate_ovfl : std_logic;
-
+ signal reset_hists : std_logic;
+
-- Event Buffer
signal fee_data_o_0 : std_logic_vector(31 downto 0);
signal fee_data_write_o_0 : std_logic;
NOMORE_DATA_OUT => validate_nomore_data,
EVT_BUFFER_CLEAR_OUT => event_buffer_clear,
EVT_BUFFER_FULL_IN => evt_buffer_full,
-
+
+ HISTOGRAM_RESET_OUT => reset_hists,
HISTOGRAM_FILL_OUT => trigger_validate_fill,
HISTOGRAM_BIN_OUT => trigger_validate_bin,
HISTOGRAM_ADC_OUT => trigger_validate_adc,
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- RESET_HISTS_IN => '0',
+ RESET_HISTS_IN => reset_hists,
CHANNEL_FILL_IN => trigger_validate_fill,
CHANNEL_ID_IN => trigger_validate_bin,
CHANNEL_ADC_IN => trigger_validate_adc,
end entity;
architecture Behavioral of pulse_dtrans is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "PULSE_DTRANS";
+-- attribute HGROUP : string;
+-- attribute HGROUP of Behavioral : architecture is "PULSE_DTRANS";
signal pulse_a_l : std_logic;
signal pulse_b_o : std_logic;
end entity;
architecture Behavioral of pulse_to_level is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "PULSE_TO_LEVEL";
+-- attribute HGROUP : string;
+-- attribute HGROUP of Behavioral : architecture is "PULSE_TO_LEVEL";
signal start_timer_x : std_logic;
---------------------------------------------------------------> Time t
+
+
+##############################################################################
+# nXyter FEB Clock Setup:
+#
+# CLK_PCLK_RIGHT : real Oszillator 200MHz
+# CLK_PCLK_RIGHT --> PLL#0 --> clk_100_i -----> Main Clock all entities
+#
+# CLK_PCLK_RIGHT --> nx_main_clk 1+2
+# (250 MHz) -----> nXyter Main Clock 1+2
+# |
+# |----> FPGA Timestamp Entity 1+2
+#
+# nx_main_clk 1+2 --> nXyter Data Clk
+# (1/2 = 125MHz) -----> FPGA Data Receiver
+# |
+# |----> Johnson 1/4 --> ADC SCLK
+#
+# CLK_PCLK_RIGHT (PLL#2) --> clk_adc_dat_1
+# (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 1
+#
+# CLK_PCLK_RIGHT (PLL#3) --> clk_adc_dat_2
+# (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 2
+
end entity;
architecture Behavioral of signal_async_to_pulse is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "SIGNAL_ASYNC_TO_PULSE";
+-- attribute HGROUP : string;
+-- attribute HGROUP of Behavioral : architecture is "SIGNAL_ASYNC_TO_PULSE";
signal pulse_ff : std_logic_vector(NUM_FF - 1 downto 0);
signal pulse_o : std_logic;
end entity;
architecture Behavioral of timer is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "NX_TIMER";
+-- attribute HGROUP : string;
+-- attribute HGROUP of Behavioral : architecture is "NX_TIMER";
-- Timer
signal timer_ctr_x : unsigned(CTR_WIDTH - 1 downto 0);
end entity;
architecture Behavioral of timer_static is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "NX_TIMER_STATIC";
+-- attribute HGROUP : string;
+-- attribute HGROUP of Behavioral : architecture is "NX_TIMER_STATIC";
-- Timer
constant ctr_limit : unsigned(CTR_WIDTH - 1 downto 0)
--- /dev/null
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 69
+-c 1
+-e 2
+-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
#
#################################################
-#BLOCK NET "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/fifo_adc_48to48_dc_*/r_gcount*";
MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 50 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_nx_timestamp_clk_in_ff*" 30 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/error_adc0_ff*" 30 ns;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_handler_reset_i*" 30 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler*" 30 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler_cnx_ff*" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_bit_shift*" 100 ns;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*" 100 ns;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_clk_ok" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_sclk_ok_f*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_notlock_ctr_r*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_error_ctr_r*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_r*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/disable_adc_n*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_full_rr*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_empty_rr*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_rr*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/disable_adc_f*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_f*" 100 ns;
+
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/RESET_CLKDIV*" 30 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/RESET_ADC0_CLKD_F*" 30 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc0_locked_o*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns;
# look at .par and .twr.setup file for clocks
# IN .mrp you find the semantic errors
-#PROHIBIT PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c";
-#PROHIBIT SECONDARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c";
-
+# DDR Generic PLL Setup, very important, do never remove!
+LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R61C5" ;
PROHIBIT PRIMARY NET "NX1_DATA_CLK_*";
PROHIBIT SECONDARY NET "NX1_DATA_CLK_*";
-#PROHIBIT PRIMARY NET "NX2_DATA_CLK_*";
-#PROHIBIT SECONDARY NET "NX2_DATA_CLK_*";
-
DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
-INPUT_SETUP GROUP "NX1_IN" 1.0 ns HOLD 1.0 ns CLKPORT="NX1_DATA_CLK_IN";
-
-#DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*";
-#INPUT_SETUP GROUP "NX2_IN" 2.0 ns HOLD 2.0 ns CLKPORT="NX2_DATA_CLK_IN";
+INPUT_SETUP GROUP "NX1_IN" 1.5 ns HOLD 1.5 ns CLKPORT="NX1_DATA_CLK_IN";
-UGROUP NXYTER1 BBOX 76 58
+UGROUP NXYTER1 BBOX 100 70
BLKNAME nXyter_FEE_board_0;
-LOCATE UGROUP NXYTER1 SITE "R28C2D";
-
-
-LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R61C5" ;
+LOCATE UGROUP NXYTER1 SITE "R2C2D";
--- /dev/null
+-w
+-i 2
+-l 5
+-n 28
+-t 28
+-s 1
+-c 1
+-e 2
+-stopzero
+-m nodelist.txt
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
jspc29 / trb3.git / commitdiff