port (
CLOCK_IN : in std_logic; -- oscillator
GLOBAL_RESET_IN : in std_logic;
-
- BUS_RX : in CTRLBUS_RX;
- BUS_TX : out CTRLBUS_TX;
RESET_OUT : out std_logic;
CLEAR_OUT : out std_logic;
DEBUG_OUT(15 downto 2) <= debug_reset_handler(15 downto 2);
DEBUG_OUT(31 downto 16) <= (others => '0');
-BUS_TX.data <= (others => '0');
-BUS_TX.unknown <= '1';
-BUS_TX.ack <= '0';
-BUS_TX.nack <= '0';
-
end architecture;
--- /dev/null
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+-- FPGA type
+ constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
+
+ constant FPGA_SIZE : string := "85KUM";
+
+-- select channel 0 or 1 in DCU
+ constant SERDES_NUM : integer := 0;
+
+-- Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F770";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"30";
+
+-- I/O specific
+ constant INCLUDE_UART : integer := c_NO; --300 slices
+ constant INCLUDE_SPI : integer := c_NO; --300 slices
+ constant INCLUDE_LCD : integer := c_NO; --800 slices
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices
+
+-- input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2
+ constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32
+ constant TRIG_GEN_INPUT_NUM : integer := 32;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := 32;
+
+-------------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------------
+
+--TDC settings
+ constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 2; --the nearest power of two, for convenience reasons
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+ -- 0: single edge only,
+ -- 1: same channel,
+ -- 2: alternating channels,
+ -- 3: same channel with stretcher
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
+ -- mode: 0, 1, 2, 3, 7
+ -- size: 32, 64, 96, 128, dyn
+ constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC
+ -- 0: Single fine time as the sum of the two transitions
+ -- 1: Double fine time, individual transitions
+ -- 13: Debug - fine time + (if 0x3ff full chain)
+ -- 14: Debug - single fine time and the ROM addresses for the two transitions
+ -- 15: Debug - complete carry chain dump
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t := (others => x"00");
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"A8000000";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
+
+ t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
+ t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+ t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+ t(15) := '1'; --TDC
+ t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+
+ t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
--- /dev/null
+Familyname => 'ECP5UM',
+Devicename => 'LFE5UM-85F',
+Package => 'CABGA756',
+Speedgrade => '8',
+
+
+TOPNAME => "trb5sc_template",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1702\@jspc29",
+lattice_path => '/d/jspc29/lattice/diamond/3.10_x64',
+synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/',
+
+nodelist_file => '../nodelist_frankfurt.txt',
+pinout_file => 'trb5sc_tdc',
+par_options => '../par.p2t',
+
+
+#Include only necessary lpf files
+include_TDC => 1,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 1, #if there is no serdes being used
--- /dev/null
+Familyname => 'ECP5UM5G',
+Devicename => 'LFE5UM5G-85F',
+Package => 'CABGA381',
+Speedgrade => '8',
+
+TOPNAME => "tomcat_gbe",
+lm_license_file_for_synplify => "27000\@lxcad04.gsi.de",
+lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lattice_path => '/opt/lattice/diamond/3.12',
+synplify_path => '/opt/synplicity/R-2020.09-SP1',
+synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier",
+
+nodelist_file => '../nodelist.txt',
+pinout_file => 'tomcat_prototype',
+par_options => '../par.p2t',
+
+include_TDC => 0,
+include_GBE => 0,
+
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 1, #must not be set for ECP5
+
--- /dev/null
+// nodes file for parallel place&route
+
+[hades66]
+system = linux
+corenum = 24
+ENV = /home/compile/bin/diamond_env
+workdir = /home/compile/vhdl/dirich/dirich/workdir
+
--- /dev/null
+// nodes file for parallel place&route
+
+[jspc37]
+SYSTEM = linux
+CORENUM = 7
+ENV = /d/jspc29/lattice/310_settings.sh
+WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir
+
+[jspc57]
+SYSTEM = linux
+CORENUM = 3
+ENV = /d/jspc29/lattice/310_settings.sh
+WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir
--- /dev/null
+-w
+-l 5
+-s 10
+-t 13 # seed setting here!
+-c 2
+-e 2
+-i 10
+-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+
--- /dev/null
+../../tdc/releases/tdc_v2.3
\ No newline at end of file
--- /dev/null
+COMMERCIAL ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+#FREQUENCY PORT CLK_200 200 MHz;
+#FREQUENCY PORT CLK_125 125 MHz;
+
+FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+
+FREQUENCY NET "med2int_0.clk_full" 200 MHz;
+
+BLOCK PATH TO PORT "LED*";
+BLOCK PATH TO PORT "PROGRAMN";
+BLOCK PATH TO PORT "TEMP_LINE";
+BLOCK PATH FROM PORT "TEMP_LINE";
+BLOCK PATH TO PORT "TEST_LINE*";
+
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
+
+## read from SCI can be delayed due to long read strobe
+#MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+## write strobe can be delayed due to A/D being stable after access
+#MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+
+GSR_NET NET "clear_i";
+
+REGION "MEDIA" "R81C44D" 13 25;
+LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
+
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology ECP5UM
+set_option -part LFE5UM_85F
+set_option -package BG381C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "tomcat_gbe"
+set_option -resource_sharing false
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+set_option -multi_file_compilation_unit 1
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/tomcat_gbe.edf"
+set_option log_file "workdir/tomcat_project.srf"
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um5g.vhd"
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+#add_file -vhdl -lib work "tdc_release/tdc_version.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
+add_file -vhdl -lib work "../../TOMcat/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+
+#I2C stuff
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire2.vhd"
+
+#GbE
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_5G.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface_5G.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
+
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/slv_mac_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
+
+# sgmii_core
+# tsmac
+# serdes_gbe
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+
+
+####################################################################################################
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../TOMcat/code/tomcat_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_RS.vhd"
+
+
+
+#########################################
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0_inv/serdes_sync_0.vhd"
+# 125MHz files
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs_125M.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0_125M_inv_5G/serdes_sync_0_125M.vhd"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_125M_softlogic.v"
+# 200MHz files
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs_200M.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0_200M_inv_5G/serdes_sync_0_200M.vhd"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_200M_softlogic.v"
+##########################################
+
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
+#add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
+
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
+
+
+add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
+add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
+add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
+add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
+add_file -vhdl -lib work "tdc_release/Channel.vhd"
+add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
+add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
+add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd"
+add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
+add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+add_file -vhdl -lib work "tdc_release/up_counter.vhd"
+
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
+
+add_file -vhdl -lib work "./tomcat_gbe.vhd"
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.version.all;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.med_sync_define_RS.all;
+
+entity tomcat_gbe is
+ port(
+ -- clock oscillators
+ CLK_200 : in std_logic;
+ CLK_125 : in std_logic;
+ -- SFP signals
+ SFP_TX_DIS : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_RATESEL : out std_logic;
+ SFP_MOD_0 : in std_logic; -- detect
+ SFP_MOD_1 : inout std_logic; -- SCL
+ SFP_MOD_2 : inout std_logic; -- SDA
+ -- Flash, Reload
+ FLASH_SCLK : out std_logic;
+ FLASH_NCS : out std_logic;
+ FLASH_MOSI : out std_logic;
+ FLASH_MISO : in std_logic;
+ FLASH_HOLD : out std_logic;
+ FLASH_WP : out std_logic;
+ FLASH_SELECT : in std_logic;
+ FLASH_OVERRIDE : out std_logic;
+ PROGRAMN : out std_logic;
+ -- I2C (temperature, UID)
+ I2C_SDA : inout std_logic;
+ I2C_SCL : inout std_logic;
+ -- LEDs
+ LED : out std_logic_vector(3 downto 0);
+ LED_SFP_YELLOW : out std_logic;
+ LED_SFP_GREEN : out std_logic;
+ LED_SFP_RED : out std_logic;
+ -- LVDS intercom
+-- INTCOM : inout std_logic_vector(9 downto 0); -- LVDS
+ INTCOM : inout std_logic_vector(19 downto 0); -- LVCMOS
+ -- timing measurements
+ TIMING_TEST : inout std_logic;
+ -- GPIO
+ GPIO : out std_logic_vector(15 downto 0)
+ );
+
+ attribute syn_useioff : boolean;
+ attribute syn_useioff of FLASH_NCS : signal is true;
+ attribute syn_useioff of FLASH_SCLK : signal is true;
+ attribute syn_useioff of FLASH_MOSI : signal is true;
+ attribute syn_useioff of FLASH_MISO : signal is true;
+
+end entity;
+
+architecture arch of tomcat_gbe is
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+ signal clk_sys : std_logic;
+ signal clk_full : std_logic;
+ signal clk_full_osc : std_logic;
+ signal GSR_N : std_logic;
+ signal reset_i : std_logic;
+ signal clear_i : std_logic;
+
+ signal led_i : std_logic_vector(3 downto 0);
+
+ signal uuid_i : std_logic_vector(63 downto 0);
+
+ signal gsc_init_data : std_logic_vector(15 downto 0);
+ signal gsc_reply_data : std_logic_vector(15 downto 0);
+ signal gsc_init_read : std_logic;
+ signal gsc_reply_read : std_logic;
+ signal gsc_init_dataready : std_logic;
+ signal gsc_reply_dataready : std_logic;
+ signal gsc_init_packet_num : std_logic_vector(2 downto 0);
+ signal gsc_reply_packet_num : std_logic_vector(2 downto 0);
+ signal gsc_busy : std_logic;
+
+ ----------------------------------------------------------------------------
+
+
+ signal debug_clock_reset : std_logic_vector(31 downto 0);
+ signal debug_tools : std_logic_vector(31 downto 0);
+
+ --Media Interface
+ signal med2int : med2int_array_t(0 to 0);
+ signal int2med : int2med_array_t(0 to 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+
+ signal readout_rx : READOUT_RX;
+ signal readout_tx : readout_tx_array_t(0 to 0);
+
+ signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX;
+ signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX;
+
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal bus_master_active : std_logic;
+
+ signal timer : TIMERS;
+ signal led_off : std_logic;
+
+ signal link_stat_in_reg : std_logic;
+
+
+ signal link_clock : std_logic;
+ signal full_reset : std_logic;
+ signal master_clk_i : std_logic;
+ signal tx_pll_lol_dual_a : std_logic;
+ signal tx_clk_avail_i : std_logic;
+ signal word_sync_i : std_logic;
+ signal tx_pcs_rst_i : std_logic;
+ signal link_tx_ready_i : std_logic;
+
+ signal rx_dlm_word : std_logic_vector(7 downto 0);
+ signal rx_dlm : std_logic;
+
+ signal debug_i : std_logic_vector(31 downto 0);
+
+ signal additional_reg : std_logic_vector(31 downto 0);
+
+ signal flash_ncs_i : std_logic;
+ signal flash_sclk_i : std_logic;
+ signal flash_miso_i : std_logic;
+ signal flash_mosi_i : std_logic;
+
+ signal ep_debug : std_logic_vector(15 downto 0);
+
+begin
+
+-------------------------------------------------------------------------------
+-- Clock & Reset Handling
+-------------------------------------------------------------------------------
+ THE_CLOCK_RESET : entity work.clock_reset_handler
+ port map(
+ CLOCK_IN => CLK_200,
+ GLOBAL_RESET_IN => '0',
+ RESET_OUT => reset_i,
+ CLEAR_OUT => clear_i,
+ GSR_OUT => GSR_N,
+ REF_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ RAW_CLK_OUT => clk_full_osc,
+ DEBUG_OUT => debug_clock_reset
+ );
+
+-------------------------------------------------------------------------------
+-- UUID handling, needed as MAC for GbE
+-------------------------------------------------------------------------------
+ THE_UUID_STUFF: trb_net_i2cwire2
+ generic map(
+ USE_TEMPERATURE_READOUT => 1,
+ CLK_PERIOD => 10
+ )
+ port map(
+ CLK => clk_sys,
+ RESET => clear_i,
+ READOUT_ENABLE_IN => '1',
+ --connection to I2C interface
+ SCL_INOUT => I2C_SCL,
+ SDA_INOUT => I2C_SDA,
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT => open,
+ ADDR_OUT => open,
+ WRITE_OUT => open,
+ TEMP_OUT => open,
+ ID_OUT => uuid_i,
+ STAT => open
+ );
+
+-------------------------------------------------------------------------------
+-- GbE interface
+-------------------------------------------------------------------------------
+ GBE : entity work.gbe_wrapper_5G
+ generic map(
+ DO_SIMULATION => 0,
+ INCLUDE_DEBUG => 0,
+ USE_INTERNAL_TRBNET_DUMMY => 0,
+ USE_EXTERNAL_TRBNET_DUMMY => 0,
+ RX_PATH_ENABLE => 1,
+ FIXED_SIZE_MODE => 1,
+ INCREMENTAL_MODE => 1,
+ FIXED_SIZE => 100,
+ FIXED_DELAY_MODE => 1,
+ UP_DOWN_MODE => 0,
+ UP_DOWN_LIMIT => 100,
+ FIXED_DELAY => 100,
+
+ NUMBER_OF_GBE_LINKS => 4,
+ LINKS_ACTIVE => "0001",
+
+ LINK_HAS_READOUT => "0000",
+ LINK_HAS_SLOWCTRL => "0001",
+ LINK_HAS_DHCP => "0001",
+ LINK_HAS_ARP => "0001",
+ LINK_HAS_PING => "0001",
+ LINK_HAS_FWD => "0000"
+ )
+ port map(
+ CLK_SYS_IN => clk_sys,
+ CLK_125_IN => CLK_125,
+ RESET => reset_i,
+ GSR_N => GSR_N,
+ -- Trigger
+ TRIGGER_IN => '0', --cts_rdo_rx.data_valid,
+ -- SFP
+ SD_PRSNT_N_IN(0) => SFP_MOD_0,
+ SD_LOS_IN(0) => SFP_LOS,
+ SD_TXDIS_OUT(0) => SFP_TX_DIS,
+ -- trigger channel
+ CTS_NUMBER_IN => (others => '0'), --gbe_cts_number,
+ CTS_CODE_IN => (others => '0'), --gbe_cts_code,
+ CTS_INFORMATION_IN => (others => '0'), --gbe_cts_information,
+ CTS_READOUT_TYPE_IN => (others => '0'), --gbe_cts_readout_type,
+ CTS_START_READOUT_IN => (others => '0'), --gbe_cts_start_readout,
+ CTS_DATA_OUT => open,
+ CTS_DATAREADY_OUT => open,
+ CTS_READOUT_FINISHED_OUT => open, --gbe_cts_readout_finished,
+ CTS_READ_IN => '1',
+ CTS_LENGTH_OUT => open,
+ CTS_ERROR_PATTERN_OUT => open, --gbe_cts_status_bits,
+ -- data channel
+ FEE_DATA_IN => (others => '0'), --gbe_fee_data,
+ FEE_DATAREADY_IN => '0', --gbe_fee_dataready,
+ FEE_READ_OUT => open, --gbe_fee_read,
+ FEE_STATUS_BITS_IN => (others => '0'), --gbe_fee_status_bits,
+ FEE_BUSY_IN => '0', --gbe_fee_busy,
+ -- unique adresses
+ MC_UNIQUE_ID_IN => uuid_i, --timer.uid,
+ MY_TRBNET_ADDRESS_IN => x"c000", --timer.network_address,
+ ISSUE_REBOOT_OUT => open, --reboot_from_gbe, -- reboot by GbE
+ -- slow control by GbE
+ GSC_CLK_IN => clk_sys,
+ GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
+ GSC_INIT_DATA_OUT => gsc_init_data,
+ GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
+ GSC_INIT_READ_IN => gsc_init_read,
+ GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
+ GSC_REPLY_DATA_IN => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
+ GSC_REPLY_READ_OUT => gsc_reply_read,
+ GSC_BUSY_IN => gsc_busy,
+ -- readout
+ BUS_IP_RX => open, --busgbeip_rx,
+ BUS_IP_TX => open, --busgbeip_tx,
+ BUS_REG_RX => open, --busgbereg_rx,
+ BUS_REG_TX => open, --busgbereg_tx,
+ -- reset
+ MAKE_RESET_OUT => open, --reset_via_gbe, -- reset by GbE
+ -- debug
+ DEBUG_OUT => open
+ );
+
+
+-------------------------------------------------------------------------------
+-- Outputs
+-------------------------------------------------------------------------------
+ INTCOM(19 downto 0) <= (others => '0');
+-- INTCOM(19) <= '0';
+-- INTCOM(18) <= '0';
+-- INTCOM(17) <= '0';
+-- INTCOM(16) <= '0';
+-- INTCOM(15) <= '0';
+-- INTCOM(14) <= '0';
+-- INTCOM(13) <= '0';
+-- INTCOM(12) <= '0';
+-- INTCOM(11) <= '0';
+-- INTCOM(10) <= '0';
+-- INTCOM(9) <= '0';
+-- INTCOM(8) <= '0';
+-- INTCOM(7) <= '0';
+-- INTCOM(6) <= '0';
+-- INTCOM(5) <= '0';
+-- INTCOM(4) <= '0';
+-- INTCOM(3) <= '0';
+-- INTCOM(2) <= '0';
+-- INTCOM(1) <= '0';
+-- INTCOM(0) <= '0';
+
+ GPIO <= (others => '0');
+-- GPIO(15) <= '0';
+-- GPIO(14) <= '0';
+-- GPIO(13) <= '0';
+-- GPIO(12) <= '0';
+-- GPIO(11) <= '0';
+-- GPIO(10) <= '0';
+-- GPIO(9) <= '0';
+-- GPIO(8) <= '0';
+-- GPIO(7) <= '0';
+-- GPIO(6) <= '0';
+-- GPIO(9) <= '0';
+-- GPIO(4) <= '0';
+-- GPIO(3) <= '0';
+-- GPIO(2) <= '0';
+-- GPIO(1) <= '0';
+-- GPIO(0) <= '0';
+
+ TIMING_TEST <= '0';
+
+-------------------------------------------------------------------------------
+-- LED
+-------------------------------------------------------------------------------
+ LED_SFP_GREEN <= not '0';
+ LED_SFP_RED <= not '0';
+ LED_SFP_YELLOW <= not '0';
+ LED(3) <= not '0';
+ LED(2) <= not '0';
+ LED(1) <= not '0';
+ LED(0) <= not '0';
+
+ -- 0 red
+ -- 1 orange
+ -- 2 green
+ -- 3 green
+
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+
+-- type CTRLBUS_TX is record
+-- data : std_logic_vector(31 downto 0);
+-- ack : std_logic;
+-- wack,rack : std_logic; --for the old-fashioned guys
+-- unknown : std_logic;
+-- nack : std_logic;
+-- end record;
+
+-- type CTRLBUS_RX is record
+-- data : std_logic_vector(31 downto 0);
+-- addr : std_logic_vector(15 downto 0);
+-- write : std_logic;
+-- read : std_logic;
+-- timeout : std_logic;
+-- end record;
+
+-------------------------------------------------------------------------------
+-- Bus Handler
+-------------------------------------------------------------------------------
+-- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+-- generic map(
+-- PORT_NUMBER => 4,
+-- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", others => x"0000"),
+-- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, others => 0),
+-- PORT_MASK_ENABLE => 1
+-- )
+-- port map(
+-- CLK => clk_sys,
+-- RESET => reset_i,
+-- REGIO_RX => ctrlbus_rx,
+-- REGIO_TX => ctrlbus_tx,
+-- BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+-- BUS_RX(1) => bussci_rx, --SCI Serdes
+-- BUS_RX(2) => bustc_rx, --Clock switch
+-- BUS_TX(0) => bustools_tx,
+-- BUS_TX(1) => bussci_tx,
+-- BUS_TX(2) => bustc_tx,
+-- STAT_DEBUG => open
+-- );
+
+-------------------------------------------------------------------------------
+-- Control Tools
+-------------------------------------------------------------------------------
+-- THE_TOOLS : entity work.tomcat_tools
+-- port map(
+-- CLK => clk_sys,
+-- RESET => reset_i,
+-- --Flash & Reload
+-- FLASH_CS => flash_ncs_i,
+-- FLASH_CLK => flash_sclk_i,
+-- FLASH_IN => flash_miso_i,
+-- FLASH_OUT => flash_mosi_i,
+-- PROGRAMN => PROGRAMN,
+-- REBOOT_IN => common_ctrl_reg(15),
+-- -- I2C
+-- SDA_INOUT => SFP_MOD_2, --open, --I2C_SDA,
+-- SCL_INOUT => SFP_MOD_1, --open, --SI2C_SCL,
+-- -- Additional register
+-- ADDITIONAL_REG => additional_reg,
+-- --Slowcontrol
+-- BUS_RX => bustools_rx,
+-- BUS_TX => bustools_tx,
+-- --Control master for default settings
+-- BUS_MASTER_IN => bus_master_in,
+-- BUS_MASTER_OUT => bus_master_out,
+-- BUS_MASTER_ACTIVE => bus_master_active,
+-- DEBUG_OUT => debug_tools
+-- );-
+--
+-- led_off <= additional_reg(0);
+--
+-- -- FlashROM external connections
+-- FLASH_OVERRIDE <= not additional_reg(1);
+-- FLASH_HOLD <= '1';
+-- FLASH_WP <= '1';
+-- FLASH_NCS <= flash_ncs_i;
+-- FLASH_SCLK <= flash_sclk_i;
+-- FLASH_MOSI <= flash_mosi_i;
+-- flash_miso_i <= FLASH_MISO;
+--
+-- -- Jan's proposal
+-- -- led_off <= additional_reg(0);
+-- -- FLASH_OVERRIDE <= not additional_reg(1);
+
+end architecture;
####################
-add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd"
+add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um5g.vhd"
#Packages
add_file -vhdl -lib work "workdir/version.vhd"
signal readout_rx : READOUT_RX;
signal readout_tx : readout_tx_array_t(0 to 0);
- signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX;
- signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX;
+ signal ctrlbus_tx, bussci_tx, bustools_tx, busthresh_tx, bus_master_in : CTRLBUS_TX;
+ signal ctrlbus_rx, bussci_rx, bustools_rx, busthresh_rx, bus_master_out : CTRLBUS_RX;
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
port map(
CLOCK_IN => CLK_200,
GLOBAL_RESET_IN => global_reset_i,
- BUS_RX => bustc_rx,
- BUS_TX => bustc_tx,
RESET_OUT => reset_i,
CLEAR_OUT => clear_i,
GSR_OUT => GSR_N,
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
---trigger_in_i <= INTCOM(0); -- BUG: we need a "timing trigger"
-trigger_in_i <= TIMING_TEST; -- BUG: we need a "timing trigger"
+trigger_in_i <= INTCOM(0); -- BUG: we need a "timing trigger"
-- at least 100ns!
---INTCOM(9 downto 1) <= (others => '0');
+INTCOM(9 downto 1) <= (others => '0');
---TIMING_TEST <= rx_dlm;
+TIMING_TEST <= rx_dlm;
-------------------------------------------------------------------------------
-- Endpoint
-------------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, others => 0),
+ PORT_NUMBER => 2,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
REGIO_TX => ctrlbus_tx,
BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
BUS_RX(1) => bussci_rx, --SCI Serdes
- BUS_RX(2) => bustc_rx, --Clock switch
BUS_TX(0) => bustools_tx,
BUS_TX(1) => bussci_tx,
- BUS_TX(2) => bustc_tx,
STAT_DEBUG => open
);
-------------------------------------------------------------------------------
-- I/O
-------------------------------------------------------------------------------
--- GPIO <= (others => '0');
- GPIO(15) <= ep_debug(3); --'0'; -- reg.nack
- GPIO(14) <= ctrlbus_tx.nack; --'0';
- GPIO(13) <= ctrlbus_tx.ack; --'0';
- GPIO(12) <= ctrlbus_rx.write; --'0';
- GPIO(11) <= ctrlbus_rx.read; --'0';
- GPIO(10) <= bustools_rx.addr(0); --'0';
- GPIO(9) <= bustools_tx.ack; --'0';
- GPIO(8) <= bustools_rx.write; --'0';
- GPIO(7) <= bustools_rx.read; --'0';
- GPIO(6) <= debug_tools(8); --'0'; -- spi.busy
- GPIO(5) <= debug_tools(6); --'0'; -- mem.ack
- GPIO(4) <= debug_tools(5); --'0'; -- mem.write
- GPIO(3) <= debug_tools(4); --'0'; -- mem.read
- GPIO(2) <= ep_debug(2); --'0'; -- reg.ack
- GPIO(1) <= ep_debug(1); --'0'; -- reg.write
- GPIO(0) <= ep_debug(0); --'0'; -- reg.read
+ GPIO <= (others => '0');
+-- GPIO(15) <= ep_debug(3); --'0'; -- reg.nack
+-- GPIO(14) <= ctrlbus_tx.nack; --'0';
+-- GPIO(13) <= ctrlbus_tx.ack; --'0';
+-- GPIO(12) <= ctrlbus_rx.write; --'0';
+-- GPIO(11) <= ctrlbus_rx.read; --'0';
+-- GPIO(10) <= bustools_rx.addr(0); --'0';
+-- GPIO(9) <= bustools_tx.ack; --'0';
+-- GPIO(8) <= bustools_rx.write; --'0';
+-- GPIO(7) <= bustools_rx.read; --'0';
+-- GPIO(6) <= debug_tools(8); --'0'; -- spi.busy
+-- GPIO(5) <= debug_tools(6); --'0'; -- mem.ack
+-- GPIO(4) <= debug_tools(5); --'0'; -- mem.write
+-- GPIO(3) <= debug_tools(4); --'0'; -- mem.read
+-- GPIO(2) <= ep_debug(2); --'0'; -- reg.ack
+-- GPIO(1) <= ep_debug(1); --'0'; -- reg.write
+-- GPIO(0) <= ep_debug(0); --'0'; -- reg.read
- INTCOM(19) <= '0';
- INTCOM(18) <= '0';
- INTCOM(17) <= '0';
- INTCOM(16) <= int2med(0).data(3);
- INTCOM(15) <= int2med(0).data(2);
- INTCOM(14) <= int2med(0).data(1);
- INTCOM(13) <= int2med(0).data(0);
- INTCOM(12) <= med2int(0).data(3);
- INTCOM(11) <= med2int(0).data(2);
- INTCOM(10) <= med2int(0).data(1);
- INTCOM(9) <= med2int(0).data(0);
- INTCOM(8) <= int2med(0).dataready;
- INTCOM(7) <= int2med(0).packet_num(2);
- INTCOM(6) <= int2med(0).packet_num(1);
- INTCOM(5) <= int2med(0).packet_num(0);
- INTCOM(4) <= med2int(0).tx_read;
- INTCOM(3) <= med2int(0).dataready;
- INTCOM(2) <= med2int(0).packet_num(2);
- INTCOM(1) <= med2int(0).packet_num(1);
- INTCOM(0) <= med2int(0).packet_num(0);
+-- INTCOM(19) <= '0';
+-- INTCOM(18) <= '0';
+-- INTCOM(17) <= '0';
+-- INTCOM(16) <= int2med(0).data(3);
+-- INTCOM(15) <= int2med(0).data(2);
+-- INTCOM(14) <= int2med(0).data(1);
+-- INTCOM(13) <= int2med(0).data(0);
+-- INTCOM(12) <= med2int(0).data(3);
+-- INTCOM(11) <= med2int(0).data(2);
+-- INTCOM(10) <= med2int(0).data(1);
+-- INTCOM(9) <= med2int(0).data(0);
+-- INTCOM(8) <= int2med(0).dataready;
+-- INTCOM(7) <= int2med(0).packet_num(2);
+-- INTCOM(6) <= int2med(0).packet_num(1);
+-- INTCOM(5) <= int2med(0).packet_num(0);
+-- INTCOM(4) <= med2int(0).tx_read;
+-- INTCOM(3) <= med2int(0).dataready;
+-- INTCOM(2) <= med2int(0).packet_num(2);
+-- INTCOM(1) <= med2int(0).packet_num(1);
+-- INTCOM(0) <= med2int(0).packet_num(0);
-------------------------------------------------------------------------------
-- LED
LED_SFP_GREEN <= not med2int(0).stat_op(9) or led_off;
LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;
LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off;
- LED(3) <= not rx_dlm_word(7); --led_i(3) or led_off;
- LED(2) <= not debug_i(2) or led_off; --led_i(2) or led_off;
- LED(1) <= not debug_i(1) or led_off; --led_i(1) or led_off;
- LED(0) <= not debug_i(0) or led_off; --led_i(0) or led_off;
+ LED(3) <= not rx_dlm_word(7) or led_off; --led_i(3) or led_off;
+ LED(2) <= not debug_i(2) or led_off; --led_i(2) or led_off;
+ LED(1) <= not debug_i(1) or led_off; --led_i(1) or led_off;
+ LED(0) <= not debug_i(0) or led_off; --led_i(0) or led_off;
-- 0 red
-- 1 orange
readout_tx(0).busy_release <= '1';
end architecture;
-
-
-
jspc29 / TOMcat.git / commitdiff