added I2C for Serdes, new reset routine and more stable CDR settings, mt

diff --git a/dirich5s/config_compile_gsi.pl b/dirich5s/config_compile_gsi.pl
index 1af88c94061a6e42b61c680bf630c0df0419ef13..6f76e304746ab885c34c43c32d8905ba046c38ad 100644 (file)
--- a/dirich5s/config_compile_gsi.pl
+++ b/dirich5s/config_compile_gsi.pl
@@ -4,13 +4,13 @@ Package     => 'CABGA381',
 Speedgrade  => '8',
 
 TOPNAME                      => "dirich5s",
-lm_license_file_for_synplify => "27000\@lxcad03.gsi.de",
+lm_license_file_for_synplify => "27000\@lxcad04.gsi.de",
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
 lattice_path                 => '/opt/lattice/diamond/3.12',
-synplify_path                => '/opt/synplicity/R-2020.09-SP1',
+synplify_path                => '/opt/synplicity/T-2022.09-SP2',
 #synplify_command             => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options",
 #synplify_command             => "/opt/synplicity/P-2019.09-SP1/bin/synplify_premier_dp",
-synplify_command             => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier_dp",
+synplify_command             => "/opt/synplicity/T-2022.09-SP2/bin/synplify_premier_dp",
 
 nodelist_file                => "../nodelist_hades69.txt",
 pinout_file                  => 'dirich5s',

diff --git a/dirich5s/dirich5s.prj b/dirich5s/dirich5s.prj
index 0f11128765fdab3dc426cb6f7c47dc2f09f936f5..52dc5946aca5d7db1b54ecdfcc0fbd5fda02c7c2 100644 (file)
--- a/dirich5s/dirich5s.prj
+++ b/dirich5s/dirich5s.prj
@@ -46,6 +46,7 @@ set_option log_file "workdir/dirich5s_project.srf"
 #implementation attributes
 
 set_option -vlog_std v2001
+set_option -vhdl2008 1
 set_option -project_relative_includes 1
 impl -active "workdir"
 
@@ -96,6 +97,9 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16
 add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
 
+add_file -vhdl -lib work "../../trbnet/special/i2c_slim2.vhd"
+add_file -vhdl -lib work "../../trbnet/special/i2c_gstart2.vhd"
+add_file -vhdl -lib work "../../trbnet/special/i2c_sendb2.vhd"
 
 #Flash & Reload, Tools
 add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
@@ -127,8 +131,10 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
@@ -216,7 +222,7 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.vhd"
 #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd"
 #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.vhd"
 
 
 ### Triggering

diff --git a/dirich5s/dirich5s.vhd b/dirich5s/dirich5s.vhd
index 085878ef139c9714f67958391899a7e2f4638b31..e070043448a0bf3639e371ca77000cfc873149e3 100644 (file)
--- a/dirich5s/dirich5s.vhd
+++ b/dirich5s/dirich5s.vhd
@@ -12,7 +12,7 @@ use work.med_sync_define.all;
 
 entity dirich5s is
   port(
-    CLOCK_CORE  : in std_logic;           --Main Oscillator
+    CLOCK_IN    : in std_logic;           --Main Oscillator, on_board oscillator
     TRIG_IN     : in std_logic;           --Reference Time
     CLOCK_CAL   : in std_logic;           --on-board calibration oscillator
     
@@ -47,6 +47,9 @@ entity dirich5s is
     PROGRAMN   : out   std_logic;
     TEMP_LINE  : inout std_logic;
     
+    SFP_MOD1   : inout std_logic;
+    SFP_MOD2   : inout std_logic;
+
     MISO_IN    : in    std_logic_vector(1 downto 0);
     MOSI_OUT   : out   std_logic_vector(1 downto 0);
     SCLK_OUT   : out   std_logic_vector(1 downto 0);
@@ -117,7 +120,6 @@ architecture dirich5s_arch of dirich5s is
   
   signal link_stat_in_reg : std_logic;
 
-
   component usrmclk
     port(
       USRMCLKI  : in std_ulogic;
@@ -135,7 +137,7 @@ begin
 ---------------------------------------------------------------------------
   THE_CLOCK_RESET : entity work.clock_reset_handler
     port map(
-      CLOCK_IN       => CLOCK_CORE,
+      CLOCK_IN       => CLOCK_IN,
       RESET_FROM_NET => med2int(0).stat_op(13),
       SEND_RESET_IN  => med2int(0).stat_op(15),
 
@@ -211,8 +213,11 @@ THE_CAL_PLL : entity work.pll_in200_out50
       CTRL_DEBUG    => open
       );
 
-  SIG(2)       <= '1' when link_stat_out = '1' else '0';
-  link_stat_in <= '0';--SIG(1);
+  SIG(2)       <= '1' when link_stat_out = '1' else '0'; -- SD_TXDIR_OUT
+--                                                         -- on pin SIG2, N5
+--    SIG(2)       <= '0'; -- when link_stat_out = '1' else '0'; -- SD_TXDIR_OUT on
+
+  link_stat_in <= '0'; --SIG(1); -- not available for SFF
 
 ---------------------------------------------------------------------------
 -- Endpoint
@@ -334,6 +339,9 @@ THE_CAL_PLL : entity work.pll_in200_out50
       TRIG_GEN_OUTPUTS  => SIG(4 downto 3),
       --SED
       SED_ERROR_OUT     => sed_error_i,
+      --I2C
+      SDA_INOUT         => SFP_MOD2,
+      SCL_INOUT         => SFP_MOD1,
       --Slowcontrol
       BUS_RX            => bustools_rx,
       BUS_TX            => bustools_tx,
@@ -383,7 +391,6 @@ port map (
 -- I/O
 ---------------------------------------------------------------------------
 
-
 --Debug UART
   --hdr_io(8)               <= TEST_LINE(1);
   --TEST_LINE(2)           <= hdr_io(9);
@@ -398,18 +405,29 @@ port map (
 --TEST_LINE(8 downto 1) <= clk_sys &  med_stat_debug(9) & med_stat_debug(10) &   med_stat_debug(11) & clear_i & reset_i & link_stat_out & link_stat_in_reg;
 --  TEST_LINE(8 downto 3) <= clear_i & reset_i & link_stat_out & link_stat_in_reg & debug_clock_reset(0) & med_stat_debug(4);-- & med_stat_debug(5) & med_stat_debug(6);
 
-  TEST_LINE(1) <= time_counter(0);
-  TEST_LINE(2) <= time_counter(1);
-  TEST_LINE(3) <= time_counter(2);
+
+  
+  TEST_LINE(1) <= med_stat_debug(15); -- RX_CV_ERROR, same as rx_error
+  TEST_LINE(2) <= med_stat_debug(2); -- RX_LOS
+  TEST_LINE(3) <= med_stat_debug(13); -- RX_LSM
+  TEST_LINE(4) <= med_stat_debug(14); -- CDR_LOL
+--  TEST_LINE(8 downto 5) <= med_stat_debug(19 downto 16); -- rx_fsm_state
+
+
+
+  
+--    TEST_LINE(1) <= med_stat_debug(10); -- finished_reset_tx
+--  TEST_LINE(5) <= med_stat_debug(15); -- RX_CV_ERROR, same as rx_error
+--  TEST_LINE(6) <= med_stat_debug(9); -- finished_reset_rx
   
-  TEST_LINE(4) <= not med2int(0).stat_op(9) or led_off;                               --LED_GREEN
-  TEST_LINE(5) <= debug_clock_reset(0) or led_off;                                    --LED_ORANGE
-  TEST_LINE(6) <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;  --LED_RED
-  TEST_LINE(7) <= not med2int(0).stat_op(8) or led_off;                               --LED_YELLOW
-  TEST_LINE(8) <= reset_i;
-  TEST_LINE(9) <= int2med(0).ctrl_op(15);  -- SEND_LINK_RESET_IN
-  TEST_LINE(10) <= int2med(0).dataready;   -- To SFP
-  TEST_LINE(11) <= med2int(0).dataready;   -- from SFP
+--  TEST_LINE(4) <= not med2int(0).stat_op(9) or led_off;                               --LED_GREEN
+--  TEST_LINE(5) <= debug_clock_reset(0) or led_off;                                    --LED_ORANGE
+--  TEST_LINE(6) <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;  --LED_RED
+--  TEST_LINE(7) <= not med2int(0).stat_op(8) or led_off;                               --LED_YELLOW
+--  TEST_LINE(8) <= reset_i;
+--  TEST_LINE(9) <= int2med(0).ctrl_op(15);  -- SEND_LINK_RESET_IN
+--  TEST_LINE(10) <= int2med(0).dataready;   -- To SFP
+--  TEST_LINE(11) <= med2int(0).dataready;   -- from SFP
 
   SIG(5) <= '1';
 
@@ -448,7 +466,7 @@ port map (
       SIMULATION     => c_NO)
     port map (
       RESET              => reset_i,
-      CLK_TDC            => CLOCK_CORE,
+      CLK_TDC            => CLOCK_IN,
       CLK_READOUT        => clk_sys,    -- Clock for the readout
       REFERENCE_TIME     => TRIG_IN,    -- Reference time input
       HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals

diff --git a/dirich5s/nodelist_hades69.txt b/dirich5s/nodelist_hades69.txt
index 44b6ae05e2ac867ec3a18bbaaa4fc3ee92d84787..3e2ff5b6bdca59ffadd679ea0851e50f0bef0348 100644 (file)
--- a/dirich5s/nodelist_hades69.txt
+++ b/dirich5s/nodelist_hades69.txt
@@ -2,6 +2,6 @@
 
 [localhost]
 SYSTEM = linux
-CORENUM = 12
+CORENUM = 24
 ENV = /home/hadaq/bin/diamond_env
-WORKDIR = /home/hadaq/vhdl/dirich/dirich5s/workdir
+WORKDIR = /home/hadaq/vhdl_new_serdes_reset/dirich/dirich5s/workdir

diff --git a/dirich5s/par.p2t b/dirich5s/par.p2t
index fae8f59d395b42e06b53c758fd5d29ee2ab3a02a..02a58675064ac21687b739eecd972ae0dca2be58 100644 (file)
--- a/dirich5s/par.p2t
+++ b/dirich5s/par.p2t
@@ -4,8 +4,7 @@
 #-m nodelist.txt       # Controlled by the compile.pl script.
 #-n 2                          # Controlled by the compile.pl script.
 -s 10
-#-t 96
--t 60
+-t 1
 -c 2
 -e 2
 -i 10

diff --git a/pinout/dirich5s.lpf b/pinout/dirich5s.lpf
index 583fff7cfba9ad62ae9e2d06732100a4574e2297..cc7a4f5fc0154e49c1bedd251a828a8e66105fd1 100644 (file)
--- a/pinout/dirich5s.lpf
+++ b/pinout/dirich5s.lpf
@@ -43,7 +43,7 @@ LOCATE COMP "INPUT[32]" SITE "U18";
 DEFINE PORT GROUP "INP_group" "INP*" ;
 IOBUF GROUP  "INP_group" IO_TYPE=LVDS  DIFFRESISTOR=OFF BANK_VCCIO=2.5;
 
-LOCATE COMP "CLOCK_CORE"     SITE "J19";
+LOCATE COMP "CLOCK_IN"       SITE "J19";  # This signal is called CLOCK_CORE in the schematics
 LOCATE COMP "CLOCK_CAL"      SITE "J20";
 
 LOCATE COMP "CLOCK_OUT"      SITE "K2";
@@ -139,6 +139,10 @@ LOCATE COMP "SCLK_OUT[0]"         SITE "E6";    #DAC1_CTRL2
 LOCATE COMP "SCLK_OUT[1]"         SITE "B19";   #DAC2_CTRL2
 LOCATE COMP "CS_OUT[0]"           SITE "D6";    #DAC1_CTRL3
 LOCATE COMP "CS_OUT[1]"           SITE "B18";   #DAC2_CTRL3
+
+LOCATE COMP "SFP_MOD1"           SITE "H1";     # SFP I2C SCL
+LOCATE COMP "SFP_MOD2"           SITE "K1";      # SFP I2C SDA
+
 IOBUF PORT "MISO_IN[0]" IO_TYPE=LVCMOS25 PULLMODE=UP;
 IOBUF PORT "MOSI_OUT[0]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
 IOBUF PORT "SCLK_OUT[0]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;