fibres (typically 2~m per clock cycle).
Independent of the origin, signals that are out of phase can manually be synchronised by delay lines. In an
- input module, a delay line is built from a 15~bit shift register and a multiplexer used to select the required
+ input module, a delay line is built from a 15~bit (64~bit since 2020-06-15) shift register and a multiplexer used to select the required
delay.
\subsubsection{AddOn Input module}
Currently, CBM-MBS is supported.
\item \textbf{Up to 16 independent trigger modules} to implement complex behaviour.
\item \textbf{8 general purpose trigger inputs} with independent spike rejection and delay lines.
- \item \textbf{4 channel TDC} to determine the trigger time with a resolution of 20~ps.
+ \item \textbf{32 channel TDC} to determine the trigger time with a resolution of 20~ps or to allow a stand-alone readout-system (Trb3sc only).
\item \textbf{MBS master} Sends out a MBS trigger word for each trigger on a serial LVDS line parallel to a 50 MHz clock
\item \textbf{Run-time configurable periodical and random pulsers modules}. The mCTS supports regular and (pseudo-)random
pulsers to produce trigger decisions with an (average) interval of 10~ns to 40~s.
edge and/or level-sensitive.
\item \textbf{Generic counters, scalers and debugging features} accessible via slow-control and embeddable into the
data stream to the event builder.
-\end{itemize*}
\ No newline at end of file
+\end{itemize*}
\hline
\textbf{TriggerWindowConfig}\hfill(rw) & c801 & & Configuration of the TriggerWindow feature \\
\quad TriggerWindowBefore & & 0--10 & Trigger window width BEFORE the trigger with granularity of 5 ns \\
- \quad TriggerWindowAfter & & 16--26 & Trigger window width AFTER the trigger with granularity of 5 ns. ATTENTION: Minimum value is x"00f"! \\
+ \quad TriggerWindowAfter & & 16--26 & Trigger window width AFTER the trigger with granularity of 5 ns. The post-trigger window can be set to negative values. The 11 Bit wide register allows values from -1023 to 1023, corresponding to times -5115 ns to +5115 ns. Values between 0 and 10 are not permitted. \\
\quad TriggerWindowEnable & & 31 & Trigger window enable \\
\hline
\textbf{ChannelEnable.0}\hfill(rw) & c802 & 0--31 & Enable signals/hits of the specific channel. LSB is channel 1. \\
\label{sec:tdcTrigWin}
In order to reduce the data load on the DAQ a feature called trigger window is
-implemented. With this feature the user can define the interested time
-interval and filter the hits occurred in this time interval. An illustration
+implemented. With this feature the user can define the time
+interval of interest and filter the hits that occurred in this time interval. An illustration
of the trigger window feature is shown in Figure \ref{fig:tdcTrigWin}. The
trigger window is relative to the rising edge of the reference time at the
-\textit{TRIGGER\_INP1} (see Figure \ref{fig:trb3}) with the granularity of
+\textit{TRIGGER\_IN} (see Table \ref{tab:trb3_central_rj45_connections}) with the granularity of
5~ns. The \textit{Pre-Trigger Window} and \textit{Post-Trigger Window} widths
-can be set via slow control (Table \ref{tab:tdcControlReg}).
+can be set via slow control (Table \ref{tab:tdcControlReg}, Registers TriggerWindowBefore and TriggerWindowAfter).
\begin{information}
For the post-trigger window the values 0x0 to 0xa are not allowed.
\begin{information}
For TDC versions starting from 2.4:
-The post-trigger window can be set to negative values. The 11 Bit wide register allows values from -1023 to 1023, corresponding to times -5115 ns to +5115 ns. The post-trigger setting must be later than the pre-trigger setting - i.e. the post-value has to be smaller than the pre-value.
+The post-trigger window can be set to negative values. The 11 Bit wide register allows values from -1023 to 1023, corresponding to times -5115 ns to +5115 ns. Values between 0 and 10 are not permitted.
+The post-trigger setting must be later than the pre-trigger setting.
\end{information}
\begin{figure}[htp]
The VHDL code is available in \files{trb3/base/code/input\_to\_trigger\_logic\_record.vhd}
\paragraph*{Setup}
-The trigger module can feature up to 96 input signals and up to 16 independent outputs.
+The trigger module can feature up to 96 input signals and up to 8 independent outputs.
For each output, any of the connected inputs can be enabled or disabled as well as been inverted
individually. The output is an 'or' of all enabled inputs. The peripheral FPGA can send four
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