signal rx_fsm_state : std_logic_vector(3 downto 0);
signal tx_fsm_state : std_logic_vector(3 downto 0);
signal wa_position_rx : std_logic_vector(3 downto 0);
-signal start_timer : unsigned(11 downto 0) := (others => '0'); --FIXME SIMULATION 20
+signal start_timer : unsigned(20 downto 0) := (others => '0'); --REAL
+--signal start_timer : unsigned(11 downto 0) := (others => '0'); --SIM
+
signal request_retr_i : std_logic;
signal start_retr_i : std_logic;
TX_ALLOW_IN => tx_allow,
RX_ALLOW_IN => rx_allow,
+ ENABLE_SEND_CHKSUM => '1',
+ -- ENABLE_SEND_CHKSUM => MEDIA_INT2MED.ctrl_op(8),
+
DEBUG_OUT => DEBUG_TX_CONTROL,
STAT_REG_OUT => STAT_TX_CONTROL
);
TX_ALLOW_IN : in std_logic := '0';
RX_ALLOW_IN : in std_logic := '0';
+ ENABLE_SEND_CHKSUM : in std_logic;
+
DEBUG_OUT : out std_logic_vector(31 downto 0);
STAT_REG_OUT : out std_logic_vector(31 downto 0)
);
signal good_pos_counter : unsigned(7 downto 0) := (others => '0');
signal num_pakets : unsigned(3 downto 0) := (others => '0');
+signal use_crc : std_logic := '0';
+
begin
----------------------------------------------------------------------
----------------------------------------------------------------------
-ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty and (pulse_good_100 or got_pulse_good or pulse_bad_100 or got_pulse_bad); -- when rising_edge(CLK_100);
-buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty and (pulse_good_100 or got_pulse_good) and not (pulse_bad_100 or got_pulse_bad) when rising_edge(CLK_100);
+ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty and (pulse_good_100 or got_pulse_good or pulse_bad_100 or got_pulse_bad or not use_crc); -- when rising_edge(CLK_100);
+--ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty;
+buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty and (((pulse_good_100 or got_pulse_good) and not (pulse_bad_100 or got_pulse_bad)) or not use_crc)
+ when rising_edge(CLK_100);
+--buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty when rising_edge(CLK_100);
RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ;
RX_WRITE_OUT <= buf_rx_write_out;
when FIRST =>
rx_state_bits <= x"2";
- rx_data(7 downto 0) <= reg_rx_data_in;
+ rx_data(7 downto 0) <= reg_rx_data_in;
if reg_rx_k_in = '1' then
case reg_rx_data_in is
when K_IDLE =>
rx_state <= SLEEP;
end if;
- when GET_CRC => --TODO: mitzaehlen, of CRC nach 5 16-Bit-Paketen kommt
- crc_reset <= '1';
- rx_state <= FIRST;
- if (crc_q = reg_rx_data_in and waiting_for_retr = '0' and num_pakets = 5) then -- CRC match
+ when GET_CRC =>
+ if (use_crc = '0') then
+ -- first time
+ use_crc <= '1';
pulse_good <= '1';
- else
- pulse_bad <= '1';
- if waiting_for_retr = '0' then
- req_retr_i <= '1';
- waiting_for_retr <= '1';
+ else
+ if (crc_q = reg_rx_data_in and waiting_for_retr = '0' and num_pakets = 5) then -- CRC match
+ pulse_good <= '1';
+ else
+ pulse_bad <= '1';
+ if waiting_for_retr = '0' then
+ req_retr_i <= '1';
+ waiting_for_retr <= '1';
+ end if;
end if;
end if;
+ crc_reset <= '1';
+ rx_state <= FIRST;
num_pakets <= (others => '0');
when GET_RETR =>
----------------------------------------------------------------------
GOT_LINK_READY <= got_link_ready_i;
---START_RETRANSMIT_OUT <= start_retr_i when rising_edge(CLK_200);
START_RETRANSMIT_OUT_SYNC : pulse_sync
port map(
CLK_A_IN => CLK_200,
RX_DLM <= rx_dlm_i when rising_edge(CLK_200);
RX_DLM_WORD <= rx_dlm_word_i when rising_edge(CLK_200);
---REQUEST_RETRANSMIT_OUT <= req_retr_i when rising_edge(CLK_200); -- '0'; --TODO: check incoming data
REQUEST_RETRANSMIT_OUT_SYNC : pulse_sync
port map(
CLK_A_IN => CLK_200,
architecture rx_reset_fsm_arch of rx_reset_fsm is
-constant count_index : integer := 9; --FIXME SIMULATION 19
+constant count_index : integer := 19; --REAL
+--constant count_index : integer := 9; --SIM
type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_timer1, CHECK_LOL_LOS, WAIT_FOR_timer2, NORMAL);
signal cs: statetype; -- current state of lsm
TX_ALLOW_IN : in std_logic := '0';
RX_ALLOW_IN : in std_logic := '0';
+ ENABLE_SEND_CHKSUM : in std_logic;
+
DEBUG_OUT : out std_logic_vector(31 downto 0);
STAT_REG_OUT : out std_logic_vector(31 downto 0)
);
signal crc_en : std_logic;
signal crc_data : std_logic_vector(7 downto 0);
signal first_idle : std_logic;
- signal toggle_idle : std_logic;
+ signal toggle_idle : std_logic := '0';
+
+ -- signal ENABLE_SEND_CHKSUM : std_logic := '0';
begin
----------------------------------------------------------------------
TX_DATA_OUT <= ram_dout(7 downto 0);
load_sop <= ram_dout(16);
load_eop <= ram_dout(17);
+ if ENABLE_SEND_CHKSUM = '0' then
+ load_eop <= '0';
+ end if;
current_state <= SEND_DATA_H;
when SEND_DATA_H =>
when SEND_CHKSUM_H =>
TX_DATA_OUT <= crc_q;
-
+
when SEND_START_L =>
TX_DATA_OUT <= K_BGN;
TX_K_OUT <= '1';
when SEND_START_H =>
--TX_DATA_OUT <= std_logic_vector(ram_read_addr);
- TX_DATA_OUT <= x"FF";
- current_state <= SEND_DATA_L;
+ TX_DATA_OUT <= x"FF"; --
+ current_state <= SEND_DATA_L; ---
when SEND_REQUEST_L =>
TX_DATA_OUT <= K_REQ;
when others =>
current_state <= SEND_IDLE_L;
end case;
-
+
if current_state = SEND_START_H or
current_state = SEND_IDLE_H or
current_state = SEND_DATA_H or
-- load_read_pointer_i <= '1';
elsif send_dlm_i = '1' then
current_state <= SEND_DLM_L;
- elsif (load_eop = '1') then
+ elsif load_eop = '1' then
current_state <= SEND_CHKSUM_L;
elsif ram_empty = '0' then
-- ram_read <= '1';
if (current_state = SEND_START_H or current_state = SEND_IDLE_H or current_state = SEND_DATA_H or
current_state = SEND_DLM_H or current_state = SEND_REQUEST_H or current_state = SEND_CHKSUM_H)
and ram_empty = '0' and tx_allow_qtx = '1' and send_link_reset_qtx = '0'
- and make_request_i = '0' and make_restart_i = '0' and send_dlm_i = '0' and load_eop = '0' then --TODO: Sync these 3 signals
+ and make_request_i = '0' and make_restart_i = '0' and send_dlm_i = '0' and load_eop = '0' then --TODO: Sync these 3 signals
ram_read <= '1';
else
ram_read <= '0';
architecture tx_reset_fsm_arch of tx_reset_fsm is
-constant count_index : integer := 9; --FIXME SIMULATION 19
+constant count_index : integer := 19; --REAL
+--constant count_index : integer := 9; --SIM
type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
signal cs: statetype; -- current state of lsm
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