case (only one TRB3) is the same FPGA as the CTS is running in. There the data
is collected from all 4 peripheral FPGAs and then combined to a UDP-frame,
which is then sent via many Ethernet-packets to the Eventbuilder.
+
+A similar scheme is implemented in a Trb3sc/Trb5sc crate system: One central
+"master" FPGA board is surrounded by up to 9 "slave" modules.
+
The Eventbuilder-PC linux is combining the packets to a UDP-frames which then
-goes to the eventbuilder process (dabc), which combines many sources (in your
-case only one source) to coherent events via the unique event-numbers the CTS
+goes to the eventbuilder process (dabc), which combines many sources
+to coherent events via the unique event-numbers the CTS
has generated in the first place.
The Evenbuilder can be on any computer in the same network (we use directly
the MAC). For small setups this can be the same computer you run the slow
\subsection{Hardware Information}
-\begin{itemize*}
- \item TRB3 \href{http://jspc29.x-matter.uni-frankfurt.de/trbweb/?action=page&url=schematics}{Schematics}
- \item Pin-out file for all FPGAs vary based on the AddOns in use and can be found in the git repositories, \verb!pinout/*.lpf!.
-\end{itemize*}
+Schematics of all boards can be found here:
+ \href{http://jspc29.x-matter.uni-frankfurt.de/trbweb/?action=page&url=schematics}{Schematics}
\subsection{Board Identification}
image!
\end{warning}
-\subsection{Design Identification}
-\label{sec:Identification}
-The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (register 0x42) that has to be set according to the following rules:
-The upper 16 Bit are used by the software to identify the hardware before programming the Flash to prevent loading invalid designs and have to contain one of the following values. The last digit should be used to denote the hardware revision.
-\begin{description*}
- \item[9000] design for Trb3 central FPGA, \verb!trb3_central!
- \item[9100] design for Trb3 peripheral FPGAs, \verb!trb3_periph!
- \item[9200] design for CBM Rich, \verb!cbm_rich!
- \item[9300] design for CBM Tof, \verb!cbm_tof!
- \item[9500] design for Trb3sc, \verb!trb3sc!
- \item[9600] design for DiRich, \verb!dirich!
- \item[9700] design for DiRich Combiner module, \verb!combiner!
- \item[9900] design for Munich Skyroc boards
- \item[9A00] design for DiRICH5s, \verb!dirich5s!
- \item[9B00] design for FaRICH1, \verb!farich!
- \item[9C00] design for DiRICH1, \verb!dirich!
- \item[A500] design for TRB5sc, \verb!trb5sc!
- \item[A600] design for MDC central, \verb!mdcoep!
- \item[A700] design for MDC TDC, \verb!mdctdc!
- \item[A800] design for TOMcat, \verb!tomcat!
-\end{description*}
+\subsection{Network Addresses and Data Unpacker}
+\label{Data_Unpacking}
-The lower 16 Bit are used to identify the contents of the design and the AddOn boards they should be used with. Combine
-as many values as you like by logical or.
-Please note that these values have been partly superseded by the IncludedFeatures register described below. This
-register should only be used to describe hardware-related features, like the needed AddOn Board.
+For proper automatic detection of data in software, the 16bit network addresses in a TRB set-up should have their first hex digit representing their function: 'C' for the CTS, '8' for a hub, '0' or '1' for TDCs.
-\begin{description*}
-\item[Trb3 central]~
-\begin{description*}
- \item[cXX0] contains a CTS
- \item[cXX1] contains a CTS, use with AddOn for trigger signals
-\end{description*}
-\item[Trb3 peripheral, Trb3sc]~
-\begin{description*}
- \item[0XXX] use with ADA adapter board AddOn version 1
- \item[1XXX] use with ADA adapter board AddOn version 2
- \item[2XXX] use with multi-purpose test AddOn
- \item[3XXX] use with SFP hub AddOn
- \item[4XXX] use with Padiwa adapter AddOn
- \item[5XXX] use with General Purpose AddOn - with NIM connectors
- \item[6XXX] use with Nxyter
- \item[7XXX] use with 32PinAddOn
- \item[9XXX] use with ADC AddOn
- \item[AXXX] use with SFP AddOn v2
- \item[BXXX] onboard connectors
- \item[XX9X] for MVD converter board 2013
-\end{description*}
+The middle two digits are often chosen to equal the serial number of the board while the last digit enumerates the FPGAs on one board / one crate. Another typical scheme is to encode the position of the board in the detector (e.g. station / sector / subgroup). Chose whatever fits your needs.
+
+These network addresses also show up in the event data in the form of SubEvent-IDs and SubSubEvent-IDs.
+SubSubEvent-IDs are identical to the network address of each board, e.g. the TDCs. The SubEvent-IDs identify one subsystem and should be equal to the network address of the FPGA sending the data on Ethernet (e.g. central FPGA on Trb3 or master FPGA in a crate). The SubEvent-IDs must be configured manually together with all other Ethernet-related settings, they are not set automatically.
+
+On the software side, the first digit of each SubSubEvent-ID should be sufficient to determine
+how the following data has to be handled:
-\item[Trb5sc]~
\begin{description*}
- \item[1000] use with ADA adapter (80pin KEL)
- \item[2000] use with 4conn adapter (40 pin KEL)
- \item[4000] use with RJ45 adapter
- \item[0100] use with HDMI adapter
-\end{description*}
+\item[0..1] Unpack as TDC data
+\item[5555](fixed) The only SubSubEvent-ID starting with 5 is 5555 at the end of each SubEvent, marking the beginning of the status information word for this SubEvent .
+\item[7] Special TDCs (like beam detectors, not part of the system under test)
+\item[8] Skip this SubSubEvent-Header. Note: Only the header, the next word should be another valid SubSubEvent-Header.
+\item[C] Unpack as CTS data
+\item[D..E] Other read-out formats, no TDC data included
\end{description*}
-\subsection{Included Features}
-Basic Information about included features should be put to a generic setting named IncludedFeatures. This should be set
-in the config.vhd file of each project according to the following table. The values are available from registers 0x41
-(lower 32 Bit) and 0x43 (upper 32 Bit) on TrbNet. The uppermost 8 Bit define a set of definitions that defines the
-meaning of the remaining 56 Bit in the word.
+The data format is shown in later sections.
+Note that these groups are only default suggestions. You can chose arbitrary ranges, but these need to be configured manually in the unpacking software.
-Fields marked as ``version'' should be increased after any bigger change in the design or major bug fixes.
-\begin{center}
- \LTXtable{\textwidth}{IncludedFeaturesTable}
-\end{center}
-\subsection{Network Addresses}
-For proper automatic detection of data in software, the network addresses in a TRB set-up need to have their first hex digit representing their function: 'C' for the CTS, '8' for a hub, '0' or '1' for TDCs. See \ref{Data_Unpacking}.
+\section{Design and Board Identification}
+\subsection{Design Features}
+All FPGA can be loaded with a multitude of different design files and may contain any subset of available features. There are two main starting points to get information about the design contents:
+
+First, the design file name. The file name currently loaded to an FPGA can be read using the \verb!trbflash info! command.
+Second, the "Network Map" page on the web server. Hover your pointer over any field in the table to get additional information!
-The middle two digits are often chosen to equal the serial number of the board while the last digit enumerates the FPGAs on one board / one crate.
+\subsection{Default Network Addresses}
+
All boards of a given type are accessible by a broadcast address (0xFE\_\_) at the same time. This is set by \signal{Broadcast\_Special\_Addr} in the TrbNet endpoint:
\end{itemize*}
-\subsection{Testing Procedure for New Trb3 Boards}
-\begin{itemize*}
- \item Visual Inspection
- \item Add sticker with serial number
- \item Power-up - current should be around 0.25A at 48V
- \item Check if fixes (Flash 0R) are done
- \item Load set of configuration files (no Flash programming for FPGAs, only load design)
- \item Also note that you need to issue an \verb!trbcmd reset! after JTAG programming in order to have the FPGAs obtain the correct local number identification reported by an info trbcmd broadcast (5 for central, 0-3 for peripheral FPGAs).
- \item Check basic TrbNet functionality
- \item Program Flash ROMs via TrbNet
- \item Reboot Board to see if all FPGA boot from Flash
- \item Add the five unique IDs to the \files{serials\_trb3.db} in the cvs (see \ref{Trb3BoardID})
- \item Add board as tested to wiki page
-\end{itemize*}
+\subsection{Hardware Types}
+\label{sec:Identification}
+\begin{information}Section mainly for developers. Users can find this information decoded in the Network Map on the web server\end{information}
+The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (register 0x42) that has to be set according to the following rules:
+The upper 16 Bit are used by the software to identify the hardware before programming the Flash to prevent loading invalid designs and have to contain one of the following values. The last digit should be used to denote the hardware revision.
+\begin{description*}
+ \item[9000] design for Trb3 central FPGA, \verb!trb3_central!
+ \item[9100] design for Trb3 peripheral FPGAs, \verb!trb3_periph!
+ \item[9200] design for CBM Rich, \verb!cbm_rich!
+ \item[9300] design for CBM Tof, \verb!cbm_tof!
+ \item[9500] design for Trb3sc, \verb!trb3sc!
+ \item[9600] design for DiRich, \verb!dirich!
+ \item[9700] design for DiRich Combiner module, \verb!combiner!
+ \item[9900] design for Munich Skyroc boards
+ \item[9A00] design for DiRICH5s, \verb!dirich5s!
+ \item[9B00] design for FaRICH1, \verb!farich!
+ \item[9C00] design for DiRICH1, \verb!dirich!
-\subsection{JTAG}
-Since programming of FPGAs can be done via GbE, the JTAG connector is usually not used. In case of corrupted designs it provides the only access to reconfigure FPGAs. Loading a design directly to the FPGA is quite fast (25 s) but loading it to the Flash ROM is deadly slow (5 minutes) - better: first load the design to the FPGA via JTAG, then flash it using TrbNet.
+ \item[A500] design for TRB5sc, \verb!trb5sc!
+ \item[A600] design for MDC central, \verb!mdcoep!
+ \item[A700] design for MDC TDC, \verb!mdctdc!
+ \item[A800] design for TOMcat, \verb!tomcat!
+\end{description*}
+
+The lower 16 Bit are used to identify the contents of the design and the AddOn boards they should be used with. Combine
+as many values as you like by logical or.
+Please note that these values have been partly superseded by the IncludedFeatures register described below. This
+register should only be used to describe hardware-related features, like the needed AddOn Board.
+
+\begin{description*}
+\item[Trb3 central]~
+\begin{description*}
+ \item[cXX0] contains a CTS
+ \item[cXX1] contains a CTS, use with AddOn for trigger signals
+\end{description*}
+\item[Trb3 peripheral, Trb3sc]~
+\begin{description*}
+ \item[0XXX] use with ADA adapter board AddOn version 1
+ \item[1XXX] use with ADA adapter board AddOn version 2
+ \item[2XXX] use with multi-purpose test AddOn
+ \item[3XXX] use with SFP hub AddOn
+ \item[4XXX] use with Padiwa adapter AddOn
+ \item[5XXX] use with General Purpose AddOn - with NIM connectors
+ \item[6XXX] use with Nxyter
+ \item[7XXX] use with 32PinAddOn
+ \item[9XXX] use with ADC AddOn
+ \item[AXXX] use with SFP AddOn v2
+ \item[BXXX] onboard connectors
+ \item[XX9X] for MVD converter board 2013
+\end{description*}
-The pin-out of the JTAG connector on TRB3 (1x8 pin-header near the power supply):
+\item[Trb5sc]~
\begin{description*}
- \item[1] VCC (3.3V, red)
- \item[2] TMS (violet)
- \item[3] TCK (white)
- \item[4] TDI (orange)
- \item[5] TDO (brown)
- \item[6] GND (black)
- \item[7] GND (n/c)
- \item[8] GND (n/c)
+ \item[1000] use with ADA adapter (80pin KEL)
+ \item[2000] use with 4conn adapter (40 pin KEL)
+ \item[4000] use with RJ45 adapter
+ \item[0100] use with HDMI adapter
+\end{description*}
\end{description*}
-Pin 1 is next to the 2x6 pin-header. Note that TDO and TDI are switched compared to the layout on all other boards.
+\subsection{Included Features}
+\begin{information}Section mainly for developers. Users can find this information decoded in the Network Map on the web server\end{information}
+Basic Information about included features should be put to a generic setting named IncludedFeatures. This should be set
+in the config.vhd file of each project according to the following table. The values are available from registers 0x41
+(lower 32 Bit) and 0x43 (upper 32 Bit) on TrbNet. The uppermost 8 Bit define a set of definitions that defines the
+meaning of the remaining 56 Bit in the word.
+
+Fields marked as ``version'' should be increased after any bigger change in the design or major bug fixes.
+
+\begin{center}
+ \LTXtable{\textwidth}{IncludedFeaturesTable}
+\end{center}
+
+\subsection{JTAG}
+Since programming of FPGAs can be done via GbE, the JTAG connector is usually not used. In case of corrupted designs it provides the only access to reconfigure FPGAs. Loading a design directly to the FPGA is quite fast (25 s) but loading it to the Flash ROM is deadly slow (5 minutes) - better: first load the design to the FPGA via JTAG, then flash it using TrbNet.
If you experience strange behaviour of the programming procedure and think you might have destroyed the cable: It's most likely a software issue - reboot your PC!
+
Note that the programming cable can only be used as root by default in most Linux flavours. You can either change permissions on the device in /dev/ by hand or put this (as one line!)
\\\verb!SUBSYSTEMS=="usb", ATTRS{idVendor}=="1134", SYMLINK+="lattice_cable",!
\\\verb!GROUP="users", MODE="0666"'!
\\\verb!echo $RESULT:1.0 >/sys/bus/usb/drivers/ftdi_sio/unbind"!
\\into \files{/etc/udev/rules.d/91-usb-hardware.rules}
-
-
-\subsection{Data Unpacker}
-\label{Data_Unpacking}
-The data stream contains SubEvent-IDs and SubSubEvent-IDs to identify the sender
-of each block of data. While SubSubEvent-IDs are equal to the network address of
-the corresponding board by design, the SubEvent-IDs can be chosen freely, but are
-defined to be equal to the network address of the board sending the SubEvent via
-Gigabit Ethernet. The first digit of each SubSubEvent-ID is sufficient to determine
-how the following data has to be handled:
-\begin{description*}
-\item[0..1] Unpack as TDC data
-\item[5555] The only SubSubEvent-ID starting with 5 is 5555 at the end of each SubEvent, marking the beginning of the status information word for this SubEvent.
-\item[7] Special TDCs (like beam detectors, not part of the system under test)
-\item[8] Skip this SubSubEvent-Header. Note: Only the header, the next word should be another valid SubSubEvent-Header.
-\item[C] Unpack as CTS data
-\item[D..E] Other read-out formats, no TDC data included
-\end{description*}
-The data format is shown in later sections.
-
-
-\subsection{TRB3 Trigger \& Clock Input}
-Both trigger and clock input (RJ-45 connectors) are equipped with a configurable fan-out chip. Its control signals can be set in slow-control register 0xd300 (currently in CTS only, but should also be present in other central FPGA).
-\begin{description*}
- \item[Bit 0] Trigger select (local signal: 1, external signal: 0
- \item[Bit 8] Clock select (Input 0 or 1)
- \item[Bit 19 -- 16] 4 User signals on trigger fan-out
- \item[Bit 27 -- 24] 4 User signals on clock fan-out
-\end{description*}
-
-\subsection{TRB3 Power Consumption}
-The TRB3 with linear supplies and typical TDC designs needs
-\begin{itemize*}
-\item 3.3V - 1.25A
-\item 2.5V - 0.5A
-\item 1.2V - 8A
-\end{itemize*}
-
-
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-%%% mode: latex
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