*** empty log message ***

diff --git a/cts.tex b/cts.tex
index a061614ca073bc19ddadc4c845786790c30bc1eb..2039a911c7a9f2c6ef9d137a7015a7c603c78d56 100644 (file)
--- a/cts.tex
+++ b/cts.tex
@@ -26,8 +26,8 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
   \item [0xA0C1] LVL1/LVL2 trigger settings:
     \begin{description}
      \item[Bit 7 -- 0] How many lvl1 events wait to send lvl2 trigger
-     \item[Bit 16 -- 12] Delay (to the fastes trigger) of MDCB trigger = value * 20 ns 
-     \item[Bit 21 -- 17] Delay of MDCA trigger = value * 20 ns 
+     \item[Bit 16 -- 12] Delay (to the fastes trigger) of MDCB (MDC 3/4) trigger = value * 20 ns 
+     \item[Bit 21 -- 17] Delay of MDCA (MDC 1/2) trigger = value * 20 ns 
      \item[Bit 31 -- 28] LVL1 trigger width, when value < 7 then width = 105 + Value*5 ns else width = Value*5ns
     \end{description}
   \item [0xA0C2] Multiplexers output select:

diff --git a/ebsetup.tex b/ebsetup.tex
index 9f7b407f0511b4849469714a2bd9bea0378ba81e..793820d7a24e6dc1ed0599880597f8fea4606f88 100644 (file)
--- a/ebsetup.tex
+++ b/ebsetup.tex
@@ -7,51 +7,51 @@
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{Port Numbers}
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-The first EB on each server uses port numbers starting with 50000 (0xc350), the second process uses ports 52000 (0xcb20) and above, while the third EB uses ports 54000 (0xd2f0) and above. Sender port and receiver port are always equal. The sender MAC is of the form 02:30:DE:AD:nn:nn where nn:nn is the same as the network address and the SubEventId of the corresponding sender.
+The first EB on each server uses port numbers starting with 50000 (0xc350), the second process uses ports 50256 (0xc450) and above, while the third EB uses ports 50512 (0xc550) and above. Sender port and receiver port are always equal. The sender MAC is of the form 02:30:DE:AD:nn:nn where nn:nn is the same as the network address and the SubEventId of the corresponding sender.
 
-The source IP is in the 192.168.100.0/24 Subnet. The lowest byte starts with 128 and the has the same offsets as the port numbers.
+The source IP is in the 192.168.100.0/24 Subnet. The lowest byte starts with 128 and then has the same offsets as the port numbers of the first EB.
 
 
 \begin{table}
 \begin{center}
-\begin{tabular}{|c|c|c|c|c|c|}
+\begin{tabular}{|c|c|c|c|c|c|c|}
 \hline
-\textbf{System} & \textbf{SubEvtId} & \textbf{EB 0 -- 3, 15} & \textbf{EB 4 -- 7}  & \textbf{EB 8 -- 11} & \textbf{IP} \\
+\textbf{System} & \textbf{SubEvtId} & \textbf{EB 0 -- 3} & \textbf{EB 4 -- 7}  & \textbf{EB 8 -- 11}  & \textbf{EB 12 -- 15} & \textbf{IP} \\
 \hline
 \hline
-Central  & 0x8000 & 50000 & 52000 & 54000 & 128 \\
-MDC1/2   & 0x8100 & 50001 & 52001 & 54001 & 129 \\
-MDC3/4   & 0x8110 & 50002 & 52002 & 54002 & 130 \\
-RICH 1/2 & 0x8300 & 50003 & 52003 & 54003 & 131 \\
-RICH 3/4 & 0x8310 & 50004 & 52004 & 54004 & 132 \\
-RICH 5/6 & 0x8320 & 50005 & 52005 & 54005 & 133 \\
-RPC 1/2/3& 0x8400 & 50006 & 52006 & 54006 & 134 \\
-RPC 4/5/6& 0x8410 & 50007 & 52007 & 54007 & 135 \\
-Shower   & 0x8500 & 50008 & 52008 & 54008 & 136 \\
-TOF      & 0x8600 & 50009 & 52009 & 54009 & 137 \\
-FW       & 0x8700 & 50010 & 52010 & 54010 & 138 \\
-Start/Veto/CTS & 0x8800 &  50011 & 52011 & 54011 & 139 \\
+Central  & 0x8000 & 50011 & 50267 & 50523 & 50779 & 128 \\
+MDC1/2   & 0x8100 & 50001 & 50257 & 50513 & 50769 & 129 \\
+MDC3/4   & 0x8110 & 50002 & 50258 & 50514 & 50770 & 130 \\
+RICH 1/2 & 0x8300 & 50003 & 50259 & 50515 & 50771 & 131 \\
+RICH 3/4 & 0x8310 & 50004 & 50260 & 50516 & 50772 & 132 \\
+RICH 5/6 & 0x8320 & 50005 & 50261 & 50517 & 50773 & 133 \\
+RPC 1/2/3& 0x8400 & 50006 & 50262 & 50518 & 50774 & 134 \\
+RPC 4/5/6& 0x8410 & 50007 & 50263 & 50519 & 50775 & 135 \\
+Shower   & 0x8500 & 50008 & 50264 & 50520 & 50776 & 136 \\
+TOF      & 0x8600 & 50009 & 50265 & 50521 & 50777 & 137 \\
+FW       & 0x8700 & 50010 & 50266 & 50522 & 50778 & 138 \\
+Start/Veto/CTS & 0x8800 &  50000 & 50256 & 50512 & 50768 & 139 \\
 \hline
-MDC1/2 1 & 0x1000 & 50016 & 52016 & 54016 & 144 \\
-MDC1/2 2 & 0x1010 & 50017 & 52017 & 54017 & 145 \\
-MDC1/2 3 & 0x1020 & 50018 & 52018 & 54018 & 146 \\
-MDC1/2 4 & 0x1030 & 50019 & 52019 & 54019 & 147 \\
-MDC1/2 5 & 0x1040 & 50020 & 52020 & 54020 & 148 \\
-MDC1/2 6 & 0x1050 & 50021 & 52021 & 54021 & 149 \\
+MDC1/2 1 & 0x1000 & 50016 & 50272 & 50528 & 50784 & 144 \\
+MDC1/2 2 & 0x1010 & 50017 & 50273 & 50529 & 50785 & 145 \\
+MDC1/2 3 & 0x1020 & 50018 & 50274 & 50530 & 50786 & 146 \\
+MDC1/2 4 & 0x1030 & 50019 & 50275 & 50531 & 50787 & 147 \\
+MDC1/2 5 & 0x1040 & 50020 & 50276 & 50532 & 50788 & 148 \\
+MDC1/2 6 & 0x1050 & 50021 & 50277 & 50533 & 50789 & 149 \\
 \hline
-MDC3/4 1 & 0x1100 & 50022 & 52022 & 54022 & 150 \\
-MDC3/4 2 & 0x1110 & 50023 & 52023 & 54023 & 151 \\
-MDC3/4 3 & 0x1120 & 50024 & 52024 & 54024 & 152 \\
-MDC3/4 4 & 0x1130 & 50025 & 52025 & 54025 & 153 \\
-MDC3/4 5 & 0x1140 & 50026 & 52026 & 54026 & 154 \\
-MDC3/4 6 & 0x1150 & 50027 & 52027 & 54027 & 155 \\
+MDC3/4 1 & 0x1100 & 50022 & 50278 & 50534 & 50790 & 150 \\
+MDC3/4 2 & 0x1110 & 50023 & 50279 & 50535 & 50791 & 151 \\
+MDC3/4 3 & 0x1120 & 50024 & 50280 & 50536 & 50792 & 152 \\
+MDC3/4 4 & 0x1130 & 50025 & 50281 & 50537 & 50793 & 153 \\
+MDC3/4 5 & 0x1140 & 50026 & 50282 & 50538 & 50794 & 154 \\
+MDC3/4 6 & 0x1150 & 50027 & 50283 & 50539 & 50795 & 155 \\
 \hline
-Shower 1 & 0x3200 & 50032 & 52032 & 54032 & 160 \\
-Shower 2 & 0x3210 & 50033 & 52033 & 54033 & 161 \\
-Shower 3 & 0x3220 & 50034 & 52034 & 54034 & 162 \\
-Shower 4 & 0x3230 & 50035 & 52035 & 54035 & 163 \\
-Shower 5 & 0x3240 & 50036 & 52036 & 54036 & 164 \\
-Shower 6 & 0x3250 & 50037 & 52037 & 54037 & 165 \\
+Shower 1 & 0x3200 & 50032 & 50288 & 50544 & 50600 & 160 \\
+Shower 2 & 0x3210 & 50033 & 50289 & 50545 & 50601 & 161 \\
+Shower 3 & 0x3220 & 50034 & 50290 & 50546 & 50602 & 162 \\
+Shower 4 & 0x3230 & 50035 & 50291 & 50547 & 50603 & 163 \\
+Shower 5 & 0x3240 & 50036 & 50292 & 50548 & 50604 & 164 \\
+Shower 6 & 0x3250 & 50037 & 50293 & 50549 & 50605 & 165 \\
 \hline
 \end{tabular}
 \caption{The UDP ports used to send data to the Eventbuilders}

diff --git a/endpoint.tex b/endpoint.tex
index a87b9fad22e8229b238ef2f92193f88f307472b2..301f2833b6e1462eb085ea7b93f5e05cf283540c 100755 (executable)
--- a/endpoint.tex
+++ b/endpoint.tex
@@ -115,7 +115,7 @@ All endpoint monitoring and status registers can be found in the address region
 7110 & LVL1 Buffer Status & Status of the LVL1 header / data buffer \\
 7200 & LVL1 release status & Release-flag for each of the data channel \\
 7201 & Data Handler Debug & Debug register of the data handler \\
-7202 & IPU Handler Status & IPU handler status register (see table \ref{endpointipuhandlerstatus}\\
+7202 & IPU Handler Status & IPU handler status register (see table \ref{endpointipuhandlerstatus})\\
 \hline
 \end{tabularx}
 \caption{Register Map of the full endpoint containing data handlers.}

diff --git a/hubs.tex b/hubs.tex
index 05214de4b68a1bb39ec5f7d6cf5497718d4a85e6..13c73233cbe774148faed6258ae3e48c792e9fec 100755 (executable)
--- a/hubs.tex
+++ b/hubs.tex
@@ -47,7 +47,7 @@
  \item[0x4030 -- 0x403F: Inclusive busy counter]One register for each port counting the time the port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4030 clears all counters.
  \item[0x4040 -- 0x404F: Exclusive busy counter] One register for each port counting the time this port and only this port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4040 clears all counters.
  \item[0x4050: Global Time] Here, the global time also accessible in register 0x50 is readable. This allows to do a simultaneous readout with the busy counter registers to get exact time information.
-\item[0x4060 -- 0x406F: LSM Status] Status of the media interfaces. Bit 2--0: med\_error\_out, Bit 7--4: Link state machine status bits, Bit 23 -- 16: Number of retransmit requests received by media interface, Bit 31 -- 24: Number of retransmit requests sent by media interface.
+ \item[0x4060 -- 0x406F: LSM Status $\dagger$] Status of the media interfaces. Bit 2--0: med\_error\_out, Bit 7--4: Link state machine status bits, Bit 23 -- 16: Number of retransmit requests received by media interface, Bit 31 -- 24: Number of retransmit requests sent by media interface.
 
 \end{description}
 $\dagger$: Register is not reset during network reset

diff --git a/mdc.tex b/mdc.tex
index 44d953b76c41395ad9cee12659dfb8075ba51c72..4b2968eddea1590d9ff7f1c3f8070298ad9899c9 100755 (executable)
--- a/mdc.tex
+++ b/mdc.tex
@@ -132,7 +132,9 @@ The bits of the common status and control registers used in the OEP are listed i
 15 & reboot FPGA  & reboot OEP\\
 14 -- 11 & reserved  & n/a\\
 10 & reset sequence counter  & reset seq. counter\\
-9 -- 4 & reserved  & n/a\\
+9 -- 6 & reserved  & n/a\\
+5 & reset status registers / error counters & \\
+4 & reset persistent error flags & \\
 3 & master reset  & n/a\\
 2 & empty IPU chain / reset IPU logic  & reset IPU\\
 1 & reset trigger logic  & reset readout logic\\

diff --git a/networkaddresses.tex b/networkaddresses.tex
index fec62c0c96a4036de0634bc40c6f21bcdbb31c27..67e1a75c702c5950b455a70f266d68342aae9f50 100755 (executable)
--- a/networkaddresses.tex
+++ b/networkaddresses.tex
@@ -81,19 +81,21 @@ In summary, the only boards that send subevents are the Hubs, MDC Concentrators
 \begin{center}
 \begin{tabularx}{\textwidth}{l|l|l|X}
 \textbf{System} & \textbf{ID} & \textbf{Number} & \textbf{Description} \\
-CTS        & 0000 - 00FF & 1  & only with the old CTS board!\\
+CTS        & 0000 - 00FF & 1(*)  & only with the old CTS board!\\
 MDC        & 1000 - 17FF & 12 & second digit is inner(0) or outer(1) MDC, 3rd digit is the sector \\
 Shower     & 3200 - 33FF & 6  & 3rd digit is the sector \\
-Forw. Wall & 4400 - 47FF & 3  & last digit is the segment of FW \\
-RPC        & 4800 - 4BFF & 24 & 3rd digit is the sector, last digit normal(0) or additional(1) TRB \\
-TOF        & 4C00 - 4FFF & 9  & 3rd digit is normal(0) or additional(1) TRB, last digit is the sector \\
+Forw. Wall & 4400 - 47FF & 3(*)  & last digit is the segment of FW \\
+RPC        & 4800 - 4BFF & 24(*) & 3rd digit is the sector, last digit normal(0) or additional(1) TRB \\
+TOF        & 4C00 - 4FFF & 9(*)  & 3rd digit is normal(0) or additional(1) TRB, last digit is the sector \\
+MDC        & 8100 - 81FF & 2(*)  & MDC readout via Hub \\
 RICH       & 8300 - 83FF & 3  & last digit is the sector divided by 2 \\
 RPC        & 8400 - 84FF & 2  & RPC readout via GbE \\
+Shower     & 8500 - 85FF & 1(*) & Shower readout via Hub \\
 TOF        & 8600 - 86FF & 1  & TOF readout via GbE \\
 Wall       & 8700 - 87FF & 1  & Forward Wall readout via GbE \\
 Start/Veto & 8800 - 88FF & 1 & Start / Veto  (and CTS in the final version) \\
 \end{tabularx}
-\caption{Reserved SubEvent IDs Ranges. }
+\caption{Reserved SubEvent IDs Ranges. Ranges marked with a (*) are not going to be used in the standard setup.}
 \label{subeventidtable}
 \end{center}
 \end{table}

diff --git a/rich.tex b/rich.tex
index d350f9e38582ecabbdf2cbcee4dda37a024e3d4d..0c1621b38c019979194c2df148c93842d2e9f1bf 100755 (executable)
--- a/rich.tex
+++ b/rich.tex
@@ -260,14 +260,14 @@ register.
 \subsubsection{ADC level register}
 
 For digital header reconstruction from analog values this register provides 
-four settings. BIT\_LOW defines the maximum value for a digital Zero, 
-BIT\_HIGH the minimum value for a digital One, and FLAT\_LOW \/ FLAT\_HIGH 
+four settings. Bit\_\-Low defines the maximum value for a digital Zero, 
+Bit\_\-High the minimum value for a digital One, and Flat\_\-Low \/ Flat\_\-High 
 the limits for a flatline caused by a missing APV frontend card (which equals 
 to a flat line on ADC around half of the input value).
 
 \noindent Values are given in raw ADC units, the least significant nibble
 of the value is fixed to zero.\\ 
-To set 0xA00 as BIT\_HIGH, 0xA0 has to be written to D[31:0]
+To set 0xA00 as Bit\-\_High, 0xA0 has to be written to D[31:0]
 
 \noindent The APV sync state machines need correct values in this register 
 for operation.