attilio:. added reset for mdc_addon_daq_bus0, used to reload thresholds

diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd
index cada1eb32cc154bc346d4252e4949e1c8c3d0cf3..b6c5bc67d9b1986b4cbb4968b4d688096993f7a0 100644 (file)
--- a/mdc_oepb.vhd
+++ b/mdc_oepb.vhd
@@ -168,7 +168,19 @@ architecture mdc_oepb_arch of mdc_oepb is
   signal counter: std_logic_vector (3 downto 0);
   signal test_pseudo_signal_i : std_logic;
 
-
+  signal flash_mem_data : std_logic_vector(31 downto 0);
+  signal flash_mem_data_out : std_logic_vector(31 downto 0);
+  signal flash_mem_write: std_logic;
+  signal flash_mem_read : std_logic;
+  signal flash_mem_addr : std_logic_vector(8 downto 0);
+
+  signal cmd_register_in  : std_logic_vector(31 downto 0);
+  signal ctrl_register : std_logic_vector(31 downto 0);
+  signal write_cmd_register_in : std_logic;
+  signal write_ctrl_register : std_logic;
+
+  signal reset_mdc_addon_daq_bus_0, pulse_reset_internal_logic : std_logic;
+  
 begin
 ---------------------------------------------------------------------
 -- PLL: 100 MHz
@@ -385,9 +397,9 @@ THE_REG_DAT_ADDR : process(CLK_100)
 
 THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
   generic map(
-    PORT_NUMBER => 2,
-    PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", others => x"0000"),
-    PORT_ADDR_MASK => (0 => 8,       1 => 6,       others => 0)
+    PORT_NUMBER => 3,
+    PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"9000", others => x"0000"),
+    PORT_ADDR_MASK => (0 => 8, 1 => 6, 2 => 8, others => 0)
     )
   port map(
     CLK                   => CLK_100,
@@ -426,11 +438,64 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_WRITE_ACK_IN(1)               => adc_write_ack,
     BUS_NO_MORE_DATA_IN(1)            => adc_no_more_data,
     BUS_UNKNOWN_ADDR_IN(1)            => adc_unknown_addr,
+--Bus Handler input on third port (SPI-FLASH)
+    BUS_READ_ENABLE_OUT(2)            => flash_mem_read,
+    BUS_WRITE_ENABLE_OUT(2)           => flash_mem_write,
+    BUS_DATA_OUT(2*32+31 downto 2*32) => flash_mem_data,
+    BUS_ADDR_OUT(2*16+8 downto 2*16)  => flash_mem_addr,
+    BUS_TIMEOUT_OUT(2)                => open, 
+    BUS_DATA_IN(2*32+31 downto 2*32)  => flash_mem_data_out,
+    BUS_DATAREADY_IN(2)               => very_last_reg_REGIO_READ,
+    BUS_WRITE_ACK_IN(2)               => reg_REGIO_WRITE,
+    BUS_NO_MORE_DATA_IN(2)            => '0',
+    BUS_UNKNOWN_ADDR_IN(2)            => '0',    
    --Debugging
     STAT_DEBUG                 => open
     );
 
+-------------------------------------------------------------------------------
+-- SPI
+-------------------------------------------------------------------------------
+  process(CLK_100)
+    begin
+      if rising_edge(CLK_100) then
+        flash_mem_data_out <= (others => '0');
+
+        if (flash_mem_addr(3 downto 0) = x"0") then
+          write_cmd_register_in <= flash_mem_write;
+          flash_mem_data_out <= cmd_register_in;
+          
+        elsif (flash_mem_addr(3 downto 0) = x"1") then
+          write_ctrl_register      <= flash_mem_write;
+           flash_mem_data_out <= ctrl_register;
+        else
+          cmd_register_in    <= cmd_register_in;
+          ctrl_register      <= ctrl_register;
+        end if;
+      end if;
+    end process;
 
+    process(CLK_100)
+    begin
+      if rising_edge(CLK_100) then
+        if (write_cmd_register_in = '1') then
+          cmd_register_in <= flash_mem_data;
+        else
+          cmd_register_in <= cmd_register_in;
+        end if;
+      end if;
+    end process;
+
+    process(CLK_100)
+    begin
+      if rising_edge(CLK_100) then
+        if (write_ctrl_register = '1') then
+          ctrl_register      <= flash_mem_data;
+        else
+          ctrl_register      <= ctrl_register;
+        end if;
+      end if;
+    end process;  
 ---------------------------------------------------------------------
 -- ADC
 ---------------------------------------------------------------------
@@ -521,6 +586,15 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
         SIGNAL_IN     => REGIO_COMMON_CTRL_REG_OUT(16),
         PULSE_OUT     => pulse_pseudo_timing_trigger);
 
+    PULSE_RESET_LOGIC : edge_to_pulse
+      port map (
+        CLOCK         => CLK_100,
+        ENABLE_CLK_IN => '1',
+        SIGNAL_IN     => REGIO_COMMON_CTRL_REG_OUT(0),
+        PULSE_OUT     => pulse_reset_internal_logic);
+
+ reset_mdc_addon_daq_bus_0  <= reset_internal or pulse_reset_internal_logic;
+    
     PULSE_BEGRUN_TRIGGER : edge_to_pulse
        port map (
          CLOCK         => CLK_100,
@@ -557,7 +631,7 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
     --generic map (bus_number => bus_number)
     port map (
       CLK                          => CLK_100,
-      RESET                        => reset_internal,
+      RESET                        => reset_mdc_addon_daq_bus_0,--reset_internal,
       A_ADS_0                      => '0',
       A_ADS_1                      => '0',
       A_ADS_2                      => '0',