CLK_EN : in std_logic;
APL_SHORT_TRANSFER_OUT : out std_logic;
+ APL_SEND_OUT : out std_logic;
APL_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
APL_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
APL_DATAREADY_IN : in std_logic;
APL_READ_OUT : out std_logic;
- APL_RUN_IN : in std_logic
+ APL_RUN_IN : in std_logic;
+
+ BUS_DBG_RX : in CTRLBUS_RX;
+ BUS_DBG_TX : out CTRLBUS_TX;
+ dbg_cnt_rdy : in unsigned(15 downto 0)
);
end entity;
architecture cri_data_receiver_arch of cri_data_receiver is
- type state_t is (Receive, REPLY);
+ type state_t is (RECEIVE, PREPARE, REPLY);
+ signal state_num : std_logic_vector(3 downto 0) := x"0";
signal state : state_t;
signal buf_APL_READ_OUT : std_logic;
signal buf_APL_SHORT_TRANSFER_OUT : std_logic;
- signal buf_rec_data : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal buf_rec_data : std_logic_vector(c_DATA_WIDTH-1 downto 0) := x"9876";
+ signal buf_APL_SEND : std_logic;
+
+ signal event_cnt : std_logic_vector(31 downto 0) := x"0000_0000";
+ signal data_cnt : std_logic_vector(31 downto 0) := x"0000_0000";
+ signal datardy_cnt : std_logic_vector(31 downto 0) := x"0000_0000";
+ signal last_APL_TYP_IN : std_logic_vector( 2 downto 0);
signal fifo_wr : std_logic;
signal fifo_almFull : std_logic;
begin
if rising_edge(CLK) then
if RESET = '1' then
- state <= Receive;
+ state <= RECEIVE;
+ state_num <= x"0";
buf_APL_READ_OUT <= '0';
buf_APL_SHORT_TRANSFER_OUT <= '0';
fifo_wr <= '0';
buf_APL_SHORT_TRANSFER_OUT <= '0';
fifo_wr <= '0';
case state is
- when Receive =>
+ when RECEIVE =>
+ state_num <= x"1";
+ buf_APL_SEND <= '0';
if APL_DATAREADY_IN = '1' and buf_APL_READ_OUT = '1' then
if APL_TYP_IN = TYPE_TRM then -- end of event
- state <= REPLY;
+ state <= PREPARE;
else
case APL_PACKET_NUM_IN is
when c_F0 => null; --crc field, ignore
fifo_wr <= '1';
when others => null;
end case;
+ state <= RECEIVE;
end if;
end if;
+ when PREPARE =>
+ state_num <= x"2";
+ buf_APL_READ_OUT <= '0';
+ buf_APL_SEND <= '0';
+ state <= REPLY;
+
when REPLY =>
+ state_num <= x"3";
+ buf_APL_SEND <= '1';
buf_APL_READ_OUT <= '0';
buf_APL_SHORT_TRANSFER_OUT <= '1';
- state <= Receive;
+ state <= RECEIVE;
when others =>
- state <= RECEIVE;
+ buf_APL_SEND <= '0';
+ state_num <= x"4";
+ state <= RECEIVE;
end case;
end if;
end if;
end process;
+ APL_SEND_OUT <= buf_APL_SEND;
APL_READ_OUT <= buf_APL_READ_OUT;
APL_SHORT_TRANSFER_OUT <= buf_APL_SHORT_TRANSFER_OUT;
+
+THE_Event_Cntr : process begin
+ wait until rising_edge(CLK);
+
+ if RESET = '1' then
+ last_APL_TYP_IN <= (others => '0');
+ event_cnt <= (others => '0');
+ data_cnt <= (others => '0');
+ datardy_cnt <= (others => '0');
+ else
+ last_APL_TYP_IN <= APL_TYP_IN;
+ if ((APL_TYP_IN = TYPE_TRM) and (last_APL_TYP_IN /= TYPE_TRM)) then
+ event_cnt <= event_cnt + 1;
+ end if;
+
+ if (APL_DATAREADY_IN = '1') and (buf_APL_READ_OUT = '1') then
+ data_cnt <= data_cnt + 1;
+ end if;
+
+ if (APL_DATAREADY_IN = '1') then
+ datardy_cnt <= datardy_cnt + 1;
+ end if;
+ end if;
+
+ end process;
+
+THE_CRI_DATA_RECEIVER_DEBUG_HANDLER : process begin
+ wait until rising_edge(CLK);
+ BUS_DBG_TX.ack <= '0';
+ BUS_DBG_TX.nack <= '0';
+ BUS_DBG_TX.unknown <= '0';
+
+ if BUS_DBG_RX.read = '1' then
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"00" then
+ BUS_DBG_TX.data <= x"00000"& "000" & buf_APL_READ_OUT & APL_DATAREADY_IN & APL_PACKET_NUM_IN & state_num;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"01" then
+ BUS_DBG_TX.data <= x"0000" & buf_rec_data;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"02" then
+ BUS_DBG_TX.data <= event_cnt;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"03" then
+ BUS_DBG_TX.data <= data_cnt;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"04" then
+ BUS_DBG_TX.data <= datardy_cnt;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"05" then
+ BUS_DBG_TX.data <= x"0000" & std_logic_vector(dbg_cnt_rdy);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ elsif BUS_DBG_RX.write = '1' then
+ --if BUS_DBG_RX.addr( 7 downto 0) = x"0C" then
+ -- MUX_cal_sw <= BUS_DBG_RX.data(0);
+ --end if;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+ end process;
end architecture;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_ARITH.ALL;
USE IEEE.std_logic_UNSIGNED.ALL;
+USE IEEE.numeric_std.ALL;
library work;
use work.trb_net_std.all;
type send_state_t is (IDLE, WAITING, SEND_DATA, READ_ANSWER);
signal send_state_current, send_state_next : send_state_t;
- signal send_state_bits : std_logic_vector( 2 downto 0);
+ signal send_state_bits : std_logic_vector( 3 downto 0);
attribute syn_encoding : string;
type fifo_states is (IDLE, PREPARE_DATA, WAIT_FOR_READY, SAVE, CLOSE, WAIT_FOR_TRANS, DIVIDE, CLEANUP);
signal fifo_machine_current_state, fifo_machine_next_state : fifo_states;
attribute syn_encoding of fifo_machine_current_state : signal is "onehot";
- signal fifo_state_bits : std_logic_vector( 2 downto 0);
+ signal fifo_state_bits : std_logic_vector( 3 downto 0);
type loc_buffer_t is array (0 to 15) of std_logic_vector(17 downto 0);
signal local_buffer : loc_buffer_t := (others => (others=> '0'));
signal buf_API_READ_OUT : std_logic;
signal buf_API_SEND_OUT : std_logic;
+ signal packet_number : std_logic_vector(2 downto 0);
begin
if RESET = '1' then
fifo_machine_current_state <= IDLE;
elsif rising_edge(CLK) then
- fifo_machine_current_state <= transmit_next_state;
+ fifo_machine_current_state <= fifo_machine_next_state;
end if;
end process FIFO_MACHINE_PROC;
FIFO_MACHINE : process(fifo_machine_current_state, CRI_DATAREADY_IN, local_end, fifo_almFull)
begin
- fifo_machine_state <= x"0";
+ fifo_state_bits <= x"0";
case fifo_machine_current_state is
when IDLE =>
- fifo_machine_state <= x"1";
+ fifo_state_bits <= x"1";
if (CRI_DATAREADY_IN = '1') then
fifo_machine_next_state <= PREPARE_DATA;
else
end if;
when PREPARE_DATA =>
- fifo_machine_state <= x"2";
+ fifo_state_bits <= x"2";
if (fifo_almFull = '0') then
fifo_machine_next_state <= WAIT_FOR_READY;
else
fifo_machine_next_state <= PREPARE_DATA;
end if;
when WAIT_FOR_READY =>
- fifo_machine_state <= x"3";
+ fifo_state_bits <= x"3";
if (fifo_almFull = '0') then
fifo_machine_next_state <= SAVE;
else
end if;
when SAVE =>
- fifo_machine_state <= x"4";
+ fifo_state_bits <= x"4";
if (local_end = x"0000") then -- or look for DataIn(8) ??
fifo_machine_next_state <= CLOSE;
else
end if;
when CLOSE =>
- fifo_machine_state <= x"5";
+ fifo_state_bits <= x"5";
fifo_machine_next_state <= IDLE;
end case;
- end process FIFO_MACHINE;
+ end process;
LOCAL_END_PROC : process begin
if (fifo_machine_current_state = IDLE and CRI_DATAREADY_IN = '1') then
local_end <= CRI_LENGTH_IN - x"1";
--full_packet_size <= CRI_LENGTH_IN;
- elsif (transmit_current_state = SAVE) then
+ elsif (fifo_machine_current_state = SAVE) then
local_end <= local_end - x"1";
--full_packet_size <= full_packet_size;
else
local_end <= local_end;
--full_packet_size <= full_packet_size;
end if;
- end process LOCAL_END_PROC;
+ end process;
SYNC_PROC : process begin
wait until rising_edge(CLK);
cri_rd_q <= cri_rd;
cri_rd_qq <= cri_rd_q;
cri_data_avail <= cri_rd_qq;
- end process SYNC_PROC;
+ end process;
-- If a 8bit word is available, it is putt in the correct position of the
if RESET = '1' then
data_word_pos <= '0';
else
- if cri_data_avail = 1 then
+ if cri_data_avail = '1' then
if data_word_pos = '0' then
fifo_data_in(7 downto 0) <= CRI_DATA_IN(7 downto 0);
fifo_data_in(16) <= CRI_DATA_IN(8); --16: mark lower 8 bit as end;
data_word_pos <= '1';
-- case that event size is odd;
- if (CRI_DATA_IN(8) = 1) then
+ if (CRI_DATA_IN(8) = '1') then
fifo_data_in(15 downto 8) <= (others => '0');
fifo_data_in(17) <= CRI_DATA_IN(8); --17: mark 16bit as EOD;
end if;
end if;
end if;
- end process LOCAL_END_PROC;
+ end process;
cri_rd <= '1' when fifo_machine_current_state = SAVE else '0';
CRI_READ_OUT <= cri_rd;
buf_API_SEND_OUT <= '0';
loc_sending_flag <= '0';
- if (API_RUN_IN = '0' and (not fifo_empty)) then
+ if ((API_RUN_IN = '0') and (fifo_empty = '0')) then
send_state_next <= WAITING;
end if;
---------------------------------------------------------------------
--Debugging
---------------------------------------------------------------------
- STAT_DEBUG( 2 downto 0) <= fifo_state_bits;
- STAT_DEBUG( 5 downto 3) <= send_state_bits;
- STAT_DEBUG(31 downto 3) <= (others => '0');
+ STAT_DEBUG( 2 downto 0) <= fifo_state_bits(2 downto 0);
+ STAT_DEBUG( 5 downto 3) <= send_state_bits(2 downto 0);
+ STAT_DEBUG(31 downto 6) <= (others => '0');
--Debugging registers
STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
- CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
+ CTRL_DEBUG : in std_logic_vector (31 downto 0); --free control regs for debugging
-- bits 0-2 are NOT (inverted) error of streaming port
+
+ BUS_HUB_DBG_RX : in CTRLBUS_RX;
+ BUS_HUB_DBG_TX : out CTRLBUS_TX
);
end entity;
signal buf_cri_to_apl_seqnr : std_logic_vector(MII_NUMBER*8-1 downto 0);
signal buf_cri_to_apl_type : std_logic_vector(MII_NUMBER*3-1 downto 0);
+ signal bus_cri_data_rec_rx : ctrlbus_rx_array_t(0 to MII_NUMBER-1);
+ signal bus_cri_data_rec_tx : ctrlbus_tx_array_t(0 to MII_NUMBER-1);
+ type point_array_t is array (0 to 15) of unsigned(15 downto 0);
+ signal dbg_cnt : point_array_t := (others => (others=> '0'));
+
+
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
attribute syn_preserve of m_DATA_IN : signal is true;
constant i : integer := j*2**(c_MUX_WIDTH-1)+k;
begin
-- data channel
- gen_iobuf: if (k = 1) and ( j < MII_NUMBER-1) generate
+ gen_iobuf: if (k = c_DATA_CHANNEL) generate --and ( j < MII_NUMBER-1)
IOBUF: trb_net16_iobuf
generic map (
IBUF_DEPTH => calc_depth(i,MII_IBUF_DEPTH, INT_IBUF_DEPTH, MII_NUMBER, INT_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
end generate;
-- slow control channel
- gen_iobuf: if k = 3 generate
+ gen_iobuf: if k = c_SLOW_CTRL_CHANNEL generate
IOBUF: trb_net16_iobuf
generic map (
IBUF_DEPTH => calc_depth(i,MII_IBUF_DEPTH, INT_IBUF_DEPTH, MII_NUMBER, INT_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
);
end generate;
- gen_trmbuf: if (k = 0) or (k = 2) or ((k = 1) and ( j = MII_NUMBER-1)) generate -- terminate trigger channel and chnl 2 and data uplink channel
+ gen_trmbuf: if (k = 0) or (k = 2) generate -- or ((k = c_DATA_CHANNEL) and ( j = MII_NUMBER-1)) : terminate trigger channel and chnl 2 and data uplink channel
hub_to_buf_init_read(i) <= '0';
buf_to_hub_init_dataready(i) <= '0';
buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
);
end generate;
gen_select_logic2 : if (i = c_DATA_CHANNEL) generate -- TODO: think about the last channel: data uplink to nowhere
- gen_data_chnl_api : for j in 0 to MII_NUMBER-1 generate
+ gen_data_chnl_api : for j in 0 to point_num-1 generate
constant local_position : integer := first_point_num+j;
begin
--API for data channel
APL_SHORT_TRANSFER_IN => buf_apl_to_cri_short_transfer(j),
APL_DTYPE_IN => (others => '0'),
APL_ERROR_PATTERN_IN => (others => '0'),
- APL_SEND_IN => '0',--buf_apl_to_cri_send(j), -- 1 till end of Datastream
+ APL_SEND_IN => buf_apl_to_cri_send(j), -- 1 till end of Datastream
APL_TARGET_ADDRESS_IN => (others => '0'),
-- Receiver port
APL_DATA_OUT => buf_cri_to_apl_data((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
APL_FIFO_COUNT_OUT => open,
-- Internal direction port
- INT_MASTER_DATAREADY_OUT => HUB_REPLY_DATAREADY_IN(local_position),
- INT_MASTER_DATA_OUT => HUB_REPLY_DATA_IN((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> HUB_REPLY_PACKET_NUM_IN((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
- INT_MASTER_READ_IN => HUB_REPLY_READ_OUT(local_position),
+ INT_MASTER_DATAREADY_OUT => HUB_REPLY_DATAREADY_OUT(local_position),
+ INT_MASTER_DATA_OUT => HUB_REPLY_DATA_OUT((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_OUT=> HUB_REPLY_PACKET_NUM_OUT((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
+ INT_MASTER_READ_IN => HUB_REPLY_READ_IN(local_position),
- INT_MASTER_DATAREADY_IN => HUB_REPLY_DATAREADY_OUT(local_position),
- INT_MASTER_DATA_IN => HUB_REPLY_DATA_OUT((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => HUB_REPLY_PACKET_NUM_OUT((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => HUB_REPLY_READ_IN(local_position),
+ INT_MASTER_DATAREADY_IN => HUB_REPLY_DATAREADY_IN(local_position),
+ INT_MASTER_DATA_IN => HUB_REPLY_DATA_IN((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_IN => HUB_REPLY_PACKET_NUM_IN((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
+ INT_MASTER_READ_OUT => HUB_REPLY_READ_OUT(local_position),
- INT_SLAVE_DATAREADY_OUT => HUB_INIT_DATAREADY_IN(local_position),
- INT_SLAVE_DATA_OUT => HUB_INIT_DATA_IN((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT => HUB_INIT_PACKET_NUM_IN((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => HUB_INIT_READ_OUT(local_position),
+ INT_SLAVE_DATAREADY_OUT => HUB_INIT_DATAREADY_OUT(local_position),
+ INT_SLAVE_DATA_OUT => HUB_INIT_DATA_OUT((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_OUT => HUB_INIT_PACKET_NUM_OUT((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
+ INT_SLAVE_READ_IN => HUB_INIT_READ_IN(local_position),
- INT_SLAVE_DATAREADY_IN => HUB_INIT_DATAREADY_OUT(local_position),
- INT_SLAVE_DATA_IN => HUB_INIT_DATA_OUT((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN => HUB_INIT_PACKET_NUM_OUT((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => HUB_INIT_READ_IN(local_position),
+ INT_SLAVE_DATAREADY_IN => HUB_INIT_DATAREADY_IN(local_position),
+ INT_SLAVE_DATA_IN => HUB_INIT_DATA_IN((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_IN => HUB_INIT_PACKET_NUM_IN((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
+ INT_SLAVE_READ_OUT => HUB_INIT_READ_OUT(local_position),
-- Status and control port
CTRL_SEQNR_RESET => '0',--common_ctrl(10), --TO BE IMPLEMENTED
STAT_FIFO_TO_APL => open
);
+
+ DBG_INPUT2API : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if reset_i = '1' then
+ dbg_cnt(j) <= 0;
+ else
+ if HUB_INIT_DATAREADY_IN(local_position) = '1' or HUB_REPLY_DATAREADY_IN(local_position) = '1' then
+ dbg_cnt(j) <= dbg_cnt(j) + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
CRI_DATA_RECEIVER: entity work.cri_data_receiver
port map (
CLK => CLK,
CLK_EN => '1',
APL_SHORT_TRANSFER_OUT => buf_apl_to_cri_short_transfer(j),
+ APL_SEND_OUT => buf_apl_to_cri_send(j),
APL_DATA_IN => buf_cri_to_apl_data((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
APL_PACKET_NUM_IN => buf_cri_to_apl_packnum((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
APL_DATAREADY_IN => buf_cri_to_apl_dataready(j),
APL_READ_OUT => buf_apl_to_cri_read(j),
- APL_RUN_IN => buf_cri_to_apl_run(j)
+ APL_RUN_IN => buf_cri_to_apl_run(j),
+
+ BUS_DBG_RX => bus_cri_data_rec_rx(j),
+ BUS_DBG_TX => bus_cri_data_rec_tx(j),
+
+ dbg_cnt_rdy => dbg_cnt(j)
);
end generate;
HUB_INIT_READ_OUT(next_point_num-1 downto first_point_num) <= (others => '0');
end generate;
end generate;
-
+
gen_unused_signals : for i in 0 to 2**(c_MUX_WIDTH-1)-2 generate
begin
buf_STAT_POINTS_locked((i+1)*32-1 downto i*32) <= (others => '0');
iobuf_stat_data_counter((i+1)*32-1 downto i*32) <= (others => '0');
stat_timeout((i+1)*32-1 downto i*32) <= (others => '0');
end generate;
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_CRI_DATA_REC_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 10,
+ PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0200", 3 => x"0300", 4 => x"0400", 5 => x"0500", 6 => x"0600", 7 => x"0700",
+ 8 => x"0800", 9 => x"0900", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 8, 1 => 8, 2 => 8, 3 => 8, 4 => 8, 5 => 8, 6 => 8, 7 => 8,
+ 8 => 8, 9 => 8, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => CLK,
+ RESET => reset_i,
+
+ REGIO_RX => BUS_HUB_DBG_RX,
+ REGIO_TX => BUS_HUB_DBG_TX,
+
+ BUS_RX(0) => bus_cri_data_rec_rx(0), --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bus_cri_data_rec_rx(1),
+ BUS_RX(2) => bus_cri_data_rec_rx(2),
+ BUS_RX(3) => bus_cri_data_rec_rx(3),
+ BUS_RX(4) => bus_cri_data_rec_rx(4),
+ BUS_RX(5) => bus_cri_data_rec_rx(5),
+ BUS_RX(6) => bus_cri_data_rec_rx(6),
+ BUS_RX(7) => bus_cri_data_rec_rx(7),
+ BUS_RX(8) => bus_cri_data_rec_rx(8),
+ BUS_RX(9) => bus_cri_data_rec_rx(9),
+
+ BUS_TX(0) => bus_cri_data_rec_tx(0),
+ BUS_TX(1) => bus_cri_data_rec_tx(1),
+ BUS_TX(2) => bus_cri_data_rec_tx(2),
+ BUS_TX(3) => bus_cri_data_rec_tx(3),
+ BUS_TX(4) => bus_cri_data_rec_tx(4),
+ BUS_TX(5) => bus_cri_data_rec_tx(5),
+ BUS_TX(6) => bus_cri_data_rec_tx(6),
+ BUS_TX(7) => bus_cri_data_rec_tx(7),
+ BUS_TX(8) => bus_cri_data_rec_tx(8),
+ BUS_TX(9) => bus_cri_data_rec_tx(9),
+ STAT_DEBUG => open
+ );
+
---------------------------------------------------------------------
--Control RegIO
---------------------------------------------------------------------
signal cfg_max_frame : std_logic_vector(15 downto 0);
signal tc_rd_en : std_logic := '0';
+ signal tc_data : std_logic_vector( 8 downto 0);
+ signal tc_size : std_logic_vector(15 downto 0);
signal resp_ready : std_logic := '0';
+ signal resp_busy : std_logic := '0';
+ signal cri_readout_finished_in : std_logic;
signal cri_init_dataready_out : std_logic;
signal cri_init_data_out : std_logic_vector(15 downto 0);
signal dbg_pc_sos_cnt : unsigned(15 downto 0);
signal dbg_pc_eos_cnt : unsigned(15 downto 0);
signal dbg_pc_eoq_cnt : unsigned(15 downto 0);
+
+ signal dbg_api_fifo_to_int : std_logic_vector(31 downto 0);
+ signal dbg_api_fifo_to_api : std_logic_vector(31 downto 0);
+
+ signal dbg_start_data_send : std_logic;
+
+ signal dbg_io_dataready_cnt_2 : unsigned(15 downto 0);
+ signal dbg_io_dataready_cnt_3 : unsigned(15 downto 0);
+ signal dbg_io_dataready_cnt_6 : unsigned(15 downto 0);
+ signal dbg_io_dataready_cnt_7 : unsigned(15 downto 0);
begin
PS_WR_EN_IN => '0',
PS_ACTIVATE_IN => '0',
PS_RESPONSE_READY_OUT => resp_ready, -- TODO: make use of it
- PS_BUSY_OUT => open,--busy(3), -- TODO: make use of it
+ PS_BUSY_OUT => resp_busy,--busy(3), -- TODO: make use of it
PS_SELECTED_IN => '1',
PS_SRC_MAC_ADDRESS_IN => (others => '0'),
PS_DEST_MAC_ADDRESS_IN => (others => '0'),
-- BEGIN TODO : Connect this to the ouside world. Now data is just thrown away
TC_RD_EN_IN => tc_rd_en,--'1',--TC_RD_EN_IN,
- TC_DATA_OUT => open,--tc_data(4 * 9 - 1 downto 3 * 9),
- TC_FRAME_SIZE_OUT => open,--tc_size(4 * 16 - 1 downto 3 * 16),
+ TC_DATA_OUT => tc_data,--tc_data(4 * 9 - 1 downto 3 * 9),
+ TC_FRAME_SIZE_OUT => tc_size,--tc_size(4 * 16 - 1 downto 3 * 16),
TC_FRAME_TYPE_OUT => open,--tc_type(4 * 16 - 1 downto 3 * 16),
TC_IP_PROTOCOL_OUT => open,--tc_ip_proto(4 * 8 - 1 downto 3 * 8),
TC_IDENT_OUT => open,--tc_ident(4 * 16 - 1 downto 3 * 16),
BUS_DBG_TX => BUS_DBG_TX,
--debuging for TrbNet Transfer
- dbg_event_cnt => cri_event_cnt
+ dbg_event_cnt => cri_event_cnt,
+ dbg_data_send_cnt => cri_data_send_cnt,
+ dbg_api_fifo_to_int => dbg_api_fifo_to_int,
+ dbg_api_fifo_to_api => dbg_api_fifo_to_api,
+ dbg_start_data_send => dbg_start_data_send,
+
+ dbg_io_datardy_data(15 downto 0) => std_logic_vector(dbg_io_dataready_cnt_2),
+ dbg_io_datardy_data(31 downto 16) => std_logic_vector(dbg_io_dataready_cnt_3),
+
+ dbg_io_datardy_slwc(15 downto 0) => std_logic_vector(dbg_io_dataready_cnt_6),
+ dbg_io_datardy_slwc(31 downto 16) => std_logic_vector(dbg_io_dataready_cnt_7)
);
cri_packet_num_cnt <= 0;
cri_data_send_cnt <= 0;
cri_event_cnt <= 0;
+
+ dbg_io_dataready_cnt_2 <= 0;
+ dbg_io_dataready_cnt_3 <= 0;
+ dbg_io_dataready_cnt_6 <= 0;
+ dbg_io_dataready_cnt_7 <= 0;
+
else
-- if resp_ready = '1' then --maybe not good in timing; then maybe event_bytes != loaded_bytes for ever
-- tc_rd_en <= '1';
-- else
-- tc_rd_en <= '0'; --includes also busy state
-- end if;
-
- if (debug_resp_control(35 downto 32) <= x"2") then
+ -- Test of readout
+ if (debug_resp_control(35 downto 32) <= x"2") then
+ -- if (resp_busy = '0') then
tc_rd_en <= '0';
else
tc_rd_en <= '1';
end if;
+ -- END Test of readout
- ---
-
- --fifo 8to 16 with almost empty and full
-
- if (cri_data_send_cnt < x"20" ) then
- cri_send <= '1';
- else
- cri_send <= '0';
- if (cri_apl_run_out = '0') then -- data transfer has finished and the reply is in
- cri_data_send_cnt <= 0;
- cri_event_cnt <= cri_event_cnt + 1;
+ --Test of data Sending
+ --TODO: FRIDAY 7.3.: STart over slowcontrol; monitor dataout on data channel to multiplexer! DONE - 2020-07-6
+ if dbg_start_data_send = '1' then
+ if (cri_data_send_cnt < 32 ) then
+ cri_send <= '1';
+ else
+ cri_send <= '0';
+ --if (cri_apl_run_out = '0') then -- data transfer has finished and the reply is in
+ if cri_apl_dataready_out = '1' and cri_apl_read_in = '1' and cri_apl_typ_out = TYPE_TRM then
+ cri_data_send_cnt <= 0;
+ cri_event_cnt <= cri_event_cnt + 1;
+ end if;
end if;
+
+ -- Write only if buffer in api is not full
+ if cri_apl_read_out = '1' and cri_send = '1' then --TODO: add fifo dataready for real dataflow
+ cri_apl_dataready_in <= '1';
+ cri_apl_data_in <= x"1234";
+ cri_apl_packet_num_in <= '0' & std_logic_vector(cri_packet_num_cnt);
+ cri_packet_num_cnt <= cri_packet_num_cnt + 1;
+ cri_apl_send_in <= '1';
+ cri_data_send_cnt <= cri_data_send_cnt + 1;
+ else
+ cri_apl_send_in <= '0';
+ cri_apl_dataready_in <= '0';
+ end if;
+ cri_apl_read_in <= '1';
+ end if;
+ --END Test of data Sending
+
+ if io_dataready_out(2) = '1' then
+ dbg_io_dataready_cnt_2 <= dbg_io_dataready_cnt_2 + 1;
end if;
- -- Write only if buffer in api is not full
- if cri_apl_read_out = '0' and cri_send = '1' then --TODO: add fifo dataready for real dataflow
- cri_apl_dataready_in <= '1';
- cri_apl_data_in <= x"1234";
- cri_apl_packet_num_in <= '0' & std_logic_vector(cri_packet_num_cnt);
- cri_packet_num_cnt <= cri_packet_num_cnt + 1;
- cri_apl_send_in <= '1';
- cri_data_send_cnt <= cri_data_send_cnt + 1;
- else
- cri_apl_send_in <= '0';
+ if io_dataready_out(3) = '1' then
+ dbg_io_dataready_cnt_3 <= dbg_io_dataready_cnt_3 + 1;
end if;
+ if io_dataready_out(6) = '1' then
+ dbg_io_dataready_cnt_6 <= dbg_io_dataready_cnt_6 + 1;
+ end if;
+ if io_dataready_out(7) = '1' then
+ dbg_io_dataready_cnt_7 <= dbg_io_dataready_cnt_7 + 1;
+ end if;
end if;
end process;
-
-
+
+-- THE_CRI_DATA_SENDER : entity work.cri_data_sender
+-- port map(
+-- -- Misc
+-- CLK => CLK,
+-- RESET => reset_i,
+-- CLK_EN => '1',
+-- -- Port to API
+-- API_DATA_OUT => cri_apl_data_in,
+-- API_PACKET_NUM_OUT => cri_apl_packet_num_in,
+-- API_DATAREADY_OUT => cri_apl_dataready_in,
+-- API_READ_IN => cri_apl_read_out,
+-- API_SHORT_TRANSFER_OUT => open,
+-- API_DTYPE_OUT => open,
+-- API_ERROR_PATTERN_OUT => open,
+-- API_SEND_OUT => cri_apl_send_in,
+-- -- Receiver port
+-- API_DATA_IN => cri_apl_data_out,
+-- API_PACKET_NUM_IN => cri_apl_packet_num_out,
+-- API_TYP_IN => cri_apl_typ_out,
+-- API_DATAREADY_IN => cri_apl_dataready_out,
+-- API_READ_OUT => cri_apl_read_in,
+-- -- APL Control port
+-- API_RUN_IN => cri_apl_run_out,
+-- API_SEQNR_IN => (others => '0'),
+-- API_LENGTH_OUT => open,
+-- MY_ADDRESS_IN => MY_ADDRESS_IN,
+--
+-- --data from event packer
+-- CRI_DATA_IN => tc_data, --8 is EOD
+-- CRI_DATAREADY_IN => resp_ready,
+-- --no more data, send TRM
+-- CRI_READOUT_FINISHED_IN => cri_readout_finished_in, --currently not used
+-- CRI_READ_OUT => tc_rd_en,
+-- CRI_LENGTH_IN => tc_size,
+--
+-- STAT_DEBUG => open
+-- );
+--
+-- cri_readout_finished_in <= resp_busy and not resp_ready;
+
---------------------------------------------------------------------
-- active API for Data Channel
---------------------------------------------------------------------
INT_SLAVE_READ_OUT => cri_reply_read_out,
-- Status and control port
CTRL_SEQNR_RESET => '0',--common_ctrl(10), --TO BE IMPLEMENTED
- STAT_FIFO_TO_INT => open,
- STAT_FIFO_TO_APL => open
+ STAT_FIFO_TO_INT => dbg_api_fifo_to_int,
+ STAT_FIFO_TO_APL => dbg_api_fifo_to_api
);
--iobuf on streaming api, towards CRI, data channel
end if;
elsif BUS_DBG_RX.write = '1' then
- --if BUS_DBG_RX.addr( 7 downto 0) = x"0C" then
- -- MUX_cal_sw <= BUS_DBG_RX.data(0);
- --end if;
- BUS_DBG_TX.ack <= '1';
+
+-- if BUS_DBG_RX.addr( 7 downto 0) = x"00" then
+-- dbg_start_data_send <= BUS_DBG_RX.data(0);
+-- end if;
+--
+-- BUS_DBG_TX.ack <= '1';
end if;
end process;
end generate debug_gen;
BUS_DBG_RX : in CTRLBUS_RX;
BUS_DBG_TX : out CTRLBUS_TX;
- dbg_event_cnt : in unsigned(15 downto 0)
+ dbg_event_cnt : in unsigned(15 downto 0);
+ dbg_data_send_cnt : in unsigned(15 downto 0);
+ dbg_api_fifo_to_int : in std_logic_vector(31 downto 0);
+ dbg_api_fifo_to_api : in std_logic_vector(31 downto 0);
+ dbg_start_data_send : out std_logic;
+
+ dbg_io_datardy_data : in std_logic_vector(31 downto 0);
+ dbg_io_datardy_slwc : in std_logic_vector(31 downto 0)
);
end trb_net16_cri_response_constructor_TrbNetData;
if BUS_DBG_RX.addr(7 downto 0) = x"09" then
BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_event_cnt);
- BUS_DBG_TX.data(31 downto 16) <= (others => '0');
+ BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_data_send_cnt);
BUS_DBG_TX.ack <= '1';
end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"0a" then
+ BUS_DBG_TX.data <= dbg_api_fifo_to_int;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"0b" then
+ BUS_DBG_TX.data <= dbg_api_fifo_to_api;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"0C" then
+ BUS_DBG_TX.data(0) <= dbg_start_data_send;
+ BUS_DBG_TX.data(31 downto 1) <= (others => '0');
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"0D" then
+ BUS_DBG_TX.data <= dbg_io_datardy_data;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"0E" then
+ BUS_DBG_TX.data <= dbg_io_datardy_slwc;
+ BUS_DBG_TX.ack <= '1';
+ end if;
elsif BUS_DBG_RX.write = '1' then
- --if BUS_DBG_RX.addr( 7 downto 0) = x"0C" then
- -- MUX_cal_sw <= BUS_DBG_RX.data(0);
- --end if;
+
+ if BUS_DBG_RX.addr( 7 downto 0) = x"0C" then
+ dbg_start_data_send <= BUS_DBG_RX.data(0);
+ end if;
+
BUS_DBG_TX.ack <= '1';
end if;
end process;
jspc29 / dirich.git / commitdiff