changed VHDL repos, JM

diff --git a/trb3/CodeRepository.tex b/trb3/CodeRepository.tex
index a83c6d0205d0f433060ec7070bdaf825b84b419a..8c2f73e3e4d51b25880e84559cae239f5df921a7 100644 (file)
--- a/trb3/CodeRepository.tex
+++ b/trb3/CodeRepository.tex
@@ -1,7 +1,7 @@
 \subsection{VHDL}
   \begin{description*}
-    \item[Trb3 Vhdl]~\\cvs -d hadaq@lxi051.gsi.de:/misc/hadesprojects/daq/cvsroot/  co trb3 
-    \item[TrbNet Vhdl]~\\cvs -d hadaq@lxi051.gsi.de:/misc/hadesprojects/daq/cvsroot/ co trbnet
+    \item[Trb3 Vhdl]~\\git clone git://jspc29.x-matter.uni-frankfurt.de/projects/trb3.git 
+    \item[TrbNet Vhdl]~\\git clone git://jspc29.x-matter.uni-frankfurt.de/projects/trbnet.git
   \end{description*}
 
 \subsection{Software / Documentation}

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index e79b9db2eed00cb8dce879fb3e0b55fd4b8f3c5b..5421101789cf68914120a23a339dd9e58b0e60f4 100644 (file)
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -69,7 +69,7 @@ The lower 16 Bit are used to identify the contents of the design and the AddOn b
   \item[1XXX]  use with ADA adapter board AddOn version 2
   \item[2XXX]  use with multipurpose test AddOn
   \item[3XXX]  use with SFP hub AddOn
-  \item[4XXX]  use with Wasa adapter AddOn
+  \item[4XXX]  use with Padiwa adapter AddOn
   \item[8XXX]  uses RX clock as main internal clock
   \item[X0nX]  contains $2^n$ TDC channels, single edge
   \item[X1nX]  contains $2^n$ TDC channels, double edge

diff --git a/trb3/main.tex b/trb3/main.tex
index 9bb2e9910c116b0b7789a5331d960a883c6c8a41..66c0c6da7fea68ec72d51e71aeb44d603dcbd1dd 100644 (file)
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -153,7 +153,7 @@
       \input{MvdAddOn}
     \subsection{CTS AddOn}
       \input{CtsAddOn}
-    \subsection{Panda Dirc Wasa Front-end}
+    \subsection{Padiwa}
       \input{WasaFrontend}
 
   \section{Related Boards}