added ADC frontends to discussion

diff --git a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf
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Binary files a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf and b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf differ

diff --git a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex
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--- a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex
+++ b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex
@@ -393,8 +393,11 @@ described charge-to-width front-end. The temperature independence of
 the PaDiWa thresholds and of the TDC calibration is currently
 investigated. There are also several further front-end developments:
 Integration of the MuPix ASIC for the PANDA luminosity detector and
-the SPADIC ASIC for a TPC in Mainz. An ~50 channel 10bit 65MSPS ADC AddOn (4
-can be put in one TRB3) is in the layout phase. Since both ASICs use the CBMnet
+the SPADIC ASIC for a TPC in Mainz. An $\sim$50 channel 10bit 65MSPS ADC AddOn (4
+can be put in one TRB3) is in the layout phase. For the
+PANDA-Straw-Tube-Tracker the development of an ADC inside FPGA is
+followed. Test measurements show that an ADC with 8 bits resolution and
+>50MSPS is possible. Since both ASICs use the CBMnet
 protocol, an implementation of CBMnet on the TRB3 was started.
 Furthermore, an extension of TrbNet with defined propagation delays of
 trigger signals for PANDA is being developed and tested.