Mention TDC counter registers 0xc000 and above.

Correct a typo.

diff --git a/trb3/TdcDataFormat.tex b/trb3/TdcDataFormat.tex
index ebc2fb10d72e47a0f5cc608b2c1b8980ab967458..764e6a3fa6683ba324e130c6209dd704d01a4d8e 100644 (file)
--- a/trb3/TdcDataFormat.tex
+++ b/trb3/TdcDataFormat.tex
@@ -13,8 +13,8 @@ The data format of the \textbf{\textit{time data}} word is shown below:
       \textbf{Data Format} & \textbf{Bits} & \textbf{Description}\\
       \hline
       0x0 & 31 & Time Data Marker\\
-      & 30 & reserved. In v2.4 used as marker for corrected, approximate time values\\
-      & 29 & reserved\\
+      & 30 & reserved\\
+      & 29 & reserved. In v2.4 used as marker for corrected, approximate time values\\
       & 28-22 & channel number\\
       & 21-12 & fine time - sum of the two transition of the WUL\\
       & 11 & the type of the measured edge - '1' rising, '0' falling edge\\
@@ -46,7 +46,7 @@ Three time informations are generated for each signal detected by each
 channel; epoch counter, coarse counter and fine counter. The epoch counter
 word is explained in \ref{sec:tdcEpoch}. The coarse time information has the
 granularity of 5~ns (period of the system clock). The range of the coarse time
-is 10,24~us. The fine time has the range of 5~ns but doesn't have a fixed
+is 10.24~us. The fine time has the range of 5~ns but doesn't have a fixed
 granularity. The fine time information has to be calibrated using the
 statistic collected by the individual channel (for details see
 \ref{sec:tdcFineTime}). The response efficiency of the TDC is 100\%. So even

diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex
index 98526e451e7fd2aab394144249d2314bb4474e81..cf5950e96a9e808af01870fcab36b99aa845320c 100644 (file)
--- a/trb3/TdcSlowControl.tex
+++ b/trb3/TdcSlowControl.tex
@@ -1,3 +1,10 @@
+A set of rate registers is available starting from address 0xc000 up to 0xc040, 
+depending on the number of channels included. The lower 31 Bit of these registers
+are used as counters for rising edges on the input. The uppermost bit reflects
+the current status of the input - '1' when high, '0' when low. This bit is useful
+to determine the correct polarity settings of the inputs.
+ 
+ 
  A set of control registers (0xc800) are assigned in order to access the basic
  controls, edit the features and debug information of the TDC. A detailed
  explanation of the control registers are given in Table