--- /dev/null
+\r
+\r
+-- channel_0 is in "Gigabit Ethernet" mode\r
+-- channel_1 is in "Disabled" mode\r
+-- channel_2 is in "Disabled" mode\r
+-- channel_3 is in "Disabled" mode\r
+\r
+--synopsys translate_off\r
+\r
+library pcsa_work;\r
+use pcsa_work.all;\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity PCSA is\r
+GENERIC(\r
+ CONFIG_FILE : String := "serdes_gbe_0.txt"\r
+ );\r
+port (\r
+ HDINP0 : in std_logic;\r
+ HDINN0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ REFCLKP : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ RXREFCLKP : in std_logic;\r
+ RXREFCLKN : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+\r
+ FFC_LANE_TX_RST0 : in std_logic;\r
+ FFC_LANE_TX_RST1 : in std_logic;\r
+ FFC_LANE_TX_RST2 : in std_logic;\r
+ FFC_LANE_TX_RST3 : in std_logic;\r
+\r
+ FFC_LANE_RX_RST0 : in std_logic;\r
+ FFC_LANE_RX_RST1 : in std_logic;\r
+ FFC_LANE_RX_RST2 : in std_logic;\r
+ FFC_LANE_RX_RST3 : in std_logic;\r
+\r
+ FFC_PCIE_EI_EN_0 : in std_logic;\r
+ FFC_PCIE_EI_EN_1 : in std_logic;\r
+ FFC_PCIE_EI_EN_2 : in std_logic;\r
+ FFC_PCIE_EI_EN_3 : in std_logic;\r
+\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+\r
+ FFC_PCIE_TX_0 : in std_logic;\r
+ FFC_PCIE_TX_1 : in std_logic;\r
+ FFC_PCIE_TX_2 : in std_logic;\r
+ FFC_PCIE_TX_3 : in std_logic;\r
+\r
+ FFC_PCIE_RX_0 : in std_logic;\r
+ FFC_PCIE_RX_1 : in std_logic;\r
+ FFC_PCIE_RX_2 : in std_logic;\r
+ FFC_PCIE_RX_3 : in std_logic;\r
+\r
+ FFC_SD_0 : in std_logic;\r
+ FFC_SD_1 : in std_logic;\r
+ FFC_SD_2 : in std_logic;\r
+ FFC_SD_3 : in std_logic;\r
+\r
+ FFC_EN_CGA_0 : in std_logic;\r
+ FFC_EN_CGA_1 : in std_logic;\r
+ FFC_EN_CGA_2 : in std_logic;\r
+ FFC_EN_CGA_3 : in std_logic;\r
+\r
+ FFC_ALIGN_EN_0 : in std_logic;\r
+ FFC_ALIGN_EN_1 : in std_logic;\r
+ FFC_ALIGN_EN_2 : in std_logic;\r
+ FFC_ALIGN_EN_3 : in std_logic;\r
+\r
+ FFC_AB_RESET : in std_logic;\r
+ FFC_CD_RESET : in std_logic;\r
+\r
+ FFS_LS_STATUS_0 : out std_logic;\r
+ FFS_LS_STATUS_1 : out std_logic;\r
+ FFS_LS_STATUS_2 : out std_logic;\r
+ FFS_LS_STATUS_3 : out std_logic;\r
+\r
+ FFS_AB_STATUS : out std_logic;\r
+ FFS_CD_STATUS : out std_logic;\r
+\r
+ FFS_AB_ALIGNED : out std_logic;\r
+ FFS_CD_ALIGNED : out std_logic;\r
+\r
+ FFS_RLOS_LO0 : out std_logic;\r
+ FFS_RLOS_LO1 : out std_logic;\r
+ FFS_RLOS_LO2 : out std_logic;\r
+ FFS_RLOS_LO3 : out std_logic;\r
+\r
+ FFS_AB_FAILED : out std_logic;\r
+ FFS_CD_FAILED : out std_logic;\r
+\r
+ FFC_FB_LB_0 : in std_logic;\r
+ FFC_FB_LB_1 : in std_logic;\r
+ FFC_FB_LB_2 : in std_logic;\r
+ FFC_FB_LB_3 : in std_logic;\r
+\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+\r
+ FFS_CC_ORUN_0 : out std_logic;\r
+ FFS_CC_ORUN_1 : out std_logic;\r
+ FFS_CC_ORUN_2 : out std_logic;\r
+ FFS_CC_ORUN_3 : out std_logic;\r
+\r
+ FFS_CC_URUN_0 : out std_logic;\r
+ FFS_CC_URUN_1 : out std_logic;\r
+ FFS_CC_URUN_2 : out std_logic;\r
+ FFS_CC_URUN_3 : out std_logic;\r
+\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ RDATAO_7 : out std_logic;\r
+ RDATAO_6 : out std_logic;\r
+ RDATAO_5 : out std_logic;\r
+ RDATAO_4 : out std_logic;\r
+ RDATAO_3 : out std_logic;\r
+ RDATAO_2 : out std_logic;\r
+ RDATAO_1 : out std_logic;\r
+ RDATAO_0 : out std_logic;\r
+ INTO : out std_logic;\r
+\r
+ ADDRI_7 : in std_logic;\r
+ ADDRI_6 : in std_logic;\r
+ ADDRI_5 : in std_logic;\r
+ ADDRI_4 : in std_logic;\r
+ ADDRI_3 : in std_logic;\r
+ ADDRI_2 : in std_logic;\r
+ ADDRI_1 : in std_logic;\r
+ ADDRI_0 : in std_logic;\r
+ WDATAI_7 : in std_logic;\r
+ WDATAI_6 : in std_logic;\r
+ WDATAI_5 : in std_logic;\r
+ WDATAI_4 : in std_logic;\r
+ WDATAI_3 : in std_logic;\r
+ WDATAI_2 : in std_logic;\r
+ WDATAI_1 : in std_logic;\r
+ WDATAI_0 : in std_logic;\r
+ RDI : in std_logic;\r
+ WSTBI : in std_logic;\r
+\r
+ CS_CHIF_0 : in std_logic;\r
+ CS_CHIF_1 : in std_logic;\r
+ CS_CHIF_2 : in std_logic;\r
+ CS_CHIF_3 : in std_logic;\r
+ CS_QIF : in std_logic;\r
+\r
+ QUAD_ID_1 : in std_logic;\r
+ QUAD_ID_0 : in std_logic;\r
+\r
+ FF_SYSCLK_P1 : out std_logic;\r
+\r
+ FF_SYSCLK0 : out std_logic;\r
+ FF_SYSCLK1 : out std_logic;\r
+ FF_SYSCLK2 : out std_logic;\r
+ FF_SYSCLK3 : out std_logic;\r
+\r
+ FF_RXCLK_P1 : out std_logic;\r
+ FF_RXCLK_P2 : out std_logic;\r
+\r
+ FF_RXCLK0 : out std_logic;\r
+ FF_RXCLK1 : out std_logic;\r
+ FF_RXCLK2 : out std_logic;\r
+ FF_RXCLK3 : out std_logic;\r
+\r
+ QUAD_CLK : out std_logic;\r
+\r
+ GRP_CLK_P1_3 : in std_logic;\r
+ GRP_CLK_P1_2 : in std_logic;\r
+ GRP_CLK_P1_1 : in std_logic;\r
+ GRP_CLK_P1_0 : in std_logic;\r
+\r
+ GRP_CLK_P2_3 : in std_logic;\r
+ GRP_CLK_P2_2 : in std_logic;\r
+ GRP_CLK_P2_1 : in std_logic;\r
+ GRP_CLK_P2_0 : in std_logic;\r
+\r
+ GRP_START_3 : in std_logic;\r
+ GRP_START_2 : in std_logic;\r
+ GRP_START_1 : in std_logic;\r
+ GRP_START_0 : in std_logic;\r
+\r
+ GRP_DONE_3 : in std_logic;\r
+ GRP_DONE_2 : in std_logic;\r
+ GRP_DONE_1 : in std_logic;\r
+ GRP_DONE_0 : in std_logic;\r
+\r
+ GRP_DESKEW_ERROR_3 : in std_logic;\r
+ GRP_DESKEW_ERROR_2 : in std_logic;\r
+ GRP_DESKEW_ERROR_1 : in std_logic;\r
+ GRP_DESKEW_ERROR_0 : in std_logic;\r
+\r
+ IQA_START_LS : out std_logic;\r
+ IQA_DONE_LS : out std_logic;\r
+ IQA_AND_FP1_LS : out std_logic;\r
+ IQA_AND_FP0_LS : out std_logic;\r
+ IQA_OR_FP1_LS : out std_logic;\r
+ IQA_OR_FP0_LS : out std_logic;\r
+ IQA_RST_N : out std_logic;\r
+\r
+ FF_TCLK0 : in std_logic;\r
+ FF_TCLK1 : in std_logic;\r
+ FF_TCLK2 : in std_logic;\r
+ FF_TCLK3 : in std_logic;\r
+\r
+ FF_RCLK0 : in std_logic;\r
+ FF_RCLK1 : in std_logic;\r
+ FF_RCLK2 : in std_logic;\r
+ FF_RCLK3 : in std_logic;\r
+ TCK_FMACP : in std_logic;\r
+\r
+ FF_TXD_0_23 : in std_logic;\r
+ FF_TXD_0_22 : in std_logic;\r
+ FF_TXD_0_21 : in std_logic;\r
+ FF_TXD_0_20 : in std_logic;\r
+ FF_TXD_0_19 : in std_logic;\r
+ FF_TXD_0_18 : in std_logic;\r
+ FF_TXD_0_17 : in std_logic;\r
+ FF_TXD_0_16 : in std_logic;\r
+ FF_TXD_0_15 : in std_logic;\r
+ FF_TXD_0_14 : in std_logic;\r
+ FF_TXD_0_13 : in std_logic;\r
+ FF_TXD_0_12 : in std_logic;\r
+ FF_TXD_0_11 : in std_logic;\r
+ FF_TXD_0_10 : in std_logic;\r
+ FF_TXD_0_9 : in std_logic;\r
+ FF_TXD_0_8 : in std_logic;\r
+ FF_TXD_0_7 : in std_logic;\r
+ FF_TXD_0_6 : in std_logic;\r
+ FF_TXD_0_5 : in std_logic;\r
+ FF_TXD_0_4 : in std_logic;\r
+ FF_TXD_0_3 : in std_logic;\r
+ FF_TXD_0_2 : in std_logic;\r
+ FF_TXD_0_1 : in std_logic;\r
+ FF_TXD_0_0 : in std_logic;\r
+ FB_RXD_0_23 : out std_logic;\r
+ FB_RXD_0_22 : out std_logic;\r
+ FB_RXD_0_21 : out std_logic;\r
+ FB_RXD_0_20 : out std_logic;\r
+ FB_RXD_0_19 : out std_logic;\r
+ FB_RXD_0_18 : out std_logic;\r
+ FB_RXD_0_17 : out std_logic;\r
+ FB_RXD_0_16 : out std_logic;\r
+ FB_RXD_0_15 : out std_logic;\r
+ FB_RXD_0_14 : out std_logic;\r
+ FB_RXD_0_13 : out std_logic;\r
+ FB_RXD_0_12 : out std_logic;\r
+ FB_RXD_0_11 : out std_logic;\r
+ FB_RXD_0_10 : out std_logic;\r
+ FB_RXD_0_9 : out std_logic;\r
+ FB_RXD_0_8 : out std_logic;\r
+ FB_RXD_0_7 : out std_logic;\r
+ FB_RXD_0_6 : out std_logic;\r
+ FB_RXD_0_5 : out std_logic;\r
+ FB_RXD_0_4 : out std_logic;\r
+ FB_RXD_0_3 : out std_logic;\r
+ FB_RXD_0_2 : out std_logic;\r
+ FB_RXD_0_1 : out std_logic;\r
+ FB_RXD_0_0 : out std_logic;\r
+ FF_TXD_1_23 : in std_logic;\r
+ FF_TXD_1_22 : in std_logic;\r
+ FF_TXD_1_21 : in std_logic;\r
+ FF_TXD_1_20 : in std_logic;\r
+ FF_TXD_1_19 : in std_logic;\r
+ FF_TXD_1_18 : in std_logic;\r
+ FF_TXD_1_17 : in std_logic;\r
+ FF_TXD_1_16 : in std_logic;\r
+ FF_TXD_1_15 : in std_logic;\r
+ FF_TXD_1_14 : in std_logic;\r
+ FF_TXD_1_13 : in std_logic;\r
+ FF_TXD_1_12 : in std_logic;\r
+ FF_TXD_1_11 : in std_logic;\r
+ FF_TXD_1_10 : in std_logic;\r
+ FF_TXD_1_9 : in std_logic;\r
+ FF_TXD_1_8 : in std_logic;\r
+ FF_TXD_1_7 : in std_logic;\r
+ FF_TXD_1_6 : in std_logic;\r
+ FF_TXD_1_5 : in std_logic;\r
+ FF_TXD_1_4 : in std_logic;\r
+ FF_TXD_1_3 : in std_logic;\r
+ FF_TXD_1_2 : in std_logic;\r
+ FF_TXD_1_1 : in std_logic;\r
+ FF_TXD_1_0 : in std_logic;\r
+ FB_RXD_1_23 : out std_logic;\r
+ FB_RXD_1_22 : out std_logic;\r
+ FB_RXD_1_21 : out std_logic;\r
+ FB_RXD_1_20 : out std_logic;\r
+ FB_RXD_1_19 : out std_logic;\r
+ FB_RXD_1_18 : out std_logic;\r
+ FB_RXD_1_17 : out std_logic;\r
+ FB_RXD_1_16 : out std_logic;\r
+ FB_RXD_1_15 : out std_logic;\r
+ FB_RXD_1_14 : out std_logic;\r
+ FB_RXD_1_13 : out std_logic;\r
+ FB_RXD_1_12 : out std_logic;\r
+ FB_RXD_1_11 : out std_logic;\r
+ FB_RXD_1_10 : out std_logic;\r
+ FB_RXD_1_9 : out std_logic;\r
+ FB_RXD_1_8 : out std_logic;\r
+ FB_RXD_1_7 : out std_logic;\r
+ FB_RXD_1_6 : out std_logic;\r
+ FB_RXD_1_5 : out std_logic;\r
+ FB_RXD_1_4 : out std_logic;\r
+ FB_RXD_1_3 : out std_logic;\r
+ FB_RXD_1_2 : out std_logic;\r
+ FB_RXD_1_1 : out std_logic;\r
+ FB_RXD_1_0 : out std_logic;\r
+ FF_TXD_2_23 : in std_logic;\r
+ FF_TXD_2_22 : in std_logic;\r
+ FF_TXD_2_21 : in std_logic;\r
+ FF_TXD_2_20 : in std_logic;\r
+ FF_TXD_2_19 : in std_logic;\r
+ FF_TXD_2_18 : in std_logic;\r
+ FF_TXD_2_17 : in std_logic;\r
+ FF_TXD_2_16 : in std_logic;\r
+ FF_TXD_2_15 : in std_logic;\r
+ FF_TXD_2_14 : in std_logic;\r
+ FF_TXD_2_13 : in std_logic;\r
+ FF_TXD_2_12 : in std_logic;\r
+ FF_TXD_2_11 : in std_logic;\r
+ FF_TXD_2_10 : in std_logic;\r
+ FF_TXD_2_9 : in std_logic;\r
+ FF_TXD_2_8 : in std_logic;\r
+ FF_TXD_2_7 : in std_logic;\r
+ FF_TXD_2_6 : in std_logic;\r
+ FF_TXD_2_5 : in std_logic;\r
+ FF_TXD_2_4 : in std_logic;\r
+ FF_TXD_2_3 : in std_logic;\r
+ FF_TXD_2_2 : in std_logic;\r
+ FF_TXD_2_1 : in std_logic;\r
+ FF_TXD_2_0 : in std_logic;\r
+ FB_RXD_2_23 : out std_logic;\r
+ FB_RXD_2_22 : out std_logic;\r
+ FB_RXD_2_21 : out std_logic;\r
+ FB_RXD_2_20 : out std_logic;\r
+ FB_RXD_2_19 : out std_logic;\r
+ FB_RXD_2_18 : out std_logic;\r
+ FB_RXD_2_17 : out std_logic;\r
+ FB_RXD_2_16 : out std_logic;\r
+ FB_RXD_2_15 : out std_logic;\r
+ FB_RXD_2_14 : out std_logic;\r
+ FB_RXD_2_13 : out std_logic;\r
+ FB_RXD_2_12 : out std_logic;\r
+ FB_RXD_2_11 : out std_logic;\r
+ FB_RXD_2_10 : out std_logic;\r
+ FB_RXD_2_9 : out std_logic;\r
+ FB_RXD_2_8 : out std_logic;\r
+ FB_RXD_2_7 : out std_logic;\r
+ FB_RXD_2_6 : out std_logic;\r
+ FB_RXD_2_5 : out std_logic;\r
+ FB_RXD_2_4 : out std_logic;\r
+ FB_RXD_2_3 : out std_logic;\r
+ FB_RXD_2_2 : out std_logic;\r
+ FB_RXD_2_1 : out std_logic;\r
+ FB_RXD_2_0 : out std_logic;\r
+ FF_TXD_3_23 : in std_logic;\r
+ FF_TXD_3_22 : in std_logic;\r
+ FF_TXD_3_21 : in std_logic;\r
+ FF_TXD_3_20 : in std_logic;\r
+ FF_TXD_3_19 : in std_logic;\r
+ FF_TXD_3_18 : in std_logic;\r
+ FF_TXD_3_17 : in std_logic;\r
+ FF_TXD_3_16 : in std_logic;\r
+ FF_TXD_3_15 : in std_logic;\r
+ FF_TXD_3_14 : in std_logic;\r
+ FF_TXD_3_13 : in std_logic;\r
+ FF_TXD_3_12 : in std_logic;\r
+ FF_TXD_3_11 : in std_logic;\r
+ FF_TXD_3_10 : in std_logic;\r
+ FF_TXD_3_9 : in std_logic;\r
+ FF_TXD_3_8 : in std_logic;\r
+ FF_TXD_3_7 : in std_logic;\r
+ FF_TXD_3_6 : in std_logic;\r
+ FF_TXD_3_5 : in std_logic;\r
+ FF_TXD_3_4 : in std_logic;\r
+ FF_TXD_3_3 : in std_logic;\r
+ FF_TXD_3_2 : in std_logic;\r
+ FF_TXD_3_1 : in std_logic;\r
+ FF_TXD_3_0 : in std_logic;\r
+ FB_RXD_3_23 : out std_logic;\r
+ FB_RXD_3_22 : out std_logic;\r
+ FB_RXD_3_21 : out std_logic;\r
+ FB_RXD_3_20 : out std_logic;\r
+ FB_RXD_3_19 : out std_logic;\r
+ FB_RXD_3_18 : out std_logic;\r
+ FB_RXD_3_17 : out std_logic;\r
+ FB_RXD_3_16 : out std_logic;\r
+ FB_RXD_3_15 : out std_logic;\r
+ FB_RXD_3_14 : out std_logic;\r
+ FB_RXD_3_13 : out std_logic;\r
+ FB_RXD_3_12 : out std_logic;\r
+ FB_RXD_3_11 : out std_logic;\r
+ FB_RXD_3_10 : out std_logic;\r
+ FB_RXD_3_9 : out std_logic;\r
+ FB_RXD_3_8 : out std_logic;\r
+ FB_RXD_3_7 : out std_logic;\r
+ FB_RXD_3_6 : out std_logic;\r
+ FB_RXD_3_5 : out std_logic;\r
+ FB_RXD_3_4 : out std_logic;\r
+ FB_RXD_3_3 : out std_logic;\r
+ FB_RXD_3_2 : out std_logic;\r
+ FB_RXD_3_1 : out std_logic;\r
+ FB_RXD_3_0 : out std_logic;\r
+ TCK_FMAC : out std_logic;\r
+ BS4PAD_0 : out std_logic;\r
+ BS4PAD_1 : out std_logic;\r
+ BS4PAD_2 : out std_logic;\r
+ BS4PAD_3 : out std_logic;\r
+ COUT_21 : out std_logic;\r
+ COUT_20 : out std_logic;\r
+ COUT_19 : out std_logic;\r
+ COUT_18 : out std_logic;\r
+ COUT_17 : out std_logic;\r
+ COUT_16 : out std_logic;\r
+ COUT_15 : out std_logic;\r
+ COUT_14 : out std_logic;\r
+ COUT_13 : out std_logic;\r
+ COUT_12 : out std_logic;\r
+ COUT_11 : out std_logic;\r
+ COUT_10 : out std_logic;\r
+ COUT_9 : out std_logic;\r
+ COUT_8 : out std_logic;\r
+ COUT_7 : out std_logic;\r
+ COUT_6 : out std_logic;\r
+ COUT_5 : out std_logic;\r
+ COUT_4 : out std_logic;\r
+ COUT_3 : out std_logic;\r
+ COUT_2 : out std_logic;\r
+ COUT_1 : out std_logic;\r
+ COUT_0 : out std_logic;\r
+ CIN_12 : in std_logic;\r
+ CIN_11 : in std_logic;\r
+ CIN_10 : in std_logic;\r
+ CIN_9 : in std_logic;\r
+ CIN_8 : in std_logic;\r
+ CIN_7 : in std_logic;\r
+ CIN_6 : in std_logic;\r
+ CIN_5 : in std_logic;\r
+ CIN_4 : in std_logic;\r
+ CIN_3 : in std_logic;\r
+ CIN_2 : in std_logic;\r
+ CIN_1 : in std_logic;\r
+ CIN_0 : in std_logic;\r
+ TESTCLK_MACO : in std_logic\r
+);\r
+\r
+end PCSA;\r
+\r
+architecture PCSA_arch of PCSA is\r
+\r
+component PCSA_sim\r
+GENERIC(\r
+ CONFIG_FILE : String\r
+ );\r
+port (\r
+ HDINP0 : in std_logic;\r
+ HDINN0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ REFCLKP : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ RXREFCLKP : in std_logic;\r
+ RXREFCLKN : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+\r
+ FFC_LANE_TX_RST0 : in std_logic;\r
+ FFC_LANE_TX_RST1 : in std_logic;\r
+ FFC_LANE_TX_RST2 : in std_logic;\r
+ FFC_LANE_TX_RST3 : in std_logic;\r
+\r
+ FFC_LANE_RX_RST0 : in std_logic;\r
+ FFC_LANE_RX_RST1 : in std_logic;\r
+ FFC_LANE_RX_RST2 : in std_logic;\r
+ FFC_LANE_RX_RST3 : in std_logic;\r
+\r
+ FFC_PCIE_EI_EN_0 : in std_logic;\r
+ FFC_PCIE_EI_EN_1 : in std_logic;\r
+ FFC_PCIE_EI_EN_2 : in std_logic;\r
+ FFC_PCIE_EI_EN_3 : in std_logic;\r
+\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+\r
+ FFC_PCIE_TX_0 : in std_logic;\r
+ FFC_PCIE_TX_1 : in std_logic;\r
+ FFC_PCIE_TX_2 : in std_logic;\r
+ FFC_PCIE_TX_3 : in std_logic;\r
+\r
+ FFC_PCIE_RX_0 : in std_logic;\r
+ FFC_PCIE_RX_1 : in std_logic;\r
+ FFC_PCIE_RX_2 : in std_logic;\r
+ FFC_PCIE_RX_3 : in std_logic;\r
+\r
+ FFC_SD_0 : in std_logic;\r
+ FFC_SD_1 : in std_logic;\r
+ FFC_SD_2 : in std_logic;\r
+ FFC_SD_3 : in std_logic;\r
+\r
+ FFC_EN_CGA_0 : in std_logic;\r
+ FFC_EN_CGA_1 : in std_logic;\r
+ FFC_EN_CGA_2 : in std_logic;\r
+ FFC_EN_CGA_3 : in std_logic;\r
+\r
+ FFC_ALIGN_EN_0 : in std_logic;\r
+ FFC_ALIGN_EN_1 : in std_logic;\r
+ FFC_ALIGN_EN_2 : in std_logic;\r
+ FFC_ALIGN_EN_3 : in std_logic;\r
+\r
+ FFC_AB_RESET : in std_logic;\r
+ FFC_CD_RESET : in std_logic;\r
+\r
+ FFS_LS_STATUS_0 : out std_logic;\r
+ FFS_LS_STATUS_1 : out std_logic;\r
+ FFS_LS_STATUS_2 : out std_logic;\r
+ FFS_LS_STATUS_3 : out std_logic;\r
+\r
+ FFS_AB_STATUS : out std_logic;\r
+ FFS_CD_STATUS : out std_logic;\r
+\r
+ FFS_AB_ALIGNED : out std_logic;\r
+ FFS_CD_ALIGNED : out std_logic;\r
+\r
+ FFS_AB_FAILED : out std_logic;\r
+ FFS_CD_FAILED : out std_logic;\r
+\r
+ FFS_RLOS_LO0 : out std_logic;\r
+ FFS_RLOS_LO1 : out std_logic;\r
+ FFS_RLOS_LO2 : out std_logic;\r
+ FFS_RLOS_LO3 : out std_logic;\r
+\r
+ FFC_FB_LB_0 : in std_logic;\r
+ FFC_FB_LB_1 : in std_logic;\r
+ FFC_FB_LB_2 : in std_logic;\r
+ FFC_FB_LB_3 : in std_logic;\r
+\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+\r
+ FFS_CC_ORUN_0 : out std_logic;\r
+ FFS_CC_ORUN_1 : out std_logic;\r
+ FFS_CC_ORUN_2 : out std_logic;\r
+ FFS_CC_ORUN_3 : out std_logic;\r
+\r
+ FFS_CC_URUN_0 : out std_logic;\r
+ FFS_CC_URUN_1 : out std_logic;\r
+ FFS_CC_URUN_2 : out std_logic;\r
+ FFS_CC_URUN_3 : out std_logic;\r
+\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ RDATAO_7 : out std_logic;\r
+ RDATAO_6 : out std_logic;\r
+ RDATAO_5 : out std_logic;\r
+ RDATAO_4 : out std_logic;\r
+ RDATAO_3 : out std_logic;\r
+ RDATAO_2 : out std_logic;\r
+ RDATAO_1 : out std_logic;\r
+ RDATAO_0 : out std_logic;\r
+ INTO : out std_logic;\r
+\r
+ ADDRI_7 : in std_logic;\r
+ ADDRI_6 : in std_logic;\r
+ ADDRI_5 : in std_logic;\r
+ ADDRI_4 : in std_logic;\r
+ ADDRI_3 : in std_logic;\r
+ ADDRI_2 : in std_logic;\r
+ ADDRI_1 : in std_logic;\r
+ ADDRI_0 : in std_logic;\r
+ WDATAI_7 : in std_logic;\r
+ WDATAI_6 : in std_logic;\r
+ WDATAI_5 : in std_logic;\r
+ WDATAI_4 : in std_logic;\r
+ WDATAI_3 : in std_logic;\r
+ WDATAI_2 : in std_logic;\r
+ WDATAI_1 : in std_logic;\r
+ WDATAI_0 : in std_logic;\r
+ RDI : in std_logic;\r
+ WSTBI : in std_logic;\r
+\r
+ CS_CHIF_0 : in std_logic;\r
+ CS_CHIF_1 : in std_logic;\r
+ CS_CHIF_2 : in std_logic;\r
+ CS_CHIF_3 : in std_logic;\r
+ CS_QIF : in std_logic;\r
+\r
+ QUAD_ID_1 : in std_logic;\r
+ QUAD_ID_0 : in std_logic;\r
+\r
+ FF_SYSCLK_P1 : out std_logic;\r
+\r
+ FF_SYSCLK0 : out std_logic;\r
+ FF_SYSCLK1 : out std_logic;\r
+ FF_SYSCLK2 : out std_logic;\r
+ FF_SYSCLK3 : out std_logic;\r
+\r
+ FF_RXCLK_P1 : out std_logic;\r
+ FF_RXCLK_P2 : out std_logic;\r
+\r
+ FF_RXCLK0 : out std_logic;\r
+ FF_RXCLK1 : out std_logic;\r
+ FF_RXCLK2 : out std_logic;\r
+ FF_RXCLK3 : out std_logic;\r
+\r
+ QUAD_CLK : out std_logic;\r
+\r
+ GRP_CLK_P1_3 : in std_logic;\r
+ GRP_CLK_P1_2 : in std_logic;\r
+ GRP_CLK_P1_1 : in std_logic;\r
+ GRP_CLK_P1_0 : in std_logic;\r
+\r
+ GRP_CLK_P2_3 : in std_logic;\r
+ GRP_CLK_P2_2 : in std_logic;\r
+ GRP_CLK_P2_1 : in std_logic;\r
+ GRP_CLK_P2_0 : in std_logic;\r
+\r
+ GRP_START_3 : in std_logic;\r
+ GRP_START_2 : in std_logic;\r
+ GRP_START_1 : in std_logic;\r
+ GRP_START_0 : in std_logic;\r
+\r
+ GRP_DONE_3 : in std_logic;\r
+ GRP_DONE_2 : in std_logic;\r
+ GRP_DONE_1 : in std_logic;\r
+ GRP_DONE_0 : in std_logic;\r
+\r
+ GRP_DESKEW_ERROR_3 : in std_logic;\r
+ GRP_DESKEW_ERROR_2 : in std_logic;\r
+ GRP_DESKEW_ERROR_1 : in std_logic;\r
+ GRP_DESKEW_ERROR_0 : in std_logic;\r
+\r
+ IQA_START_LS : out std_logic;\r
+ IQA_DONE_LS : out std_logic;\r
+ IQA_AND_FP1_LS : out std_logic;\r
+ IQA_AND_FP0_LS : out std_logic;\r
+ IQA_OR_FP1_LS : out std_logic;\r
+ IQA_OR_FP0_LS : out std_logic;\r
+ IQA_RST_N : out std_logic;\r
+\r
+ FF_TCLK0 : in std_logic;\r
+ FF_TCLK1 : in std_logic;\r
+ FF_TCLK2 : in std_logic;\r
+ FF_TCLK3 : in std_logic;\r
+\r
+ FF_RCLK0 : in std_logic;\r
+ FF_RCLK1 : in std_logic;\r
+ FF_RCLK2 : in std_logic;\r
+ FF_RCLK3 : in std_logic;\r
+ TCK_FMACP : in std_logic;\r
+\r
+ FF_TXD_0_23 : in std_logic;\r
+ FF_TXD_0_22 : in std_logic;\r
+ FF_TXD_0_21 : in std_logic;\r
+ FF_TXD_0_20 : in std_logic;\r
+ FF_TXD_0_19 : in std_logic;\r
+ FF_TXD_0_18 : in std_logic;\r
+ FF_TXD_0_17 : in std_logic;\r
+ FF_TXD_0_16 : in std_logic;\r
+ FF_TXD_0_15 : in std_logic;\r
+ FF_TXD_0_14 : in std_logic;\r
+ FF_TXD_0_13 : in std_logic;\r
+ FF_TXD_0_12 : in std_logic;\r
+ FF_TXD_0_11 : in std_logic;\r
+ FF_TXD_0_10 : in std_logic;\r
+ FF_TXD_0_9 : in std_logic;\r
+ FF_TXD_0_8 : in std_logic;\r
+ FF_TXD_0_7 : in std_logic;\r
+ FF_TXD_0_6 : in std_logic;\r
+ FF_TXD_0_5 : in std_logic;\r
+ FF_TXD_0_4 : in std_logic;\r
+ FF_TXD_0_3 : in std_logic;\r
+ FF_TXD_0_2 : in std_logic;\r
+ FF_TXD_0_1 : in std_logic;\r
+ FF_TXD_0_0 : in std_logic;\r
+ FB_RXD_0_23 : out std_logic;\r
+ FB_RXD_0_22 : out std_logic;\r
+ FB_RXD_0_21 : out std_logic;\r
+ FB_RXD_0_20 : out std_logic;\r
+ FB_RXD_0_19 : out std_logic;\r
+ FB_RXD_0_18 : out std_logic;\r
+ FB_RXD_0_17 : out std_logic;\r
+ FB_RXD_0_16 : out std_logic;\r
+ FB_RXD_0_15 : out std_logic;\r
+ FB_RXD_0_14 : out std_logic;\r
+ FB_RXD_0_13 : out std_logic;\r
+ FB_RXD_0_12 : out std_logic;\r
+ FB_RXD_0_11 : out std_logic;\r
+ FB_RXD_0_10 : out std_logic;\r
+ FB_RXD_0_9 : out std_logic;\r
+ FB_RXD_0_8 : out std_logic;\r
+ FB_RXD_0_7 : out std_logic;\r
+ FB_RXD_0_6 : out std_logic;\r
+ FB_RXD_0_5 : out std_logic;\r
+ FB_RXD_0_4 : out std_logic;\r
+ FB_RXD_0_3 : out std_logic;\r
+ FB_RXD_0_2 : out std_logic;\r
+ FB_RXD_0_1 : out std_logic;\r
+ FB_RXD_0_0 : out std_logic;\r
+ FF_TXD_1_23 : in std_logic;\r
+ FF_TXD_1_22 : in std_logic;\r
+ FF_TXD_1_21 : in std_logic;\r
+ FF_TXD_1_20 : in std_logic;\r
+ FF_TXD_1_19 : in std_logic;\r
+ FF_TXD_1_18 : in std_logic;\r
+ FF_TXD_1_17 : in std_logic;\r
+ FF_TXD_1_16 : in std_logic;\r
+ FF_TXD_1_15 : in std_logic;\r
+ FF_TXD_1_14 : in std_logic;\r
+ FF_TXD_1_13 : in std_logic;\r
+ FF_TXD_1_12 : in std_logic;\r
+ FF_TXD_1_11 : in std_logic;\r
+ FF_TXD_1_10 : in std_logic;\r
+ FF_TXD_1_9 : in std_logic;\r
+ FF_TXD_1_8 : in std_logic;\r
+ FF_TXD_1_7 : in std_logic;\r
+ FF_TXD_1_6 : in std_logic;\r
+ FF_TXD_1_5 : in std_logic;\r
+ FF_TXD_1_4 : in std_logic;\r
+ FF_TXD_1_3 : in std_logic;\r
+ FF_TXD_1_2 : in std_logic;\r
+ FF_TXD_1_1 : in std_logic;\r
+ FF_TXD_1_0 : in std_logic;\r
+ FB_RXD_1_23 : out std_logic;\r
+ FB_RXD_1_22 : out std_logic;\r
+ FB_RXD_1_21 : out std_logic;\r
+ FB_RXD_1_20 : out std_logic;\r
+ FB_RXD_1_19 : out std_logic;\r
+ FB_RXD_1_18 : out std_logic;\r
+ FB_RXD_1_17 : out std_logic;\r
+ FB_RXD_1_16 : out std_logic;\r
+ FB_RXD_1_15 : out std_logic;\r
+ FB_RXD_1_14 : out std_logic;\r
+ FB_RXD_1_13 : out std_logic;\r
+ FB_RXD_1_12 : out std_logic;\r
+ FB_RXD_1_11 : out std_logic;\r
+ FB_RXD_1_10 : out std_logic;\r
+ FB_RXD_1_9 : out std_logic;\r
+ FB_RXD_1_8 : out std_logic;\r
+ FB_RXD_1_7 : out std_logic;\r
+ FB_RXD_1_6 : out std_logic;\r
+ FB_RXD_1_5 : out std_logic;\r
+ FB_RXD_1_4 : out std_logic;\r
+ FB_RXD_1_3 : out std_logic;\r
+ FB_RXD_1_2 : out std_logic;\r
+ FB_RXD_1_1 : out std_logic;\r
+ FB_RXD_1_0 : out std_logic;\r
+ FF_TXD_2_23 : in std_logic;\r
+ FF_TXD_2_22 : in std_logic;\r
+ FF_TXD_2_21 : in std_logic;\r
+ FF_TXD_2_20 : in std_logic;\r
+ FF_TXD_2_19 : in std_logic;\r
+ FF_TXD_2_18 : in std_logic;\r
+ FF_TXD_2_17 : in std_logic;\r
+ FF_TXD_2_16 : in std_logic;\r
+ FF_TXD_2_15 : in std_logic;\r
+ FF_TXD_2_14 : in std_logic;\r
+ FF_TXD_2_13 : in std_logic;\r
+ FF_TXD_2_12 : in std_logic;\r
+ FF_TXD_2_11 : in std_logic;\r
+ FF_TXD_2_10 : in std_logic;\r
+ FF_TXD_2_9 : in std_logic;\r
+ FF_TXD_2_8 : in std_logic;\r
+ FF_TXD_2_7 : in std_logic;\r
+ FF_TXD_2_6 : in std_logic;\r
+ FF_TXD_2_5 : in std_logic;\r
+ FF_TXD_2_4 : in std_logic;\r
+ FF_TXD_2_3 : in std_logic;\r
+ FF_TXD_2_2 : in std_logic;\r
+ FF_TXD_2_1 : in std_logic;\r
+ FF_TXD_2_0 : in std_logic;\r
+ FB_RXD_2_23 : out std_logic;\r
+ FB_RXD_2_22 : out std_logic;\r
+ FB_RXD_2_21 : out std_logic;\r
+ FB_RXD_2_20 : out std_logic;\r
+ FB_RXD_2_19 : out std_logic;\r
+ FB_RXD_2_18 : out std_logic;\r
+ FB_RXD_2_17 : out std_logic;\r
+ FB_RXD_2_16 : out std_logic;\r
+ FB_RXD_2_15 : out std_logic;\r
+ FB_RXD_2_14 : out std_logic;\r
+ FB_RXD_2_13 : out std_logic;\r
+ FB_RXD_2_12 : out std_logic;\r
+ FB_RXD_2_11 : out std_logic;\r
+ FB_RXD_2_10 : out std_logic;\r
+ FB_RXD_2_9 : out std_logic;\r
+ FB_RXD_2_8 : out std_logic;\r
+ FB_RXD_2_7 : out std_logic;\r
+ FB_RXD_2_6 : out std_logic;\r
+ FB_RXD_2_5 : out std_logic;\r
+ FB_RXD_2_4 : out std_logic;\r
+ FB_RXD_2_3 : out std_logic;\r
+ FB_RXD_2_2 : out std_logic;\r
+ FB_RXD_2_1 : out std_logic;\r
+ FB_RXD_2_0 : out std_logic;\r
+ FF_TXD_3_23 : in std_logic;\r
+ FF_TXD_3_22 : in std_logic;\r
+ FF_TXD_3_21 : in std_logic;\r
+ FF_TXD_3_20 : in std_logic;\r
+ FF_TXD_3_19 : in std_logic;\r
+ FF_TXD_3_18 : in std_logic;\r
+ FF_TXD_3_17 : in std_logic;\r
+ FF_TXD_3_16 : in std_logic;\r
+ FF_TXD_3_15 : in std_logic;\r
+ FF_TXD_3_14 : in std_logic;\r
+ FF_TXD_3_13 : in std_logic;\r
+ FF_TXD_3_12 : in std_logic;\r
+ FF_TXD_3_11 : in std_logic;\r
+ FF_TXD_3_10 : in std_logic;\r
+ FF_TXD_3_9 : in std_logic;\r
+ FF_TXD_3_8 : in std_logic;\r
+ FF_TXD_3_7 : in std_logic;\r
+ FF_TXD_3_6 : in std_logic;\r
+ FF_TXD_3_5 : in std_logic;\r
+ FF_TXD_3_4 : in std_logic;\r
+ FF_TXD_3_3 : in std_logic;\r
+ FF_TXD_3_2 : in std_logic;\r
+ FF_TXD_3_1 : in std_logic;\r
+ FF_TXD_3_0 : in std_logic;\r
+ FB_RXD_3_23 : out std_logic;\r
+ FB_RXD_3_22 : out std_logic;\r
+ FB_RXD_3_21 : out std_logic;\r
+ FB_RXD_3_20 : out std_logic;\r
+ FB_RXD_3_19 : out std_logic;\r
+ FB_RXD_3_18 : out std_logic;\r
+ FB_RXD_3_17 : out std_logic;\r
+ FB_RXD_3_16 : out std_logic;\r
+ FB_RXD_3_15 : out std_logic;\r
+ FB_RXD_3_14 : out std_logic;\r
+ FB_RXD_3_13 : out std_logic;\r
+ FB_RXD_3_12 : out std_logic;\r
+ FB_RXD_3_11 : out std_logic;\r
+ FB_RXD_3_10 : out std_logic;\r
+ FB_RXD_3_9 : out std_logic;\r
+ FB_RXD_3_8 : out std_logic;\r
+ FB_RXD_3_7 : out std_logic;\r
+ FB_RXD_3_6 : out std_logic;\r
+ FB_RXD_3_5 : out std_logic;\r
+ FB_RXD_3_4 : out std_logic;\r
+ FB_RXD_3_3 : out std_logic;\r
+ FB_RXD_3_2 : out std_logic;\r
+ FB_RXD_3_1 : out std_logic;\r
+ FB_RXD_3_0 : out std_logic;\r
+ TCK_FMAC : out std_logic;\r
+ BS4PAD_0 : out std_logic;\r
+ BS4PAD_1 : out std_logic;\r
+ BS4PAD_2 : out std_logic;\r
+ BS4PAD_3 : out std_logic;\r
+ COUT_21 : out std_logic;\r
+ COUT_20 : out std_logic;\r
+ COUT_19 : out std_logic;\r
+ COUT_18 : out std_logic;\r
+ COUT_17 : out std_logic;\r
+ COUT_16 : out std_logic;\r
+ COUT_15 : out std_logic;\r
+ COUT_14 : out std_logic;\r
+ COUT_13 : out std_logic;\r
+ COUT_12 : out std_logic;\r
+ COUT_11 : out std_logic;\r
+ COUT_10 : out std_logic;\r
+ COUT_9 : out std_logic;\r
+ COUT_8 : out std_logic;\r
+ COUT_7 : out std_logic;\r
+ COUT_6 : out std_logic;\r
+ COUT_5 : out std_logic;\r
+ COUT_4 : out std_logic;\r
+ COUT_3 : out std_logic;\r
+ COUT_2 : out std_logic;\r
+ COUT_1 : out std_logic;\r
+ COUT_0 : out std_logic;\r
+ CIN_12 : in std_logic;\r
+ CIN_11 : in std_logic;\r
+ CIN_10 : in std_logic;\r
+ CIN_9 : in std_logic;\r
+ CIN_8 : in std_logic;\r
+ CIN_7 : in std_logic;\r
+ CIN_6 : in std_logic;\r
+ CIN_5 : in std_logic;\r
+ CIN_4 : in std_logic;\r
+ CIN_3 : in std_logic;\r
+ CIN_2 : in std_logic;\r
+ CIN_1 : in std_logic;\r
+ CIN_0 : in std_logic;\r
+ TESTCLK_MACO : in std_logic\r
+);\r
+end component;\r
+\r
+begin\r
+\r
+PCSA_sim_inst : PCSA_sim \r
+generic map (\r
+ CONFIG_FILE => CONFIG_FILE)\r
+port map (\r
+ HDINP0 => HDINP0,\r
+ HDINN0 => HDINN0,\r
+ HDINP1 => HDINP1,\r
+ HDINN1 => HDINN1,\r
+ HDINP2 => HDINP2,\r
+ HDINN2 => HDINN2,\r
+ HDINP3 => HDINP3,\r
+ HDINN3 => HDINN3,\r
+ HDOUTP0 => HDOUTP0,\r
+ HDOUTN0 => HDOUTN0,\r
+ HDOUTP1 => HDOUTP1,\r
+ HDOUTN1 => HDOUTN1,\r
+ HDOUTP2 => HDOUTP2,\r
+ HDOUTN2 => HDOUTN2,\r
+ HDOUTP3 => HDOUTP3,\r
+ HDOUTN3 => HDOUTN3,\r
+ REFCLKP => REFCLKP,\r
+ REFCLKN => REFCLKN,\r
+ RXREFCLKP => RXREFCLKP,\r
+ RXREFCLKN => RXREFCLKN,\r
+ FFC_QUAD_RST => FFC_QUAD_RST,\r
+ FFC_MACRO_RST => FFC_MACRO_RST,\r
+ FFC_LANE_TX_RST0 => FFC_LANE_TX_RST0,\r
+ FFC_LANE_TX_RST1 => FFC_LANE_TX_RST1,\r
+ FFC_LANE_TX_RST2 => FFC_LANE_TX_RST2,\r
+ FFC_LANE_TX_RST3 => FFC_LANE_TX_RST3,\r
+ FFC_LANE_RX_RST0 => FFC_LANE_RX_RST0,\r
+ FFC_LANE_RX_RST1 => FFC_LANE_RX_RST1,\r
+ FFC_LANE_RX_RST2 => FFC_LANE_RX_RST2,\r
+ FFC_LANE_RX_RST3 => FFC_LANE_RX_RST3,\r
+ FFC_PCIE_EI_EN_0 => FFC_PCIE_EI_EN_0,\r
+ FFC_PCIE_EI_EN_1 => FFC_PCIE_EI_EN_1,\r
+ FFC_PCIE_EI_EN_2 => FFC_PCIE_EI_EN_2,\r
+ FFC_PCIE_EI_EN_3 => FFC_PCIE_EI_EN_3,\r
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,\r
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,\r
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,\r
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,\r
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,\r
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,\r
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,\r
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,\r
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,\r
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,\r
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,\r
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,\r
+ FFC_PCIE_TX_0 => FFC_PCIE_TX_0,\r
+ FFC_PCIE_TX_1 => FFC_PCIE_TX_1,\r
+ FFC_PCIE_TX_2 => FFC_PCIE_TX_2,\r
+ FFC_PCIE_TX_3 => FFC_PCIE_TX_3,\r
+ FFC_PCIE_RX_0 => FFC_PCIE_RX_0,\r
+ FFC_PCIE_RX_1 => FFC_PCIE_RX_1,\r
+ FFC_PCIE_RX_2 => FFC_PCIE_RX_2,\r
+ FFC_PCIE_RX_3 => FFC_PCIE_RX_3,\r
+ FFC_SD_0 => FFC_SD_0,\r
+ FFC_SD_1 => FFC_SD_1,\r
+ FFC_SD_2 => FFC_SD_2,\r
+ FFC_SD_3 => FFC_SD_3,\r
+ FFC_EN_CGA_0 => FFC_EN_CGA_0,\r
+ FFC_EN_CGA_1 => FFC_EN_CGA_1,\r
+ FFC_EN_CGA_2 => FFC_EN_CGA_2,\r
+ FFC_EN_CGA_3 => FFC_EN_CGA_3,\r
+ FFC_ALIGN_EN_0 => FFC_ALIGN_EN_0,\r
+ FFC_ALIGN_EN_1 => FFC_ALIGN_EN_1,\r
+ FFC_ALIGN_EN_2 => FFC_ALIGN_EN_2,\r
+ FFC_ALIGN_EN_3 => FFC_ALIGN_EN_3,\r
+ FFC_AB_RESET => FFC_AB_RESET,\r
+ FFC_CD_RESET => FFC_CD_RESET,\r
+ FFS_LS_STATUS_0 => FFS_LS_STATUS_0,\r
+ FFS_LS_STATUS_1 => FFS_LS_STATUS_1,\r
+ FFS_LS_STATUS_2 => FFS_LS_STATUS_2,\r
+ FFS_LS_STATUS_3 => FFS_LS_STATUS_3,\r
+ FFS_AB_STATUS => FFS_AB_STATUS,\r
+ FFS_CD_STATUS => FFS_CD_STATUS,\r
+ FFS_AB_ALIGNED => FFS_AB_ALIGNED,\r
+ FFS_CD_ALIGNED => FFS_CD_ALIGNED,\r
+ FFS_AB_FAILED => FFS_AB_FAILED,\r
+ FFS_CD_FAILED => FFS_CD_FAILED,\r
+ FFS_RLOS_LO0 => FFS_RLOS_LO0,\r
+ FFS_RLOS_LO1 => FFS_RLOS_LO1,\r
+ FFS_RLOS_LO2 => FFS_RLOS_LO2,\r
+ FFS_RLOS_LO3 => FFS_RLOS_LO3,\r
+ FFC_FB_LB_0 => FFC_FB_LB_0,\r
+ FFC_FB_LB_1 => FFC_FB_LB_1,\r
+ FFC_FB_LB_2 => FFC_FB_LB_2,\r
+ FFC_FB_LB_3 => FFC_FB_LB_3,\r
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,\r
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,\r
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,\r
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,\r
+ FFS_CC_ORUN_0 => FFS_CC_ORUN_0,\r
+ FFS_CC_ORUN_1 => FFS_CC_ORUN_1,\r
+ FFS_CC_ORUN_2 => FFS_CC_ORUN_2,\r
+ FFS_CC_ORUN_3 => FFS_CC_ORUN_3,\r
+ FFS_CC_URUN_0 => FFS_CC_URUN_0,\r
+ FFS_CC_URUN_1 => FFS_CC_URUN_1,\r
+ FFS_CC_URUN_2 => FFS_CC_URUN_2,\r
+ FFS_CC_URUN_3 => FFS_CC_URUN_3,\r
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,\r
+ FFC_CK_CORE_RX => FFC_CK_CORE_RX,\r
+ BS4PAD_0 => BS4PAD_0,\r
+ BS4PAD_1 => BS4PAD_1,\r
+ BS4PAD_2 => BS4PAD_2,\r
+ BS4PAD_3 => BS4PAD_3,\r
+ RDATAO_7 => RDATAO_7,\r
+ RDATAO_6 => RDATAO_6,\r
+ RDATAO_5 => RDATAO_5,\r
+ RDATAO_4 => RDATAO_4,\r
+ RDATAO_3 => RDATAO_3,\r
+ RDATAO_2 => RDATAO_2,\r
+ RDATAO_1 => RDATAO_1,\r
+ RDATAO_0 => RDATAO_0,\r
+ INTO => INTO,\r
+ ADDRI_7 => ADDRI_7,\r
+ ADDRI_6 => ADDRI_6,\r
+ ADDRI_5 => ADDRI_5,\r
+ ADDRI_4 => ADDRI_4,\r
+ ADDRI_3 => ADDRI_3,\r
+ ADDRI_2 => ADDRI_2,\r
+ ADDRI_1 => ADDRI_1,\r
+ ADDRI_0 => ADDRI_0,\r
+ WDATAI_7 => WDATAI_7,\r
+ WDATAI_6 => WDATAI_6,\r
+ WDATAI_5 => WDATAI_5,\r
+ WDATAI_4 => WDATAI_4,\r
+ WDATAI_3 => WDATAI_3,\r
+ WDATAI_2 => WDATAI_2,\r
+ WDATAI_1 => WDATAI_1,\r
+ WDATAI_0 => WDATAI_0,\r
+ RDI => RDI,\r
+ WSTBI => WSTBI,\r
+ CS_CHIF_0 => CS_CHIF_0,\r
+ CS_CHIF_1 => CS_CHIF_1,\r
+ CS_CHIF_2 => CS_CHIF_2,\r
+ CS_CHIF_3 => CS_CHIF_3,\r
+ CS_QIF => CS_QIF,\r
+ QUAD_ID_1 => QUAD_ID_1,\r
+ QUAD_ID_0 => QUAD_ID_0,\r
+ FF_SYSCLK_P1 => FF_SYSCLK_P1,\r
+ FF_SYSCLK0 => FF_SYSCLK0,\r
+ FF_SYSCLK1 => FF_SYSCLK1,\r
+ FF_SYSCLK2 => FF_SYSCLK2,\r
+ FF_SYSCLK3 => FF_SYSCLK3,\r
+ FF_RXCLK_P1 => FF_RXCLK_P1,\r
+ FF_RXCLK_P2 => FF_RXCLK_P2,\r
+ FF_RXCLK0 => FF_RXCLK0,\r
+ FF_RXCLK1 => FF_RXCLK1,\r
+ FF_RXCLK2 => FF_RXCLK2,\r
+ FF_RXCLK3 => FF_RXCLK3,\r
+ QUAD_CLK => QUAD_CLK,\r
+ GRP_CLK_P1_3 => GRP_CLK_P1_3,\r
+ GRP_CLK_P1_2 => GRP_CLK_P1_2,\r
+ GRP_CLK_P1_1 => GRP_CLK_P1_1,\r
+ GRP_CLK_P1_0 => GRP_CLK_P1_0,\r
+ GRP_CLK_P2_3 => GRP_CLK_P2_3,\r
+ GRP_CLK_P2_2 => GRP_CLK_P2_2,\r
+ GRP_CLK_P2_1 => GRP_CLK_P2_1,\r
+ GRP_CLK_P2_0 => GRP_CLK_P2_0,\r
+ GRP_START_3 => GRP_START_3,\r
+ GRP_START_2 => GRP_START_2,\r
+ GRP_START_1 => GRP_START_1,\r
+ GRP_START_0 => GRP_START_0,\r
+ GRP_DONE_3 => GRP_DONE_3,\r
+ GRP_DONE_2 => GRP_DONE_2,\r
+ GRP_DONE_1 => GRP_DONE_1,\r
+ GRP_DONE_0 => GRP_DONE_0,\r
+ GRP_DESKEW_ERROR_3 => GRP_DESKEW_ERROR_3,\r
+ GRP_DESKEW_ERROR_2 => GRP_DESKEW_ERROR_2,\r
+ GRP_DESKEW_ERROR_1 => GRP_DESKEW_ERROR_1,\r
+ GRP_DESKEW_ERROR_0 => GRP_DESKEW_ERROR_0,\r
+ IQA_START_LS => IQA_START_LS,\r
+ IQA_DONE_LS => IQA_DONE_LS,\r
+ IQA_AND_FP1_LS => IQA_AND_FP1_LS,\r
+ IQA_AND_FP0_LS => IQA_AND_FP0_LS,\r
+ IQA_OR_FP1_LS => IQA_OR_FP1_LS,\r
+ IQA_OR_FP0_LS => IQA_OR_FP0_LS,\r
+ IQA_RST_N => IQA_RST_N,\r
+ FF_TCLK0 => FF_TCLK0,\r
+ FF_TCLK1 => FF_TCLK1,\r
+ FF_TCLK2 => FF_TCLK2,\r
+ FF_TCLK3 => FF_TCLK3,\r
+ FF_RCLK0 => FF_RCLK0,\r
+ FF_RCLK1 => FF_RCLK1,\r
+ FF_RCLK2 => FF_RCLK2,\r
+ FF_RCLK3 => FF_RCLK3,\r
+ TCK_FMACP => TCK_FMACP,\r
+ FF_TXD_0_23 => FF_TXD_0_23,\r
+ FF_TXD_0_22 => FF_TXD_0_22,\r
+ FF_TXD_0_21 => FF_TXD_0_21,\r
+ FF_TXD_0_20 => FF_TXD_0_20,\r
+ FF_TXD_0_19 => FF_TXD_0_19,\r
+ FF_TXD_0_18 => FF_TXD_0_18,\r
+ FF_TXD_0_17 => FF_TXD_0_17,\r
+ FF_TXD_0_16 => FF_TXD_0_16,\r
+ FF_TXD_0_15 => FF_TXD_0_15,\r
+ FF_TXD_0_14 => FF_TXD_0_14,\r
+ FF_TXD_0_13 => FF_TXD_0_13,\r
+ FF_TXD_0_12 => FF_TXD_0_12,\r
+ FF_TXD_0_11 => FF_TXD_0_11,\r
+ FF_TXD_0_10 => FF_TXD_0_10,\r
+ FF_TXD_0_9 => FF_TXD_0_9,\r
+ FF_TXD_0_8 => FF_TXD_0_8,\r
+ FF_TXD_0_7 => FF_TXD_0_7,\r
+ FF_TXD_0_6 => FF_TXD_0_6,\r
+ FF_TXD_0_5 => FF_TXD_0_5,\r
+ FF_TXD_0_4 => FF_TXD_0_4,\r
+ FF_TXD_0_3 => FF_TXD_0_3,\r
+ FF_TXD_0_2 => FF_TXD_0_2,\r
+ FF_TXD_0_1 => FF_TXD_0_1,\r
+ FF_TXD_0_0 => FF_TXD_0_0,\r
+ FB_RXD_0_23 => FB_RXD_0_23,\r
+ FB_RXD_0_22 => FB_RXD_0_22,\r
+ FB_RXD_0_21 => FB_RXD_0_21,\r
+ FB_RXD_0_20 => FB_RXD_0_20,\r
+ FB_RXD_0_19 => FB_RXD_0_19,\r
+ FB_RXD_0_18 => FB_RXD_0_18,\r
+ FB_RXD_0_17 => FB_RXD_0_17,\r
+ FB_RXD_0_16 => FB_RXD_0_16,\r
+ FB_RXD_0_15 => FB_RXD_0_15,\r
+ FB_RXD_0_14 => FB_RXD_0_14,\r
+ FB_RXD_0_13 => FB_RXD_0_13,\r
+ FB_RXD_0_12 => FB_RXD_0_12,\r
+ FB_RXD_0_11 => FB_RXD_0_11,\r
+ FB_RXD_0_10 => FB_RXD_0_10,\r
+ FB_RXD_0_9 => FB_RXD_0_9,\r
+ FB_RXD_0_8 => FB_RXD_0_8,\r
+ FB_RXD_0_7 => FB_RXD_0_7,\r
+ FB_RXD_0_6 => FB_RXD_0_6,\r
+ FB_RXD_0_5 => FB_RXD_0_5,\r
+ FB_RXD_0_4 => FB_RXD_0_4,\r
+ FB_RXD_0_3 => FB_RXD_0_3,\r
+ FB_RXD_0_2 => FB_RXD_0_2,\r
+ FB_RXD_0_1 => FB_RXD_0_1,\r
+ FB_RXD_0_0 => FB_RXD_0_0,\r
+ FF_TXD_1_23 => FF_TXD_1_23,\r
+ FF_TXD_1_22 => FF_TXD_1_22,\r
+ FF_TXD_1_21 => FF_TXD_1_21,\r
+ FF_TXD_1_20 => FF_TXD_1_20,\r
+ FF_TXD_1_19 => FF_TXD_1_19,\r
+ FF_TXD_1_18 => FF_TXD_1_18,\r
+ FF_TXD_1_17 => FF_TXD_1_17,\r
+ FF_TXD_1_16 => FF_TXD_1_16,\r
+ FF_TXD_1_15 => FF_TXD_1_15,\r
+ FF_TXD_1_14 => FF_TXD_1_14,\r
+ FF_TXD_1_13 => FF_TXD_1_13,\r
+ FF_TXD_1_12 => FF_TXD_1_12,\r
+ FF_TXD_1_11 => FF_TXD_1_11,\r
+ FF_TXD_1_10 => FF_TXD_1_10,\r
+ FF_TXD_1_9 => FF_TXD_1_9,\r
+ FF_TXD_1_8 => FF_TXD_1_8,\r
+ FF_TXD_1_7 => FF_TXD_1_7,\r
+ FF_TXD_1_6 => FF_TXD_1_6,\r
+ FF_TXD_1_5 => FF_TXD_1_5,\r
+ FF_TXD_1_4 => FF_TXD_1_4,\r
+ FF_TXD_1_3 => FF_TXD_1_3,\r
+ FF_TXD_1_2 => FF_TXD_1_2,\r
+ FF_TXD_1_1 => FF_TXD_1_1,\r
+ FF_TXD_1_0 => FF_TXD_1_0,\r
+ FB_RXD_1_23 => FB_RXD_1_23,\r
+ FB_RXD_1_22 => FB_RXD_1_22,\r
+ FB_RXD_1_21 => FB_RXD_1_21,\r
+ FB_RXD_1_20 => FB_RXD_1_20,\r
+ FB_RXD_1_19 => FB_RXD_1_19,\r
+ FB_RXD_1_18 => FB_RXD_1_18,\r
+ FB_RXD_1_17 => FB_RXD_1_17,\r
+ FB_RXD_1_16 => FB_RXD_1_16,\r
+ FB_RXD_1_15 => FB_RXD_1_15,\r
+ FB_RXD_1_14 => FB_RXD_1_14,\r
+ FB_RXD_1_13 => FB_RXD_1_13,\r
+ FB_RXD_1_12 => FB_RXD_1_12,\r
+ FB_RXD_1_11 => FB_RXD_1_11,\r
+ FB_RXD_1_10 => FB_RXD_1_10,\r
+ FB_RXD_1_9 => FB_RXD_1_9,\r
+ FB_RXD_1_8 => FB_RXD_1_8,\r
+ FB_RXD_1_7 => FB_RXD_1_7,\r
+ FB_RXD_1_6 => FB_RXD_1_6,\r
+ FB_RXD_1_5 => FB_RXD_1_5,\r
+ FB_RXD_1_4 => FB_RXD_1_4,\r
+ FB_RXD_1_3 => FB_RXD_1_3,\r
+ FB_RXD_1_2 => FB_RXD_1_2,\r
+ FB_RXD_1_1 => FB_RXD_1_1,\r
+ FB_RXD_1_0 => FB_RXD_1_0,\r
+ FF_TXD_2_23 => FF_TXD_2_23,\r
+ FF_TXD_2_22 => FF_TXD_2_22,\r
+ FF_TXD_2_21 => FF_TXD_2_21,\r
+ FF_TXD_2_20 => FF_TXD_2_20,\r
+ FF_TXD_2_19 => FF_TXD_2_19,\r
+ FF_TXD_2_18 => FF_TXD_2_18,\r
+ FF_TXD_2_17 => FF_TXD_2_17,\r
+ FF_TXD_2_16 => FF_TXD_2_16,\r
+ FF_TXD_2_15 => FF_TXD_2_15,\r
+ FF_TXD_2_14 => FF_TXD_2_14,\r
+ FF_TXD_2_13 => FF_TXD_2_13,\r
+ FF_TXD_2_12 => FF_TXD_2_12,\r
+ FF_TXD_2_11 => FF_TXD_2_11,\r
+ FF_TXD_2_10 => FF_TXD_2_10,\r
+ FF_TXD_2_9 => FF_TXD_2_9,\r
+ FF_TXD_2_8 => FF_TXD_2_8,\r
+ FF_TXD_2_7 => FF_TXD_2_7,\r
+ FF_TXD_2_6 => FF_TXD_2_6,\r
+ FF_TXD_2_5 => FF_TXD_2_5,\r
+ FF_TXD_2_4 => FF_TXD_2_4,\r
+ FF_TXD_2_3 => FF_TXD_2_3,\r
+ FF_TXD_2_2 => FF_TXD_2_2,\r
+ FF_TXD_2_1 => FF_TXD_2_1,\r
+ FF_TXD_2_0 => FF_TXD_2_0,\r
+ FB_RXD_2_23 => FB_RXD_2_23,\r
+ FB_RXD_2_22 => FB_RXD_2_22,\r
+ FB_RXD_2_21 => FB_RXD_2_21,\r
+ FB_RXD_2_20 => FB_RXD_2_20,\r
+ FB_RXD_2_19 => FB_RXD_2_19,\r
+ FB_RXD_2_18 => FB_RXD_2_18,\r
+ FB_RXD_2_17 => FB_RXD_2_17,\r
+ FB_RXD_2_16 => FB_RXD_2_16,\r
+ FB_RXD_2_15 => FB_RXD_2_15,\r
+ FB_RXD_2_14 => FB_RXD_2_14,\r
+ FB_RXD_2_13 => FB_RXD_2_13,\r
+ FB_RXD_2_12 => FB_RXD_2_12,\r
+ FB_RXD_2_11 => FB_RXD_2_11,\r
+ FB_RXD_2_10 => FB_RXD_2_10,\r
+ FB_RXD_2_9 => FB_RXD_2_9,\r
+ FB_RXD_2_8 => FB_RXD_2_8,\r
+ FB_RXD_2_7 => FB_RXD_2_7,\r
+ FB_RXD_2_6 => FB_RXD_2_6,\r
+ FB_RXD_2_5 => FB_RXD_2_5,\r
+ FB_RXD_2_4 => FB_RXD_2_4,\r
+ FB_RXD_2_3 => FB_RXD_2_3,\r
+ FB_RXD_2_2 => FB_RXD_2_2,\r
+ FB_RXD_2_1 => FB_RXD_2_1,\r
+ FB_RXD_2_0 => FB_RXD_2_0,\r
+ FF_TXD_3_23 => FF_TXD_3_23,\r
+ FF_TXD_3_22 => FF_TXD_3_22,\r
+ FF_TXD_3_21 => FF_TXD_3_21,\r
+ FF_TXD_3_20 => FF_TXD_3_20,\r
+ FF_TXD_3_19 => FF_TXD_3_19,\r
+ FF_TXD_3_18 => FF_TXD_3_18,\r
+ FF_TXD_3_17 => FF_TXD_3_17,\r
+ FF_TXD_3_16 => FF_TXD_3_16,\r
+ FF_TXD_3_15 => FF_TXD_3_15,\r
+ FF_TXD_3_14 => FF_TXD_3_14,\r
+ FF_TXD_3_13 => FF_TXD_3_13,\r
+ FF_TXD_3_12 => FF_TXD_3_12,\r
+ FF_TXD_3_11 => FF_TXD_3_11,\r
+ FF_TXD_3_10 => FF_TXD_3_10,\r
+ FF_TXD_3_9 => FF_TXD_3_9,\r
+ FF_TXD_3_8 => FF_TXD_3_8,\r
+ FF_TXD_3_7 => FF_TXD_3_7,\r
+ FF_TXD_3_6 => FF_TXD_3_6,\r
+ FF_TXD_3_5 => FF_TXD_3_5,\r
+ FF_TXD_3_4 => FF_TXD_3_4,\r
+ FF_TXD_3_3 => FF_TXD_3_3,\r
+ FF_TXD_3_2 => FF_TXD_3_2,\r
+ FF_TXD_3_1 => FF_TXD_3_1,\r
+ FF_TXD_3_0 => FF_TXD_3_0,\r
+ FB_RXD_3_23 => FB_RXD_3_23,\r
+ FB_RXD_3_22 => FB_RXD_3_22,\r
+ FB_RXD_3_21 => FB_RXD_3_21,\r
+ FB_RXD_3_20 => FB_RXD_3_20,\r
+ FB_RXD_3_19 => FB_RXD_3_19,\r
+ FB_RXD_3_18 => FB_RXD_3_18,\r
+ FB_RXD_3_17 => FB_RXD_3_17,\r
+ FB_RXD_3_16 => FB_RXD_3_16,\r
+ FB_RXD_3_15 => FB_RXD_3_15,\r
+ FB_RXD_3_14 => FB_RXD_3_14,\r
+ FB_RXD_3_13 => FB_RXD_3_13,\r
+ FB_RXD_3_12 => FB_RXD_3_12,\r
+ FB_RXD_3_11 => FB_RXD_3_11,\r
+ FB_RXD_3_10 => FB_RXD_3_10,\r
+ FB_RXD_3_9 => FB_RXD_3_9,\r
+ FB_RXD_3_8 => FB_RXD_3_8,\r
+ FB_RXD_3_7 => FB_RXD_3_7,\r
+ FB_RXD_3_6 => FB_RXD_3_6,\r
+ FB_RXD_3_5 => FB_RXD_3_5,\r
+ FB_RXD_3_4 => FB_RXD_3_4,\r
+ FB_RXD_3_3 => FB_RXD_3_3,\r
+ FB_RXD_3_2 => FB_RXD_3_2,\r
+ FB_RXD_3_1 => FB_RXD_3_1,\r
+ FB_RXD_3_0 => FB_RXD_3_0,\r
+ TCK_FMAC => TCK_FMAC,\r
+ COUT_21 => COUT_21,\r
+ COUT_20 => COUT_20,\r
+ COUT_19 => COUT_19,\r
+ COUT_18 => COUT_18,\r
+ COUT_17 => COUT_17,\r
+ COUT_16 => COUT_16,\r
+ COUT_15 => COUT_15,\r
+ COUT_14 => COUT_14,\r
+ COUT_13 => COUT_13,\r
+ COUT_12 => COUT_12,\r
+ COUT_11 => COUT_11,\r
+ COUT_10 => COUT_10,\r
+ COUT_9 => COUT_9,\r
+ COUT_8 => COUT_8,\r
+ COUT_7 => COUT_7,\r
+ COUT_6 => COUT_6,\r
+ COUT_5 => COUT_5,\r
+ COUT_4 => COUT_4,\r
+ COUT_3 => COUT_3,\r
+ COUT_2 => COUT_2,\r
+ COUT_1 => COUT_1,\r
+ COUT_0 => COUT_0,\r
+ CIN_12 => CIN_12,\r
+ CIN_11 => CIN_11,\r
+ CIN_10 => CIN_10,\r
+ CIN_9 => CIN_9,\r
+ CIN_8 => CIN_8,\r
+ CIN_7 => CIN_7,\r
+ CIN_6 => CIN_6,\r
+ CIN_5 => CIN_5,\r
+ CIN_4 => CIN_4,\r
+ CIN_3 => CIN_3,\r
+ CIN_2 => CIN_2,\r
+ CIN_1 => CIN_1,\r
+ CIN_0 => CIN_0,\r
+ TESTCLK_MACO => TESTCLK_MACO\r
+);\r
+\r
+end PCSA_arch;\r
+\r
+--synopsys translate_on\r
+\r
+--synopsys translate_off\r
+library SC;\r
+use SC.components.all;\r
+--synopsys translate_on\r
+\r
+library IEEE, STD;\r
+use IEEE.std_logic_1164.all;\r
+use STD.TEXTIO.all;\r
+\r
+\r
+entity serdes_gbe_0 is\r
+ GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0.txt");\r
+ port (\r
+-- serdes clk pins --\r
+ refclkp, refclkn : in std_logic;\r
+ rxrefclk, refclk : in std_logic;\r
+ hdinp_0, hdinn_0 : in std_logic;\r
+ hdoutp_0, hdoutn_0 : out std_logic;\r
+ tclk_0, rclk_0 : in std_logic;\r
+ tx_rst_0, rx_rst_0 : in std_logic;\r
+ ref_0_sclk : out std_logic;\r
+ txd_0 : in std_logic_vector (15 downto 0);\r
+ tx_en_0, tx_er_0, tx_crc_insert_0, tx_sfd_0 : in std_logic_vector (1 downto 0);\r
+ rxd_0 : out std_logic_vector (15 downto 0);\r
+ rx_dv_0, rx_er_0, rx_crc_eop_0, rx_sfd_0 : out std_logic_vector (1 downto 0);\r
+ lsm_en_0, felb_0 : in std_logic;\r
+ lsm_status_0, ctc_orun_0, ctc_urun_0 : out std_logic;\r
+\r
+\r
+\r
+ quad_rst, serdes_rst : in std_logic;\r
+ ref_pclk : out std_logic);\r
+\r
+end serdes_gbe_0;\r
+\r
+architecture serdes_gbe_0_arch of serdes_gbe_0 is\r
+\r
+component VLO\r
+port (\r
+ Z : out std_logic);\r
+end component;\r
+\r
+component VHI\r
+port (\r
+ Z : out std_logic);\r
+end component;\r
+\r
+component PCSA\r
+--synopsys translate_off\r
+GENERIC(\r
+ CONFIG_FILE : String\r
+ );\r
+--synopsys translate_on\r
+port (\r
+ HDINP0 : in std_logic;\r
+ HDINN0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ REFCLKP : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ RXREFCLKP : in std_logic;\r
+ RXREFCLKN : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+\r
+ FFC_LANE_TX_RST0 : in std_logic;\r
+ FFC_LANE_TX_RST1 : in std_logic;\r
+ FFC_LANE_TX_RST2 : in std_logic;\r
+ FFC_LANE_TX_RST3 : in std_logic;\r
+\r
+ FFC_LANE_RX_RST0 : in std_logic;\r
+ FFC_LANE_RX_RST1 : in std_logic;\r
+ FFC_LANE_RX_RST2 : in std_logic;\r
+ FFC_LANE_RX_RST3 : in std_logic;\r
+\r
+ FFC_PCIE_EI_EN_0 : in std_logic;\r
+ FFC_PCIE_EI_EN_1 : in std_logic;\r
+ FFC_PCIE_EI_EN_2 : in std_logic;\r
+ FFC_PCIE_EI_EN_3 : in std_logic;\r
+\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+\r
+ FFC_PCIE_TX_0 : in std_logic;\r
+ FFC_PCIE_TX_1 : in std_logic;\r
+ FFC_PCIE_TX_2 : in std_logic;\r
+ FFC_PCIE_TX_3 : in std_logic;\r
+\r
+ FFC_PCIE_RX_0 : in std_logic;\r
+ FFC_PCIE_RX_1 : in std_logic;\r
+ FFC_PCIE_RX_2 : in std_logic;\r
+ FFC_PCIE_RX_3 : in std_logic;\r
+\r
+ FFC_SD_0 : in std_logic;\r
+ FFC_SD_1 : in std_logic;\r
+ FFC_SD_2 : in std_logic;\r
+ FFC_SD_3 : in std_logic;\r
+\r
+ FFC_EN_CGA_0 : in std_logic;\r
+ FFC_EN_CGA_1 : in std_logic;\r
+ FFC_EN_CGA_2 : in std_logic;\r
+ FFC_EN_CGA_3 : in std_logic;\r
+\r
+ FFC_ALIGN_EN_0 : in std_logic;\r
+ FFC_ALIGN_EN_1 : in std_logic;\r
+ FFC_ALIGN_EN_2 : in std_logic;\r
+ FFC_ALIGN_EN_3 : in std_logic;\r
+\r
+ FFC_AB_RESET : in std_logic;\r
+ FFC_CD_RESET : in std_logic;\r
+\r
+ FFS_LS_STATUS_0 : out std_logic;\r
+ FFS_LS_STATUS_1 : out std_logic;\r
+ FFS_LS_STATUS_2 : out std_logic;\r
+ FFS_LS_STATUS_3 : out std_logic;\r
+\r
+ FFS_AB_STATUS : out std_logic;\r
+ FFS_CD_STATUS : out std_logic;\r
+\r
+ FFS_AB_ALIGNED : out std_logic;\r
+ FFS_CD_ALIGNED : out std_logic;\r
+\r
+ FFS_AB_FAILED : out std_logic;\r
+ FFS_CD_FAILED : out std_logic;\r
+\r
+ FFS_RLOS_LO0 : out std_logic;\r
+ FFS_RLOS_LO1 : out std_logic;\r
+ FFS_RLOS_LO2 : out std_logic;\r
+ FFS_RLOS_LO3 : out std_logic;\r
+\r
+ FFC_FB_LB_0 : in std_logic;\r
+ FFC_FB_LB_1 : in std_logic;\r
+ FFC_FB_LB_2 : in std_logic;\r
+ FFC_FB_LB_3 : in std_logic;\r
+\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+\r
+ FFS_CC_ORUN_0 : out std_logic;\r
+ FFS_CC_ORUN_1 : out std_logic;\r
+ FFS_CC_ORUN_2 : out std_logic;\r
+ FFS_CC_ORUN_3 : out std_logic;\r
+\r
+ FFS_CC_URUN_0 : out std_logic;\r
+ FFS_CC_URUN_1 : out std_logic;\r
+ FFS_CC_URUN_2 : out std_logic;\r
+ FFS_CC_URUN_3 : out std_logic;\r
+\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ RDATAO_7 : out std_logic;\r
+ RDATAO_6 : out std_logic;\r
+ RDATAO_5 : out std_logic;\r
+ RDATAO_4 : out std_logic;\r
+ RDATAO_3 : out std_logic;\r
+ RDATAO_2 : out std_logic;\r
+ RDATAO_1 : out std_logic;\r
+ RDATAO_0 : out std_logic;\r
+ INTO : out std_logic;\r
+\r
+ ADDRI_7 : in std_logic;\r
+ ADDRI_6 : in std_logic;\r
+ ADDRI_5 : in std_logic;\r
+ ADDRI_4 : in std_logic;\r
+ ADDRI_3 : in std_logic;\r
+ ADDRI_2 : in std_logic;\r
+ ADDRI_1 : in std_logic;\r
+ ADDRI_0 : in std_logic;\r
+ WDATAI_7 : in std_logic;\r
+ WDATAI_6 : in std_logic;\r
+ WDATAI_5 : in std_logic;\r
+ WDATAI_4 : in std_logic;\r
+ WDATAI_3 : in std_logic;\r
+ WDATAI_2 : in std_logic;\r
+ WDATAI_1 : in std_logic;\r
+ WDATAI_0 : in std_logic;\r
+ RDI : in std_logic;\r
+ WSTBI : in std_logic;\r
+\r
+ CS_CHIF_0 : in std_logic;\r
+ CS_CHIF_1 : in std_logic;\r
+ CS_CHIF_2 : in std_logic;\r
+ CS_CHIF_3 : in std_logic;\r
+ CS_QIF : in std_logic;\r
+\r
+ QUAD_ID_1 : in std_logic;\r
+ QUAD_ID_0 : in std_logic;\r
+\r
+ FF_SYSCLK_P1 : out std_logic;\r
+\r
+ FF_SYSCLK0 : out std_logic;\r
+ FF_SYSCLK1 : out std_logic;\r
+ FF_SYSCLK2 : out std_logic;\r
+ FF_SYSCLK3 : out std_logic;\r
+\r
+ FF_RXCLK_P1 : out std_logic;\r
+ FF_RXCLK_P2 : out std_logic;\r
+\r
+ FF_RXCLK0 : out std_logic;\r
+ FF_RXCLK1 : out std_logic;\r
+ FF_RXCLK2 : out std_logic;\r
+ FF_RXCLK3 : out std_logic;\r
+\r
+ QUAD_CLK : out std_logic;\r
+\r
+ GRP_CLK_P1_3 : in std_logic;\r
+ GRP_CLK_P1_2 : in std_logic;\r
+ GRP_CLK_P1_1 : in std_logic;\r
+ GRP_CLK_P1_0 : in std_logic;\r
+\r
+ GRP_CLK_P2_3 : in std_logic;\r
+ GRP_CLK_P2_2 : in std_logic;\r
+ GRP_CLK_P2_1 : in std_logic;\r
+ GRP_CLK_P2_0 : in std_logic;\r
+\r
+ GRP_START_3 : in std_logic;\r
+ GRP_START_2 : in std_logic;\r
+ GRP_START_1 : in std_logic;\r
+ GRP_START_0 : in std_logic;\r
+\r
+ GRP_DONE_3 : in std_logic;\r
+ GRP_DONE_2 : in std_logic;\r
+ GRP_DONE_1 : in std_logic;\r
+ GRP_DONE_0 : in std_logic;\r
+\r
+ GRP_DESKEW_ERROR_3 : in std_logic;\r
+ GRP_DESKEW_ERROR_2 : in std_logic;\r
+ GRP_DESKEW_ERROR_1 : in std_logic;\r
+ GRP_DESKEW_ERROR_0 : in std_logic;\r
+\r
+ IQA_START_LS : out std_logic;\r
+ IQA_DONE_LS : out std_logic;\r
+ IQA_AND_FP1_LS : out std_logic;\r
+ IQA_AND_FP0_LS : out std_logic;\r
+ IQA_OR_FP1_LS : out std_logic;\r
+ IQA_OR_FP0_LS : out std_logic;\r
+ IQA_RST_N : out std_logic;\r
+\r
+ FF_TCLK0 : in std_logic;\r
+ FF_TCLK1 : in std_logic;\r
+ FF_TCLK2 : in std_logic;\r
+ FF_TCLK3 : in std_logic;\r
+\r
+ FF_RCLK0 : in std_logic;\r
+ FF_RCLK1 : in std_logic;\r
+ FF_RCLK2 : in std_logic;\r
+ FF_RCLK3 : in std_logic;\r
+ TCK_FMACP : in std_logic;\r
+\r
+ FF_TXD_0_23 : in std_logic;\r
+ FF_TXD_0_22 : in std_logic;\r
+ FF_TXD_0_21 : in std_logic;\r
+ FF_TXD_0_20 : in std_logic;\r
+ FF_TXD_0_19 : in std_logic;\r
+ FF_TXD_0_18 : in std_logic;\r
+ FF_TXD_0_17 : in std_logic;\r
+ FF_TXD_0_16 : in std_logic;\r
+ FF_TXD_0_15 : in std_logic;\r
+ FF_TXD_0_14 : in std_logic;\r
+ FF_TXD_0_13 : in std_logic;\r
+ FF_TXD_0_12 : in std_logic;\r
+ FF_TXD_0_11 : in std_logic;\r
+ FF_TXD_0_10 : in std_logic;\r
+ FF_TXD_0_9 : in std_logic;\r
+ FF_TXD_0_8 : in std_logic;\r
+ FF_TXD_0_7 : in std_logic;\r
+ FF_TXD_0_6 : in std_logic;\r
+ FF_TXD_0_5 : in std_logic;\r
+ FF_TXD_0_4 : in std_logic;\r
+ FF_TXD_0_3 : in std_logic;\r
+ FF_TXD_0_2 : in std_logic;\r
+ FF_TXD_0_1 : in std_logic;\r
+ FF_TXD_0_0 : in std_logic;\r
+ FB_RXD_0_23 : out std_logic;\r
+ FB_RXD_0_22 : out std_logic;\r
+ FB_RXD_0_21 : out std_logic;\r
+ FB_RXD_0_20 : out std_logic;\r
+ FB_RXD_0_19 : out std_logic;\r
+ FB_RXD_0_18 : out std_logic;\r
+ FB_RXD_0_17 : out std_logic;\r
+ FB_RXD_0_16 : out std_logic;\r
+ FB_RXD_0_15 : out std_logic;\r
+ FB_RXD_0_14 : out std_logic;\r
+ FB_RXD_0_13 : out std_logic;\r
+ FB_RXD_0_12 : out std_logic;\r
+ FB_RXD_0_11 : out std_logic;\r
+ FB_RXD_0_10 : out std_logic;\r
+ FB_RXD_0_9 : out std_logic;\r
+ FB_RXD_0_8 : out std_logic;\r
+ FB_RXD_0_7 : out std_logic;\r
+ FB_RXD_0_6 : out std_logic;\r
+ FB_RXD_0_5 : out std_logic;\r
+ FB_RXD_0_4 : out std_logic;\r
+ FB_RXD_0_3 : out std_logic;\r
+ FB_RXD_0_2 : out std_logic;\r
+ FB_RXD_0_1 : out std_logic;\r
+ FB_RXD_0_0 : out std_logic;\r
+ FF_TXD_1_23 : in std_logic;\r
+ FF_TXD_1_22 : in std_logic;\r
+ FF_TXD_1_21 : in std_logic;\r
+ FF_TXD_1_20 : in std_logic;\r
+ FF_TXD_1_19 : in std_logic;\r
+ FF_TXD_1_18 : in std_logic;\r
+ FF_TXD_1_17 : in std_logic;\r
+ FF_TXD_1_16 : in std_logic;\r
+ FF_TXD_1_15 : in std_logic;\r
+ FF_TXD_1_14 : in std_logic;\r
+ FF_TXD_1_13 : in std_logic;\r
+ FF_TXD_1_12 : in std_logic;\r
+ FF_TXD_1_11 : in std_logic;\r
+ FF_TXD_1_10 : in std_logic;\r
+ FF_TXD_1_9 : in std_logic;\r
+ FF_TXD_1_8 : in std_logic;\r
+ FF_TXD_1_7 : in std_logic;\r
+ FF_TXD_1_6 : in std_logic;\r
+ FF_TXD_1_5 : in std_logic;\r
+ FF_TXD_1_4 : in std_logic;\r
+ FF_TXD_1_3 : in std_logic;\r
+ FF_TXD_1_2 : in std_logic;\r
+ FF_TXD_1_1 : in std_logic;\r
+ FF_TXD_1_0 : in std_logic;\r
+ FB_RXD_1_23 : out std_logic;\r
+ FB_RXD_1_22 : out std_logic;\r
+ FB_RXD_1_21 : out std_logic;\r
+ FB_RXD_1_20 : out std_logic;\r
+ FB_RXD_1_19 : out std_logic;\r
+ FB_RXD_1_18 : out std_logic;\r
+ FB_RXD_1_17 : out std_logic;\r
+ FB_RXD_1_16 : out std_logic;\r
+ FB_RXD_1_15 : out std_logic;\r
+ FB_RXD_1_14 : out std_logic;\r
+ FB_RXD_1_13 : out std_logic;\r
+ FB_RXD_1_12 : out std_logic;\r
+ FB_RXD_1_11 : out std_logic;\r
+ FB_RXD_1_10 : out std_logic;\r
+ FB_RXD_1_9 : out std_logic;\r
+ FB_RXD_1_8 : out std_logic;\r
+ FB_RXD_1_7 : out std_logic;\r
+ FB_RXD_1_6 : out std_logic;\r
+ FB_RXD_1_5 : out std_logic;\r
+ FB_RXD_1_4 : out std_logic;\r
+ FB_RXD_1_3 : out std_logic;\r
+ FB_RXD_1_2 : out std_logic;\r
+ FB_RXD_1_1 : out std_logic;\r
+ FB_RXD_1_0 : out std_logic;\r
+ FF_TXD_2_23 : in std_logic;\r
+ FF_TXD_2_22 : in std_logic;\r
+ FF_TXD_2_21 : in std_logic;\r
+ FF_TXD_2_20 : in std_logic;\r
+ FF_TXD_2_19 : in std_logic;\r
+ FF_TXD_2_18 : in std_logic;\r
+ FF_TXD_2_17 : in std_logic;\r
+ FF_TXD_2_16 : in std_logic;\r
+ FF_TXD_2_15 : in std_logic;\r
+ FF_TXD_2_14 : in std_logic;\r
+ FF_TXD_2_13 : in std_logic;\r
+ FF_TXD_2_12 : in std_logic;\r
+ FF_TXD_2_11 : in std_logic;\r
+ FF_TXD_2_10 : in std_logic;\r
+ FF_TXD_2_9 : in std_logic;\r
+ FF_TXD_2_8 : in std_logic;\r
+ FF_TXD_2_7 : in std_logic;\r
+ FF_TXD_2_6 : in std_logic;\r
+ FF_TXD_2_5 : in std_logic;\r
+ FF_TXD_2_4 : in std_logic;\r
+ FF_TXD_2_3 : in std_logic;\r
+ FF_TXD_2_2 : in std_logic;\r
+ FF_TXD_2_1 : in std_logic;\r
+ FF_TXD_2_0 : in std_logic;\r
+ FB_RXD_2_23 : out std_logic;\r
+ FB_RXD_2_22 : out std_logic;\r
+ FB_RXD_2_21 : out std_logic;\r
+ FB_RXD_2_20 : out std_logic;\r
+ FB_RXD_2_19 : out std_logic;\r
+ FB_RXD_2_18 : out std_logic;\r
+ FB_RXD_2_17 : out std_logic;\r
+ FB_RXD_2_16 : out std_logic;\r
+ FB_RXD_2_15 : out std_logic;\r
+ FB_RXD_2_14 : out std_logic;\r
+ FB_RXD_2_13 : out std_logic;\r
+ FB_RXD_2_12 : out std_logic;\r
+ FB_RXD_2_11 : out std_logic;\r
+ FB_RXD_2_10 : out std_logic;\r
+ FB_RXD_2_9 : out std_logic;\r
+ FB_RXD_2_8 : out std_logic;\r
+ FB_RXD_2_7 : out std_logic;\r
+ FB_RXD_2_6 : out std_logic;\r
+ FB_RXD_2_5 : out std_logic;\r
+ FB_RXD_2_4 : out std_logic;\r
+ FB_RXD_2_3 : out std_logic;\r
+ FB_RXD_2_2 : out std_logic;\r
+ FB_RXD_2_1 : out std_logic;\r
+ FB_RXD_2_0 : out std_logic;\r
+ FF_TXD_3_23 : in std_logic;\r
+ FF_TXD_3_22 : in std_logic;\r
+ FF_TXD_3_21 : in std_logic;\r
+ FF_TXD_3_20 : in std_logic;\r
+ FF_TXD_3_19 : in std_logic;\r
+ FF_TXD_3_18 : in std_logic;\r
+ FF_TXD_3_17 : in std_logic;\r
+ FF_TXD_3_16 : in std_logic;\r
+ FF_TXD_3_15 : in std_logic;\r
+ FF_TXD_3_14 : in std_logic;\r
+ FF_TXD_3_13 : in std_logic;\r
+ FF_TXD_3_12 : in std_logic;\r
+ FF_TXD_3_11 : in std_logic;\r
+ FF_TXD_3_10 : in std_logic;\r
+ FF_TXD_3_9 : in std_logic;\r
+ FF_TXD_3_8 : in std_logic;\r
+ FF_TXD_3_7 : in std_logic;\r
+ FF_TXD_3_6 : in std_logic;\r
+ FF_TXD_3_5 : in std_logic;\r
+ FF_TXD_3_4 : in std_logic;\r
+ FF_TXD_3_3 : in std_logic;\r
+ FF_TXD_3_2 : in std_logic;\r
+ FF_TXD_3_1 : in std_logic;\r
+ FF_TXD_3_0 : in std_logic;\r
+ FB_RXD_3_23 : out std_logic;\r
+ FB_RXD_3_22 : out std_logic;\r
+ FB_RXD_3_21 : out std_logic;\r
+ FB_RXD_3_20 : out std_logic;\r
+ FB_RXD_3_19 : out std_logic;\r
+ FB_RXD_3_18 : out std_logic;\r
+ FB_RXD_3_17 : out std_logic;\r
+ FB_RXD_3_16 : out std_logic;\r
+ FB_RXD_3_15 : out std_logic;\r
+ FB_RXD_3_14 : out std_logic;\r
+ FB_RXD_3_13 : out std_logic;\r
+ FB_RXD_3_12 : out std_logic;\r
+ FB_RXD_3_11 : out std_logic;\r
+ FB_RXD_3_10 : out std_logic;\r
+ FB_RXD_3_9 : out std_logic;\r
+ FB_RXD_3_8 : out std_logic;\r
+ FB_RXD_3_7 : out std_logic;\r
+ FB_RXD_3_6 : out std_logic;\r
+ FB_RXD_3_5 : out std_logic;\r
+ FB_RXD_3_4 : out std_logic;\r
+ FB_RXD_3_3 : out std_logic;\r
+ FB_RXD_3_2 : out std_logic;\r
+ FB_RXD_3_1 : out std_logic;\r
+ FB_RXD_3_0 : out std_logic;\r
+ TCK_FMAC : out std_logic;\r
+ BS4PAD_0 : out std_logic;\r
+ BS4PAD_1 : out std_logic;\r
+ BS4PAD_2 : out std_logic;\r
+ BS4PAD_3 : out std_logic;\r
+ COUT_21 : out std_logic;\r
+ COUT_20 : out std_logic;\r
+ COUT_19 : out std_logic;\r
+ COUT_18 : out std_logic;\r
+ COUT_17 : out std_logic;\r
+ COUT_16 : out std_logic;\r
+ COUT_15 : out std_logic;\r
+ COUT_14 : out std_logic;\r
+ COUT_13 : out std_logic;\r
+ COUT_12 : out std_logic;\r
+ COUT_11 : out std_logic;\r
+ COUT_10 : out std_logic;\r
+ COUT_9 : out std_logic;\r
+ COUT_8 : out std_logic;\r
+ COUT_7 : out std_logic;\r
+ COUT_6 : out std_logic;\r
+ COUT_5 : out std_logic;\r
+ COUT_4 : out std_logic;\r
+ COUT_3 : out std_logic;\r
+ COUT_2 : out std_logic;\r
+ COUT_1 : out std_logic;\r
+ COUT_0 : out std_logic;\r
+ CIN_12 : in std_logic;\r
+ CIN_11 : in std_logic;\r
+ CIN_10 : in std_logic;\r
+ CIN_9 : in std_logic;\r
+ CIN_8 : in std_logic;\r
+ CIN_7 : in std_logic;\r
+ CIN_6 : in std_logic;\r
+ CIN_5 : in std_logic;\r
+ CIN_4 : in std_logic;\r
+ CIN_3 : in std_logic;\r
+ CIN_2 : in std_logic;\r
+ CIN_1 : in std_logic;\r
+ CIN_0 : in std_logic;\r
+ TESTCLK_MACO : in std_logic\r
+);\r
+end component;\r
+ attribute IS_ASB: string;\r
+ attribute IS_ASB of PCSA_INST : label is "or5s00/data/or5s00.acd";\r
+ attribute CONFIG_FILE: string;\r
+ attribute CONFIG_FILE of PCSA_INST : label is USER_CONFIG_FILE;\r
+ attribute CH0_RX_MAXRATE: string;\r
+ attribute CH0_RX_MAXRATE of PCSA_INST : label is "RXF3";\r
+ attribute CH1_RX_MAXRATE: string;\r
+ attribute CH1_RX_MAXRATE of PCSA_INST : label is "RXF3";\r
+ attribute CH2_RX_MAXRATE: string;\r
+ attribute CH2_RX_MAXRATE of PCSA_INST : label is "RXF3";\r
+ attribute CH3_RX_MAXRATE: string;\r
+ attribute CH3_RX_MAXRATE of PCSA_INST : label is "RXF3";\r
+ attribute CH0_TX_MAXRATE: string;\r
+ attribute CH0_TX_MAXRATE of PCSA_INST : label is "TXF2";\r
+ attribute CH1_TX_MAXRATE: string;\r
+ attribute CH1_TX_MAXRATE of PCSA_INST : label is "TXF2";\r
+ attribute CH2_TX_MAXRATE: string;\r
+ attribute CH2_TX_MAXRATE of PCSA_INST : label is "TXF2";\r
+ attribute CH3_TX_MAXRATE: string;\r
+ attribute CH3_TX_MAXRATE of PCSA_INST : label is "TXF2";\r
+ attribute AMP_BOOST: string;\r
+ attribute AMP_BOOST of PCSA_INST : label is "DISABLED";\r
+ attribute black_box_pad_pin: string;\r
+ attribute black_box_pad_pin of PCSA : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN, RXREFCLKP, RXREFCLKN";\r
+\r
+signal fpsc_vlo : std_logic := '0';\r
+\r
+begin\r
+\r
+vlo_inst : VLO port map(Z => fpsc_vlo);\r
+\r
+-- pcs_quad instance\r
+PCSA_INST : PCSA\r
+--synopsys translate_off\r
+ generic map (CONFIG_FILE => USER_CONFIG_FILE)\r
+--synopsys translate_on\r
+port map ( \r
+ REFCLKP => refclkp,\r
+ REFCLKN => refclkn,\r
+ RXREFCLKP => fpsc_vlo,\r
+ RXREFCLKN => fpsc_vlo,\r
+ FFC_CK_CORE_RX => rxrefclk,\r
+ FFC_CK_CORE_TX => refclk,\r
+ CS_CHIF_0 => fpsc_vlo,\r
+ CS_CHIF_1 => fpsc_vlo,\r
+ CS_CHIF_2 => fpsc_vlo,\r
+ CS_CHIF_3 => fpsc_vlo,\r
+ CS_QIF => fpsc_vlo,\r
+ QUAD_ID_0 => fpsc_vlo,\r
+ QUAD_ID_1 => fpsc_vlo,\r
+ ADDRI_0 => fpsc_vlo,\r
+ ADDRI_1 => fpsc_vlo,\r
+ ADDRI_2 => fpsc_vlo,\r
+ ADDRI_3 => fpsc_vlo,\r
+ ADDRI_4 => fpsc_vlo,\r
+ ADDRI_5 => fpsc_vlo,\r
+ ADDRI_6 => fpsc_vlo,\r
+ ADDRI_7 => fpsc_vlo,\r
+ WDATAI_0 => fpsc_vlo,\r
+ WDATAI_1 => fpsc_vlo,\r
+ WDATAI_2 => fpsc_vlo,\r
+ WDATAI_3 => fpsc_vlo,\r
+ WDATAI_4 => fpsc_vlo,\r
+ WDATAI_5 => fpsc_vlo,\r
+ WDATAI_6 => fpsc_vlo,\r
+ WDATAI_7 => fpsc_vlo,\r
+ RDI => fpsc_vlo,\r
+ WSTBI => fpsc_vlo,\r
+ GRP_CLK_P1_0 => fpsc_vlo,\r
+ GRP_CLK_P1_1 => fpsc_vlo,\r
+ GRP_CLK_P1_2 => fpsc_vlo,\r
+ GRP_CLK_P1_3 => fpsc_vlo,\r
+ GRP_CLK_P2_0 => fpsc_vlo,\r
+ GRP_CLK_P2_1 => fpsc_vlo,\r
+ GRP_CLK_P2_2 => fpsc_vlo,\r
+ GRP_CLK_P2_3 => fpsc_vlo,\r
+ GRP_START_0 => fpsc_vlo,\r
+ GRP_START_1 => fpsc_vlo,\r
+ GRP_START_2 => fpsc_vlo,\r
+ GRP_START_3 => fpsc_vlo,\r
+ GRP_DONE_0 => fpsc_vlo,\r
+ GRP_DONE_1 => fpsc_vlo,\r
+ GRP_DONE_2 => fpsc_vlo,\r
+ GRP_DONE_3 => fpsc_vlo,\r
+ GRP_DESKEW_ERROR_0 => fpsc_vlo,\r
+ GRP_DESKEW_ERROR_1 => fpsc_vlo,\r
+ GRP_DESKEW_ERROR_2 => fpsc_vlo,\r
+ GRP_DESKEW_ERROR_3 => fpsc_vlo,\r
+-- to sysbusa\r
+ RDATAO_0 => open,\r
+ RDATAO_1 => open,\r
+ RDATAO_2 => open,\r
+ RDATAO_3 => open,\r
+ RDATAO_4 => open,\r
+ RDATAO_5 => open,\r
+ RDATAO_6 => open,\r
+ RDATAO_7 => open,\r
+ INTO => open,\r
+ QUAD_CLK => open,\r
+ IQA_START_LS => open,\r
+ IQA_DONE_LS => open,\r
+ IQA_AND_FP1_LS => open,\r
+ IQA_AND_FP0_LS => open,\r
+ IQA_OR_FP1_LS => open,\r
+ IQA_OR_FP0_LS => open,\r
+ IQA_RST_N => open,\r
+\r
+ FF_TXD_0_19 => txd_0(15),\r
+ FF_TXD_0_18 => txd_0(14),\r
+ FF_TXD_0_17 => txd_0(13),\r
+ FF_TXD_0_16 => txd_0(12),\r
+ FF_TXD_0_15 => txd_0(11),\r
+ FF_TXD_0_14 => txd_0(10),\r
+ FF_TXD_0_13 => txd_0(9),\r
+ FF_TXD_0_12 => txd_0(8),\r
+ FF_TXD_0_7 => txd_0(7),\r
+ FF_TXD_0_6 => txd_0(6),\r
+ FF_TXD_0_5 => txd_0(5),\r
+ FF_TXD_0_4 => txd_0(4),\r
+ FF_TXD_0_3 => txd_0(3),\r
+ FF_TXD_0_2 => txd_0(2),\r
+ FF_TXD_0_1 => txd_0(1),\r
+ FF_TXD_0_0 => txd_0(0),\r
+ FB_RXD_0_19 => rxd_0(15),\r
+ FB_RXD_0_18 => rxd_0(14),\r
+ FB_RXD_0_17 => rxd_0(13),\r
+ FB_RXD_0_16 => rxd_0(12),\r
+ FB_RXD_0_15 => rxd_0(11),\r
+ FB_RXD_0_14 => rxd_0(10),\r
+ FB_RXD_0_13 => rxd_0(9),\r
+ FB_RXD_0_12 => rxd_0(8),\r
+ FB_RXD_0_7 => rxd_0(7),\r
+ FB_RXD_0_6 => rxd_0(6),\r
+ FB_RXD_0_5 => rxd_0(5),\r
+ FB_RXD_0_4 => rxd_0(4),\r
+ FB_RXD_0_3 => rxd_0(3),\r
+ FB_RXD_0_2 => rxd_0(2),\r
+ FB_RXD_0_1 => rxd_0(1),\r
+ FB_RXD_0_0 => rxd_0(0),\r
+\r
+ FF_TXD_0_20 => tx_en_0(1),\r
+ FF_TXD_0_8 => tx_en_0(0),\r
+ FB_RXD_0_20 => rx_dv_0(1),\r
+ FB_RXD_0_8 => rx_dv_0(0),\r
+\r
+ FF_TXD_0_21 => tx_er_0(1),\r
+ FF_TXD_0_9 => tx_er_0(0),\r
+\r
+ FF_TXD_0_22 => tx_crc_insert_0(1),\r
+ FF_TXD_0_10 => tx_crc_insert_0(0),\r
+\r
+ FF_TXD_0_23 => tx_sfd_0(1),\r
+ FF_TXD_0_11 => tx_sfd_0(0),\r
+\r
+ FB_RXD_0_21 => rx_er_0(1),\r
+ FB_RXD_0_9 => rx_er_0(0),\r
+\r
+ FB_RXD_0_22 => rx_sfd_0(1),\r
+ FB_RXD_0_10 => rx_sfd_0(0),\r
+\r
+ FB_RXD_0_23 => rx_crc_eop_0(1),\r
+ FB_RXD_0_11 => rx_crc_eop_0(0),\r
+\r
+ FF_TXD_1_19 => fpsc_vlo,\r
+ FF_TXD_1_18 => fpsc_vlo,\r
+ FF_TXD_1_17 => fpsc_vlo,\r
+ FF_TXD_1_16 => fpsc_vlo,\r
+ FF_TXD_1_15 => fpsc_vlo,\r
+ FF_TXD_1_14 => fpsc_vlo,\r
+ FF_TXD_1_13 => fpsc_vlo,\r
+ FF_TXD_1_12 => fpsc_vlo,\r
+ FF_TXD_1_7 => fpsc_vlo,\r
+ FF_TXD_1_6 => fpsc_vlo,\r
+ FF_TXD_1_5 => fpsc_vlo,\r
+ FF_TXD_1_4 => fpsc_vlo,\r
+ FF_TXD_1_3 => fpsc_vlo,\r
+ FF_TXD_1_2 => fpsc_vlo,\r
+ FF_TXD_1_1 => fpsc_vlo,\r
+ FF_TXD_1_0 => fpsc_vlo,\r
+ FB_RXD_1_19 => open,\r
+ FB_RXD_1_18 => open,\r
+ FB_RXD_1_17 => open,\r
+ FB_RXD_1_16 => open,\r
+ FB_RXD_1_15 => open,\r
+ FB_RXD_1_14 => open,\r
+ FB_RXD_1_13 => open,\r
+ FB_RXD_1_12 => open,\r
+ FB_RXD_1_7 => open,\r
+ FB_RXD_1_6 => open,\r
+ FB_RXD_1_5 => open,\r
+ FB_RXD_1_4 => open,\r
+ FB_RXD_1_3 => open,\r
+ FB_RXD_1_2 => open,\r
+ FB_RXD_1_1 => open,\r
+ FB_RXD_1_0 => open,\r
+\r
+ FF_TXD_1_20 => fpsc_vlo,\r
+ FF_TXD_1_8 => fpsc_vlo,\r
+ FB_RXD_1_20 => open,\r
+ FB_RXD_1_8 => open,\r
+\r
+ FF_TXD_1_21 => fpsc_vlo,\r
+ FF_TXD_1_9 => fpsc_vlo,\r
+\r
+ FF_TXD_1_22 => fpsc_vlo,\r
+ FF_TXD_1_10 => fpsc_vlo,\r
+ FF_TXD_1_23 => fpsc_vlo,\r
+ FF_TXD_1_11 => fpsc_vlo,\r
+\r
+ FB_RXD_1_21 => open,\r
+ FB_RXD_1_9 => open,\r
+\r
+ FB_RXD_1_22 => open,\r
+ FB_RXD_1_10 => open,\r
+\r
+ FB_RXD_1_23 => open,\r
+ FB_RXD_1_11 => open,\r
+\r
+ FF_TXD_2_19 => fpsc_vlo,\r
+ FF_TXD_2_18 => fpsc_vlo,\r
+ FF_TXD_2_17 => fpsc_vlo,\r
+ FF_TXD_2_16 => fpsc_vlo,\r
+ FF_TXD_2_15 => fpsc_vlo,\r
+ FF_TXD_2_14 => fpsc_vlo,\r
+ FF_TXD_2_13 => fpsc_vlo,\r
+ FF_TXD_2_12 => fpsc_vlo,\r
+ FF_TXD_2_7 => fpsc_vlo,\r
+ FF_TXD_2_6 => fpsc_vlo,\r
+ FF_TXD_2_5 => fpsc_vlo,\r
+ FF_TXD_2_4 => fpsc_vlo,\r
+ FF_TXD_2_3 => fpsc_vlo,\r
+ FF_TXD_2_2 => fpsc_vlo,\r
+ FF_TXD_2_1 => fpsc_vlo,\r
+ FF_TXD_2_0 => fpsc_vlo,\r
+ FB_RXD_2_19 => open,\r
+ FB_RXD_2_18 => open,\r
+ FB_RXD_2_17 => open,\r
+ FB_RXD_2_16 => open,\r
+ FB_RXD_2_15 => open,\r
+ FB_RXD_2_14 => open,\r
+ FB_RXD_2_13 => open,\r
+ FB_RXD_2_12 => open,\r
+ FB_RXD_2_7 => open,\r
+ FB_RXD_2_6 => open,\r
+ FB_RXD_2_5 => open,\r
+ FB_RXD_2_4 => open,\r
+ FB_RXD_2_3 => open,\r
+ FB_RXD_2_2 => open,\r
+ FB_RXD_2_1 => open,\r
+ FB_RXD_2_0 => open,\r
+\r
+ FF_TXD_2_20 => fpsc_vlo,\r
+ FF_TXD_2_8 => fpsc_vlo,\r
+ FB_RXD_2_20 => open,\r
+ FB_RXD_2_8 => open,\r
+\r
+ FF_TXD_2_21 => fpsc_vlo,\r
+ FF_TXD_2_9 => fpsc_vlo,\r
+\r
+ FF_TXD_2_22 => fpsc_vlo,\r
+ FF_TXD_2_10 => fpsc_vlo,\r
+ FF_TXD_2_23 => fpsc_vlo,\r
+ FF_TXD_2_11 => fpsc_vlo,\r
+\r
+ FB_RXD_2_21 => open,\r
+ FB_RXD_2_9 => open,\r
+\r
+ FB_RXD_2_22 => open,\r
+ FB_RXD_2_10 => open,\r
+\r
+ FB_RXD_2_23 => open,\r
+ FB_RXD_2_11 => open,\r
+\r
+ FF_TXD_3_19 => fpsc_vlo,\r
+ FF_TXD_3_18 => fpsc_vlo,\r
+ FF_TXD_3_17 => fpsc_vlo,\r
+ FF_TXD_3_16 => fpsc_vlo,\r
+ FF_TXD_3_15 => fpsc_vlo,\r
+ FF_TXD_3_14 => fpsc_vlo,\r
+ FF_TXD_3_13 => fpsc_vlo,\r
+ FF_TXD_3_12 => fpsc_vlo,\r
+ FF_TXD_3_7 => fpsc_vlo,\r
+ FF_TXD_3_6 => fpsc_vlo,\r
+ FF_TXD_3_5 => fpsc_vlo,\r
+ FF_TXD_3_4 => fpsc_vlo,\r
+ FF_TXD_3_3 => fpsc_vlo,\r
+ FF_TXD_3_2 => fpsc_vlo,\r
+ FF_TXD_3_1 => fpsc_vlo,\r
+ FF_TXD_3_0 => fpsc_vlo,\r
+ FB_RXD_3_19 => open,\r
+ FB_RXD_3_18 => open,\r
+ FB_RXD_3_17 => open,\r
+ FB_RXD_3_16 => open,\r
+ FB_RXD_3_15 => open,\r
+ FB_RXD_3_14 => open,\r
+ FB_RXD_3_13 => open,\r
+ FB_RXD_3_12 => open,\r
+ FB_RXD_3_7 => open,\r
+ FB_RXD_3_6 => open,\r
+ FB_RXD_3_5 => open,\r
+ FB_RXD_3_4 => open,\r
+ FB_RXD_3_3 => open,\r
+ FB_RXD_3_2 => open,\r
+ FB_RXD_3_1 => open,\r
+ FB_RXD_3_0 => open,\r
+\r
+ FF_TXD_3_20 => fpsc_vlo,\r
+ FF_TXD_3_8 => fpsc_vlo,\r
+ FB_RXD_3_20 => open,\r
+ FB_RXD_3_8 => open,\r
+\r
+ FF_TXD_3_21 => fpsc_vlo,\r
+ FF_TXD_3_9 => fpsc_vlo,\r
+\r
+ FF_TXD_3_22 => fpsc_vlo,\r
+ FF_TXD_3_10 => fpsc_vlo,\r
+ FF_TXD_3_23 => fpsc_vlo,\r
+ FF_TXD_3_11 => fpsc_vlo,\r
+\r
+ FB_RXD_3_21 => open,\r
+ FB_RXD_3_9 => open,\r
+\r
+ FB_RXD_3_22 => open,\r
+ FB_RXD_3_10 => open,\r
+\r
+ FB_RXD_3_23 => open,\r
+ FB_RXD_3_11 => open,\r
+\r
+ HDINP0 => hdinp_0,\r
+ HDINN0 => hdinn_0,\r
+ HDOUTP0 => hdoutp_0,\r
+ HDOUTN0 => hdoutn_0,\r
+ FF_SYSCLK0 => ref_0_sclk,\r
+ FF_RXCLK0 => open,\r
+ FFC_LANE_TX_RST0 => tx_rst_0,\r
+ FFC_LANE_RX_RST0 => rx_rst_0,\r
+ FF_TCLK0 => tclk_0,\r
+ FF_RCLK0 => rclk_0,\r
+ HDINP1 => fpsc_vlo,\r
+ HDINN1 => fpsc_vlo,\r
+ HDOUTP1 => open,\r
+ HDOUTN1 => open,\r
+ FF_SYSCLK1 => open,\r
+ FF_RXCLK1 => open,\r
+ FFC_LANE_TX_RST1 => fpsc_vlo,\r
+ FFC_LANE_RX_RST1 => fpsc_vlo,\r
+ FF_TCLK1 => fpsc_vlo,\r
+ FF_RCLK1 => fpsc_vlo,\r
+ HDINP2 => fpsc_vlo,\r
+ HDINN2 => fpsc_vlo,\r
+ HDOUTP2 => open,\r
+ HDOUTN2 => open,\r
+ FF_SYSCLK2 => open,\r
+ FF_RXCLK2 => open,\r
+ FFC_LANE_TX_RST2 => fpsc_vlo,\r
+ FFC_LANE_RX_RST2 => fpsc_vlo,\r
+ FF_TCLK2 => fpsc_vlo,\r
+ FF_RCLK2 => fpsc_vlo,\r
+ HDINP3 => fpsc_vlo,\r
+ HDINN3 => fpsc_vlo,\r
+ HDOUTP3 => open,\r
+ HDOUTN3 => open,\r
+ FF_SYSCLK3 => open,\r
+ FF_RXCLK3 => open,\r
+ FFC_LANE_TX_RST3 => fpsc_vlo,\r
+ FFC_LANE_RX_RST3 => fpsc_vlo,\r
+ FF_TCLK3 => fpsc_vlo,\r
+ FF_RCLK3 => fpsc_vlo,\r
+\r
+ FFC_PCIE_EI_EN_0 => fpsc_vlo,\r
+ FFC_PCIE_CT_0 => fpsc_vlo,\r
+ FFC_PCIE_TX_0 => fpsc_vlo,\r
+ FFC_PCIE_RX_0 => fpsc_vlo,\r
+ FFS_PCIE_CON_0 => open,\r
+ FFS_PCIE_DONE_0 => open,\r
+ FFC_PCIE_EI_EN_1 => fpsc_vlo,\r
+ FFC_PCIE_CT_1 => fpsc_vlo,\r
+ FFC_PCIE_TX_1 => fpsc_vlo,\r
+ FFC_PCIE_RX_1 => fpsc_vlo,\r
+ FFS_PCIE_CON_1 => open,\r
+ FFS_PCIE_DONE_1 => open,\r
+ FFC_PCIE_EI_EN_2 => fpsc_vlo,\r
+ FFC_PCIE_CT_2 => fpsc_vlo,\r
+ FFC_PCIE_TX_2 => fpsc_vlo,\r
+ FFC_PCIE_RX_2 => fpsc_vlo,\r
+ FFS_PCIE_CON_2 => open,\r
+ FFS_PCIE_DONE_2 => open,\r
+ FFC_PCIE_EI_EN_3 => fpsc_vlo,\r
+ FFC_PCIE_CT_3 => fpsc_vlo,\r
+ FFC_PCIE_TX_3 => fpsc_vlo,\r
+ FFC_PCIE_RX_3 => fpsc_vlo,\r
+ FFS_PCIE_CON_3 => open,\r
+ FFS_PCIE_DONE_3 => open,\r
+\r
+ FFC_SD_0 => lsm_en_0,\r
+ FFC_SD_1 => fpsc_vlo,\r
+ FFC_SD_2 => fpsc_vlo,\r
+ FFC_SD_3 => fpsc_vlo,\r
+\r
+ FFC_EN_CGA_0 => fpsc_vlo,\r
+ FFC_EN_CGA_1 => fpsc_vlo,\r
+ FFC_EN_CGA_2 => fpsc_vlo,\r
+ FFC_EN_CGA_3 => fpsc_vlo,\r
+\r
+ FFC_ALIGN_EN_0 => fpsc_vlo,\r
+ FFC_ALIGN_EN_1 => fpsc_vlo,\r
+ FFC_ALIGN_EN_2 => fpsc_vlo,\r
+ FFC_ALIGN_EN_3 => fpsc_vlo,\r
+\r
+ FFC_FB_LB_0 => felb_0,\r
+ FFC_FB_LB_1 => fpsc_vlo,\r
+ FFC_FB_LB_2 => fpsc_vlo,\r
+ FFC_FB_LB_3 => fpsc_vlo,\r
+\r
+ FFS_LS_STATUS_0 => lsm_status_0,\r
+ FFS_LS_STATUS_1 => open,\r
+ FFS_LS_STATUS_2 => open,\r
+ FFS_LS_STATUS_3 => open,\r
+\r
+ FFS_CC_ORUN_0 => ctc_orun_0,\r
+ FFS_CC_URUN_0 => ctc_urun_0,\r
+ FFS_CC_ORUN_1 => open,\r
+ FFS_CC_URUN_1 => open,\r
+ FFS_CC_ORUN_2 => open,\r
+ FFS_CC_URUN_2 => open,\r
+ FFS_CC_ORUN_3 => open,\r
+ FFS_CC_URUN_3 => open,\r
+\r
+ FFC_AB_RESET => fpsc_vlo,\r
+\r
+ FFS_AB_STATUS => open,\r
+ FFS_AB_ALIGNED => open,\r
+ FFS_AB_FAILED => open,\r
+\r
+ FFC_CD_RESET => fpsc_vlo,\r
+ FFS_CD_STATUS => open,\r
+\r
+ FFS_CD_ALIGNED => open,\r
+ FFS_CD_FAILED => open,\r
+ BS4PAD_0 => open,\r
+ BS4PAD_1 => open,\r
+ BS4PAD_2 => open,\r
+ BS4PAD_3 => open,\r
+ FFC_SB_INV_RX_0 => fpsc_vlo,\r
+ FFC_SB_INV_RX_1 => fpsc_vlo,\r
+ FFC_SB_INV_RX_2 => fpsc_vlo,\r
+ FFC_SB_INV_RX_3 => fpsc_vlo,\r
+ TCK_FMAC => open,\r
+ TCK_FMACP => fpsc_vlo,\r
+ FF_SYSCLK_P1 => ref_pclk,\r
+ FF_RXCLK_P1 => open,\r
+ FF_RXCLK_P2 => open,\r
+ FFC_QUAD_RST => quad_rst,\r
+ FFS_RLOS_LO0 => open,\r
+ FFS_RLOS_LO1 => open,\r
+ FFS_RLOS_LO2 => open,\r
+ FFS_RLOS_LO3 => open,\r
+ COUT_21 => open,\r
+ COUT_20 => open,\r
+ COUT_19 => open,\r
+ COUT_18 => open,\r
+ COUT_17 => open,\r
+ COUT_16 => open,\r
+ COUT_15 => open,\r
+ COUT_14 => open,\r
+ COUT_13 => open,\r
+ COUT_12 => open,\r
+ COUT_11 => open,\r
+ COUT_10 => open,\r
+ COUT_9 => open,\r
+ COUT_8 => open,\r
+ COUT_7 => open,\r
+ COUT_6 => open,\r
+ COUT_5 => open,\r
+ COUT_4 => open,\r
+ COUT_3 => open,\r
+ COUT_2 => open,\r
+ COUT_1 => open,\r
+ COUT_0 => open,\r
+ CIN_12 => fpsc_vlo,\r
+ CIN_11 => fpsc_vlo,\r
+ CIN_10 => fpsc_vlo,\r
+ CIN_9 => fpsc_vlo,\r
+ CIN_8 => fpsc_vlo,\r
+ CIN_7 => fpsc_vlo,\r
+ CIN_6 => fpsc_vlo,\r
+ CIN_5 => fpsc_vlo,\r
+ CIN_4 => fpsc_vlo,\r
+ CIN_3 => fpsc_vlo,\r
+ CIN_2 => fpsc_vlo,\r
+ CIN_1 => fpsc_vlo,\r
+ CIN_0 => fpsc_vlo,\r
+ TESTCLK_MACO => fpsc_vlo,\r
+ FFC_MACRO_RST => serdes_rst);\r
+\r
+--synopsys translate_off\r
+file_read : PROCESS\r
+VARIABLE open_status : file_open_status;\r
+FILE config : text;\r
+BEGIN\r
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);\r
+ IF (open_status = name_error) THEN\r
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"\r
+ severity ERROR;\r
+ END IF;\r
+ wait;\r
+END PROCESS;\r
+--synopsys translate_on\r
+ \r
+end serdes_gbe_0_arch ;\r
jspc29 / trbnet.git / commitdiff