Auto-answer readout in blank project

diff --git a/blank/config.vhd b/blank/config.vhd
index 7962483d996cde68791528a884a01d63ac0dc37f..714d24ec2fa2a4774b1c8cce9a4b5c94840906be 100644 (file)
--- a/blank/config.vhd
+++ b/blank/config.vhd
@@ -32,7 +32,7 @@ package config is
 
 --Address settings
   constant INIT_ADDRESS           : std_logic_vector := x"F305";
-  constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"48";
+  constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4B";
 
 ------------------------------------------------------------------------------
 --End of design configuration

diff --git a/blank/trb3_periph_blank.vhd b/blank/trb3_periph_blank.vhd
index 88e0b4b8cc6fe7c7a1362d9a34a0b446ee0b9c0d..448071ad4ea01abf608086a6b323bbf38d1da4c8 100644 (file)
--- a/blank/trb3_periph_blank.vhd
+++ b/blank/trb3_periph_blank.vhd
@@ -378,7 +378,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
 --       BUS_TX             => busrdo_tx
 -- 
 --       );
-
+readout_tx(0).data_finished <= '1';
+readout_tx(0).data_write    <= '0';
+readout_tx(0).busy_release  <= '1';
 
 
 end architecture;