--- /dev/null
+Clocked TDC (MDC edition)
+==
+
+
+
+
+General Remarks
+--
+
+* Each FPGA contains 32 TDC channels
+ * Counting starts from 0, the reference channel has no channel number
+
+* Data is not output in ordered fashion, hits are sent mixed between channels, not ordered by time.
+* There might be up to 10 hits per channel
+
+* TDC calibration is not necessary by default
+* TDC calibration is implemented in two options (usual 0xd trigger type):
+ * Internal calibration with a 50 ns long pulse
+ * Calibration pulse using the analog front-end chips
+ * about 110 ns long, depending on front-end settings
+ * Might give several hits especially with low thresholds
+
+
+Data Format (v0)
+--
+* All time information is encoded in units of 0.4 ns.
+* All timestamps have 13 Bit
+ * Overflow happens after 3276.8 ns
+* All hits can be assumed to be in a window between -2000 and +1200 ns relative to the reference time
+
+* Header word
+ * always sent as first word
+ * (31..24) TDC Header marker 0xDC
+ * (19..16) data format version 0
+ * (12..0) Reference Time timestamp
+
+* Hit data words
+ * all remaining words after header
+ * (12..0) Trailing Edge timestamp
+ * (25..13) Leading Edge timestamp
+ * (26) Error Flag
+ * (31..27) Channel number (0 - 31)
+
+
+Data Format (v1)
+--
+
+* Same as v0, but channel numbers are encoded differently
+ * to support setups with more than 32 channels
+ * not to be used in MDC, but e.g. on Trb5sc
+ * The Header word followed by an arbitrary amount of data is repeated N = ceil(channels/3) times, e.g. 3 times for a 48 channel TDC.
+ * Bit 31 distinguishes between Header words and hit words
+
+* Header word
+ * 0xDC01rrrr
+ * (31..24) TDC Header marker 0xDC
+ * **(23..20) TDC Channel group number**
+ * **(19..16) data format version 1**
+ * (12..0) Reference Time timestamp
+
+* Hit data words
+ * (12..0) Trailing Edge timestamp
+ * (25..13) Leading Edge timestamp
+ * (26) Error Flag
+ * **(30..27) Channel number (0 - 15)**
+ * **(31) TDC Hit word marker (always 0)**
+
+
+
+