Update SPI interface with new features

diff --git a/trb3/AdditionalModules.tex b/trb3/AdditionalModules.tex
index 6bc5626d593d3a228bccd148b9f41d3ef9666c9b..8ef61a74a5ceacbc21ca83a5bd9e2f86f86a37f6 100644 (file)
--- a/trb3/AdditionalModules.tex
+++ b/trb3/AdditionalModules.tex
@@ -1,4 +1,4 @@
-\subsection{DAC Programming}
+\subsection{SPI Interface}
   \input{DacProgramming}
 \subsection{Forward inputs for trigger}
   \input{TriggerModule}      

diff --git a/trb3/DacProgramming.tex b/trb3/DacProgramming.tex
index c22c8d524bb1a503709bf46d83d1c9792dca02b9..869e99fd3568878941a4138ee84091d00930c9a5 100644 (file)
--- a/trb3/DacProgramming.tex
+++ b/trb3/DacProgramming.tex
@@ -16,7 +16,7 @@ Programming the DAC for threshold generation is simple: A standard SPI interface
 The number of bits per word can be set with a generic in the VHDL component instantiation. If a value below 32 is chosen, the upper bits in all registers are ignored.
 The number of wait-cycles between two edges on SCK can be selected as well. The default for LTC2600 and Padiwa is 7 wait cycles, I.e. 6.25 MHz.
 
-\paragraph*{Configuration File}
+\paragraph*{Configuration File for LTC2600 DAC}
 The software takes a text file as input and generates the correct SPI sequence to load and activate the DAC.
 The ASCII format is shown below, the commands can be found in table~\ref{ltc2600cmd}.
 \begin{verbatim}
@@ -62,18 +62,21 @@ The ASCII format is shown below, the commands can be found in table~\ref{ltc2600
 
 \paragraph*{Registers}~\\
 
-\begin{tabular}{c|c|l}
+\begin{tabularx}{\textwidth}{c|c|X}
  0xd40N & Data & 16 places for SPI commands \\
  0xd410 & Chip Select & CS output, one bit for each of the 15 outputs, positive logic\\
  0xd411 & Control & Control register. See next paragraph\\
  0xd412 & Readback & Data received on SPI\\
  0xd413 & Master & Block SPI for other use. See next paragraph\\ 
- 0xd414 & Clear & Additional output to connect to a CLR-input on SPI devices\\
- 0xd418 & Invert & Set lowest bit to invert all outputs\\
+ 0xd414 & Clear & Additional output to connect to a CLR-input on SPI devices \newline(not available in most designs)\\
+ 0xd415 & SDO Ctrl & Bit 15..0: Disable SDO outputs, Bit 31..16: Invert SDO outputs\newline(added 2019-01-30)\\
+ 0xd416 & SCK Ctrl & Bit 15..0: Disable SCK outputs, Bit 31..16: Invert SCK outputs\newline(added 2019-01-30)\\
+ 0xd417 & CS Ctrl  & Bit 15..0: Disable CS  outputs, Bit 31..16: Invert CS  outputs\newline(added 2019-01-30)\\
+ 0xd418 & Invert & Set lowest bit to invert all outputs (removed 2019-01-30)\\
  0xd419 & Word Length & Number of bits of a SPI word, default: 32\\
  0xd41a & Period & Half period of a SPI clock cycle, in system clocks. default: 7\\
  
-\end{tabular}
+\end{tabularx}
 
 \paragraph*{Collisions during reading}
 Writing to all registers is blocked while a transfer is in progress, i.e. writing can not be broken.