EXT_CLOCK : integer range 0 to 1 := c_NO;
USE_200_MHZ: integer range 0 to 1 := c_YES;
USE_125_MHZ: integer range 0 to 1 := c_NO;
- USE_CTC : integer range 0 to 1 := c_YES
+ USE_CTC : integer range 0 to 1 := c_YES;
+ USE_SLAVE : integer range 0 to 1 := c_NO
);
port(
CLK : in std_logic; -- SerDes clock
MED_DATAREADY_OUT : out std_logic;
MED_READ_IN : in std_logic;
REFCLK2CORE_OUT : out std_logic;
+ CLK_RX_HALF_OUT : out std_logic;
+ CLK_RX_FULL_OUT : out std_logic;
--SFP Connection
SD_RXD_P_IN : in std_logic;
SD_RXD_N_IN : in std_logic;
SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SD_TXDIS_OUT : out std_logic; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+
-- Status and control port
STAT_OP : out std_logic_vector (15 downto 0);
CTRL_OP : in std_logic_vector (15 downto 0);
signal link_error : std_logic_vector(8 downto 0);
signal ff_txhalfclk : std_logic;
signal ff_rxhalfclk : std_logic;
+ signal ff_rxfullclk : std_logic;
--rx fifo signals
signal fifo_rx_rd_en : std_logic;
signal fifo_rx_wr_en : std_logic;
signal clk_sys : std_logic;
signal clk_tx : std_logic;
signal clk_rx : std_logic;
- signal clk_ref : std_logic;
-
+ signal clk_rxref : std_logic;
+ signal clk_txref : std_logic;
+
+ signal sci_ch_i : std_logic_vector(3 downto 0);
+ signal sci_addr_i : std_logic_vector(8 downto 0);
+ signal sci_data_in_i : std_logic_vector(7 downto 0);
+ signal sci_data_out_i : std_logic_vector(7 downto 0);
+ signal sci_read_i : std_logic;
+ signal sci_write_i : std_logic;
+ signal sci_write_shift_i : std_logic_vector(2 downto 0);
+ signal sci_read_shift_i : std_logic_vector(2 downto 0);
+
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of led_counter : signal is true;
--------------------------------------------------------------------------
-- Select proper clock configuration
--------------------------------------------------------------------------
-gen_clocks_200 : if USE_200_MHZ = c_YES generate
+gen_clocks_200_ctc : if USE_200_MHZ = c_YES and USE_CTC = c_YES and USE_SLAVE = c_NO generate
clk_sys <= SYSCLK;
clk_tx <= SYSCLK;
clk_rx <= SYSCLK;
- clk_ref <= CLK;
+ clk_rxref <= CLK;
+ clk_txref <= CLK;
+end generate;
+
+
+gen_clocks_200_noctc : if USE_200_MHZ = c_YES and USE_CTC = c_NO and USE_SLAVE = c_NO generate
+ clk_sys <= SYSCLK;
+ clk_tx <= SYSCLK;
+ clk_rx <= ff_rxhalfclk;
+ clk_rxref <= CLK;
+ clk_txref <= CLK;
+end generate;
+
+
+gen_clocks_200_ctc_sync : if USE_200_MHZ = c_YES and USE_CTC = c_YES and USE_SLAVE = c_YES generate
+ clk_sys <= SYSCLK;
+ clk_tx <= ff_rxhalfclk;
+ clk_rx <= ff_rxhalfclk;
+ clk_rxref <= CLK;
+ clk_txref <= ff_rxfullclk;
+end generate;
+
+
+gen_clocks_200_noctc_sync : if USE_200_MHZ = c_YES and USE_CTC = c_NO and USE_SLAVE = c_YES generate
+ clk_sys <= SYSCLK;
+ clk_tx <= ff_rxhalfclk;
+ clk_rx <= ff_rxhalfclk;
+ clk_rxref <= CLK;
+ clk_txref <= ff_rxfullclk;
end generate;
--------------------------------------------------------------------------
ffc_quad_rst <= quad_rst;
ffc_lane_tx_rst <= lane_rst;
+
+
ffc_lane_rx_rst <= lane_rst;
-- SerDes clock output to FPGA fabric
-refclk2core_out <= '0';
+REFCLK2CORE_OUT <= ff_rxhalfclk;
+CLK_RX_HALF_OUT <= ff_rxhalfclk;
+CLK_RX_FULL_OUT <= ff_rxfullclk;
+
-- Instantiation of serdes module
RXICLK_CH0 => clk_rx,
TXICLK_CH0 => clk_tx,
- FPGA_RXREFCLK_CH0 => clk_ref,
- FPGA_TXREFCLK => clk_ref,
- RX_FULL_CLK_CH0 => open,
+ FPGA_RXREFCLK_CH0 => clk_rxref,
+ FPGA_TXREFCLK => clk_txref,
+ RX_FULL_CLK_CH0 => ff_rxfullclk,
RX_HALF_CLK_CH0 => ff_rxhalfclk,
TX_FULL_CLK_CH0 => open,
TX_HALF_CLK_CH0 => ff_txhalfclk,
TX_DIV2_MODE_CH0_C => '0', --full rate
RX_DIV2_MODE_CH0_C => '0', --full rate
- SCI_WRDATA => (others => '0'),
- SCI_RDDATA => open,
- SCI_ADDR => (others => '0'),
- SCI_SEL_QUAD => '0',
- SCI_SEL_CH0 => '0',
- SCI_RD => '0',
- SCI_WRN => '0',
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_SEL_QUAD => sci_addr_i(8),
+ SCI_SEL_CH0 => sci_ch_i(0),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
TX_SERDES_RST_C => CLEAR,
RST_N => '1',
RXICLK_CH0 => clk_rx,
TXICLK_CH0 => clk_tx,
- FPGA_RXREFCLK_CH0 => clk_ref,
- FPGA_TXREFCLK => clk_ref,
- RX_FULL_CLK_CH0 => open,
+ FPGA_RXREFCLK_CH0 => clk_rxref,
+ FPGA_TXREFCLK => clk_txref,
+ RX_FULL_CLK_CH0 => ff_rxfullclk,
RX_HALF_CLK_CH0 => ff_rxhalfclk,
TX_FULL_CLK_CH0 => open,
TX_HALF_CLK_CH0 => ff_txhalfclk,
TX_DIV2_MODE_CH0_C => '0', --full rate
RX_DIV2_MODE_CH0_C => '0', --full rate
- SCI_WRDATA => (others => '0'),
- SCI_RDDATA => open,
- SCI_ADDR => (others => '0'),
- SCI_SEL_QUAD => '0',
- SCI_SEL_CH0 => '0',
- SCI_RD => '0',
- SCI_WRN => '0',
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_SEL_QUAD => sci_addr_i(8),
+ SCI_SEL_CH0 => sci_ch_i(0),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
TX_SERDES_RST_C => CLEAR,
RST_N => '1',
RXICLK_CH1 => clk_rx,
TXICLK_CH1 => clk_tx,
- FPGA_RXREFCLK_CH1 => clk_ref,
- FPGA_TXREFCLK => clk_ref,
- RX_FULL_CLK_CH1 => open,
+ FPGA_RXREFCLK_CH1 => clk_rxref,
+ FPGA_TXREFCLK => clk_txref,
+ RX_FULL_CLK_CH1 => ff_rxfullclk,
RX_HALF_CLK_CH1 => ff_rxhalfclk,
TX_FULL_CLK_CH1 => open,
TX_HALF_CLK_CH1 => ff_txhalfclk,
TX_DIV2_MODE_CH1_C => '0', --full rate
RX_DIV2_MODE_CH1_C => '0', --full rate
- SCI_WRDATA => (others => '0'),
- SCI_RDDATA => open,
- SCI_ADDR => (others => '0'),
- SCI_SEL_QUAD => '0',
- SCI_SEL_CH1 => '0',
- SCI_RD => '0',
- SCI_WRN => '0',
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_SEL_QUAD => sci_addr_i(8),
+ SCI_SEL_CH1 => sci_ch_i(1),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
+
TX_SERDES_RST_C => CLEAR,
RST_N => '1',
end if;
end process THE_SERDES_INPUT_PROC;
+
+--SCI
+----------------------
+PROC_SCI : process begin
+ wait until rising_edge(clk_sys);
+ if SCI_READ = '1' or SCI_WRITE = '1' then
+ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_addr_i <= SCI_ADDR;
+ sci_data_in_i <= SCI_DATA_IN;
+ end if;
+ sci_read_shift_i <= sci_read_shift_i(1 downto 0) & SCI_READ;
+ sci_write_shift_i <= sci_write_shift_i(1 downto 0) & SCI_WRITE;
+ SCI_DATA_OUT <= sci_data_out_i;
+end process;
+
+sci_write_i <= or_all(sci_write_shift_i);
+sci_read_i <= or_all(sci_read_shift_i);
+SCI_ACK <= sci_write_shift_i(2) or sci_read_shift_i(2);
+
+
+
--Generate LED signals
----------------------
signal sci_write_shift_i : std_logic_vector(2 downto 0);
signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of led_counter : signal is true;
end generate;
- PROC_SCI : process begin
- wait until rising_edge(clk_sys);
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and (SCI_READ or SCI_WRITE);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and (SCI_READ or SCI_WRITE);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and (SCI_READ or SCI_WRITE);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and (SCI_READ or SCI_WRITE);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- end if;
- sci_read_shift_i <= sci_read_shift_i(1 downto 0) & SCI_READ;
- sci_write_shift_i <= sci_write_shift_i(1 downto 0) & SCI_WRITE;
- SCI_DATA_OUT <= sci_data_out_i;
- end process;
-
- sci_write_i <= or_all(sci_write_shift_i);
- sci_read_i <= or_all(sci_read_shift_i);
- SCI_ACK <= sci_write_shift_i(2) or sci_read_shift_i(2);
+PROC_SCI : process begin
+ wait until rising_edge(clk_sys);
+ if SCI_READ = '1' or SCI_WRITE = '1' then
+ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_addr_i <= SCI_ADDR;
+ sci_data_in_i <= SCI_DATA_IN;
+ end if;
+ sci_read_shift_i <= sci_read_shift_i(1 downto 0) & SCI_READ;
+ sci_write_shift_i <= sci_write_shift_i(1 downto 0) & SCI_WRITE;
+ SCI_DATA_OUT <= sci_data_out_i;
+end process;
+
+sci_write_i <= or_all(sci_write_shift_i);
+sci_read_i <= or_all(sci_read_shift_i);
+SCI_ACK <= sci_write_shift_i(2) or sci_read_shift_i(2);
+
+
-- Instantiation of serdes module
gen_serdes_200 : if FREQUENCY = 200 generate
SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
-- Status and control port
STAT_OP : out std_logic_vector (4*16-1 downto 0);
CTRL_OP : in std_logic_vector (4*16-1 downto 0);
signal clk_tx : std_logic;
signal clk_rx : std_logic;
signal clk_ref : std_logic;
-
+
+ signal sci_ch_i : std_logic_vector(3 downto 0);
+ signal sci_addr_i : std_logic_vector(8 downto 0);
+ signal sci_data_in_i : std_logic_vector(7 downto 0);
+ signal sci_data_out_i : std_logic_vector(7 downto 0);
+ signal sci_read_i : std_logic;
+ signal sci_write_i : std_logic;
+ signal sci_write_shift_i : std_logic_vector(2 downto 0);
+ signal sci_read_shift_i : std_logic_vector(2 downto 0);
+
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of led_counter : signal is true;
end generate;
+
+PROC_SCI : process begin
+ wait until rising_edge(clk_sys);
+ if SCI_READ = '1' or SCI_WRITE = '1' then
+ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_addr_i <= SCI_ADDR;
+ sci_data_in_i <= SCI_DATA_IN;
+ end if;
+ sci_read_shift_i <= sci_read_shift_i(1 downto 0) & SCI_READ;
+ sci_write_shift_i <= sci_write_shift_i(1 downto 0) & SCI_WRITE;
+ SCI_DATA_OUT <= sci_data_out_i;
+end process;
+
+sci_write_i <= or_all(sci_write_shift_i);
+sci_read_i <= or_all(sci_read_shift_i);
+SCI_ACK <= sci_write_shift_i(2) or sci_read_shift_i(2);
+
+
+
-- Instantiation of serdes module
gen_serdes_200 : if FREQUENCY = 200 generate
THE_SERDES: serdes_onboard_full
TX_DIV2_MODE_CH3_C => '0', --full rate
RX_DIV2_MODE_CH3_C => '0', --full rate
- SCI_WRDATA => (others => '0'),
- SCI_RDDATA => open,
- SCI_ADDR => (others => '0'),
- SCI_SEL_QUAD => '0',
- SCI_SEL_CH0 => '0',
- SCI_SEL_CH1 => '0',
- SCI_SEL_CH2 => '0',
- SCI_SEL_CH3 => '0',
- SCI_RD => '0',
- SCI_WRN => '0',
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_SEL_QUAD => sci_addr_i(8),
+ SCI_SEL_CH0 => sci_ch_i(0),
+ SCI_SEL_CH1 => sci_ch_i(1),
+ SCI_SEL_CH2 => sci_ch_i(2),
+ SCI_SEL_CH3 => sci_ch_i(3),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
TX_SERDES_RST_C => CLEAR,
TX_SYNC_QD_C => '0',
CLOCK_FREQUENCY : integer range 1 to 200 := 100;
USE_ONEWIRE : integer range 0 to 2 := c_YES;
BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
- RDO_ADDITIONAL_PORT : integer range 0 to 1 := c_YES;
+ RDO_ADDITIONAL_PORT : integer range 0 to 2 := 2;
RDO_DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;
- RDO_DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8;
+ RDO_DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 384;
RDO_HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;
- RDO_HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8;
+ RDO_HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 500;
--media interfaces & hub ports
MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 5;
MII_IS_UPLINK : hub_mii_config_t := (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);
RDO_VALID_TIMING_TRG_OUT : out std_logic;
RDO_VALID_NOTIMING_TRG_OUT : out std_logic;
RDO_INVALID_TRG_OUT : out std_logic;
+ RDO_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
+ RDO_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
+ RDO_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
+ RDO_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+
--Data out
RDO_TRG_STATUSBITS_IN : in std_logic_vector (31 downto 0) := (others => '0');
RDO_DATA_IN : in std_logic_vector (31 downto 0) := (others => '0');
RDO_DATA_WRITE_IN : in std_logic := '0';
RDO_DATA_FINISHED_IN : in std_logic := '0';
- RDO_ADDITIONAL_DATA : in std_logic_vector(31 downto 0);
- RDO_ADDITIONAL_WRITE : in std_logic;
- RDO_ADDITIONAL_FINISHED : in std_logic;
- RDO_ADDITIONAL_STATUSBITS_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ RDO_ADDITIONAL_DATA : in std_logic_vector(RDO_ADDITIONAL_PORT*32-1 downto 0);
+ RDO_ADDITIONAL_WRITE : in std_logic_vector(RDO_ADDITIONAL_PORT-1 downto 0);
+ RDO_ADDITIONAL_FINISHED : in std_logic_vector(RDO_ADDITIONAL_PORT-1 downto 0);
+ RDO_ADDITIONAL_STATUSBITS_IN : in std_logic_vector(RDO_ADDITIONAL_PORT*32-1 downto 0) := (others => '0');
-- Slow Control --------------------------------------------------------------------
COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
CLOCK_FREQUENCY : integer range 1 to 200 := 100;
USE_ONEWIRE : integer range 0 to 2 := c_YES;
BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
- RDO_ADDITIONAL_PORT : integer range 0 to 1 := c_YES;
+ RDO_ADDITIONAL_PORT : integer range 1 to 2 := 2;
RDO_DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;
RDO_DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8;
RDO_HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;
RDO_VALID_TIMING_TRG_OUT : out std_logic;
RDO_VALID_NOTIMING_TRG_OUT : out std_logic;
RDO_INVALID_TRG_OUT : out std_logic;
+
+ RDO_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
+ RDO_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
+ RDO_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
+ RDO_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+
--Data out
RDO_TRG_STATUSBITS_IN : in std_logic_vector (31 downto 0) := (others => '0');
RDO_DATA_IN : in std_logic_vector (31 downto 0) := (others => '0');
RDO_DATA_WRITE_IN : in std_logic := '0';
RDO_DATA_FINISHED_IN : in std_logic := '0';
- RDO_ADDITIONAL_DATA : in std_logic_vector(31 downto 0);
- RDO_ADDITIONAL_WRITE : in std_logic;
- RDO_ADDITIONAL_FINISHED : in std_logic;
- RDO_ADDITIONAL_STATUSBITS_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ RDO_ADDITIONAL_DATA : in std_logic_vector(RDO_ADDITIONAL_PORT*32-1 downto 0);
+ RDO_ADDITIONAL_WRITE : in std_logic_vector(RDO_ADDITIONAL_PORT-1 downto 0);
+ RDO_ADDITIONAL_FINISHED : in std_logic_vector(RDO_ADDITIONAL_PORT-1 downto 0);
+ RDO_ADDITIONAL_STATUSBITS_IN : in std_logic_vector(RDO_ADDITIONAL_PORT*32-1 downto 0) := (others => '0');
-- Slow Control --------------------------------------------------------------------
COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
--Stat/Control
STATUS_OUT => stat_lvl1_handler,
- TRG_ENABLE_IN => common_ctrl(95),
- TRG_INVERT_IN => common_ctrl(93),
+ TRG_ENABLE_IN => '1',
+ TRG_INVERT_IN => '0',
COUNTERS_STATUS_OUT => stat_counters_lvl1_handler,
--Debug
DEBUG_OUT => open
IPU_ERROR_PATTERN_OUT => ipu_error_pattern_i,
--FEE Input
- FEE_TRG_RELEASE_IN(0) => RDO_DATA_FINISHED_IN,
- FEE_TRG_RELEASE_IN(1) => RDO_ADDITIONAL_FINISHED,
- FEE_TRG_STATUSBITS_IN(31 downto 0) => RDO_TRG_STATUSBITS_IN,
- FEE_TRG_STATUSBITS_IN(63 downto 32) => RDO_ADDITIONAL_STATUSBITS_IN,
- FEE_DATA_IN(31 downto 0) => RDO_DATA_IN,
- FEE_DATA_IN(63 downto 32) => RDO_ADDITIONAL_DATA,
- FEE_DATA_WRITE_IN(0) => RDO_DATA_WRITE_IN,
- FEE_DATA_WRITE_IN(1) => RDO_ADDITIONAL_WRITE,
- FEE_DATA_FINISHED_IN(0) => RDO_DATA_FINISHED_IN,
- FEE_DATA_FINISHED_IN(1) => RDO_ADDITIONAL_FINISHED,
- FEE_DATA_ALMOST_FULL_OUT => open,
+ FEE_TRG_RELEASE_IN(0) => RDO_DATA_FINISHED_IN,
+ FEE_TRG_RELEASE_IN(RDO_ADDITIONAL_PORT downto 1) => RDO_ADDITIONAL_FINISHED,
+ FEE_TRG_STATUSBITS_IN(31 downto 0) => RDO_TRG_STATUSBITS_IN,
+ FEE_TRG_STATUSBITS_IN(RDO_ADDITIONAL_PORT*32+31 downto 32) => RDO_ADDITIONAL_STATUSBITS_IN,
+ FEE_DATA_IN(31 downto 0) => RDO_DATA_IN,
+ FEE_DATA_IN(RDO_ADDITIONAL_PORT*32+31 downto 32) => RDO_ADDITIONAL_DATA,
+ FEE_DATA_WRITE_IN(0) => RDO_DATA_WRITE_IN,
+ FEE_DATA_WRITE_IN(RDO_ADDITIONAL_PORT downto 1) => RDO_ADDITIONAL_WRITE,
+ FEE_DATA_FINISHED_IN(0) => RDO_DATA_FINISHED_IN,
+ FEE_DATA_FINISHED_IN(RDO_ADDITIONAL_PORT downto 1) => RDO_ADDITIONAL_FINISHED,
+ FEE_DATA_ALMOST_FULL_OUT => open,
TMG_TRG_ERROR_IN => '0',
--Status Registers
RDO_INVALID_TRG_OUT <= lvl1_invalid_i;
RDO_TRG_DATA_VALID_OUT <= lvl1_data_valid_i;
+ RDO_TRG_TYPE_OUT <= lvl1_trg_type;
+ RDO_TRG_CODE_OUT <= lvl1_trg_code;
+ RDO_TRG_INFORMATION_OUT <= lvl1_trg_information;
+ RDO_TRG_NUMBER_OUT <= lvl1_trg_number;
+
+
proc_buf_status : process(CLK)
variable tmp : integer range 0 to 15;
begin
-------------------------------------------------
-- Common Status Register
-------------------------------------------------
- proc_gen_common_stat_regs : process(common_stat, stat_lvl1_handler, lvl1_trg_information,
+ proc_gen_common_stat_regs : process(stat_lvl1_handler, lvl1_trg_information,
lvl1_trg_type, lvl1_trg_number, lvl1_trg_code,
stat_counters_lvl1_handler, int_trigger_num)
begin
- COMMON_STAT_REGS <= common_stat;
- COMMON_STAT_REGS(4) <= stat_lvl1_handler(12);
- COMMON_STAT_REGS(13) <= stat_lvl1_handler(7);
- COMMON_STAT_REGS(47 downto 32) <= int_trigger_num;
- COMMON_STAT_REGS(127 downto 64) <= stat_lvl1_handler;
- COMMON_STAT_REGS(159 downto 128) <= (others => '0');
- COMMON_STAT_REGS(175 downto 160) <= lvl1_trg_information(15 downto 0);
- COMMON_STAT_REGS(179 downto 176) <= lvl1_trg_type;
- COMMON_STAT_REGS(183 downto 180) <= lvl1_trg_number(3 downto 0);
- COMMON_STAT_REGS(191 downto 184) <= lvl1_trg_code;
- COMMON_STAT_REGS(271 downto 192) <= stat_counters_lvl1_handler;
- COMMON_STAT_REGS(287 downto 272) <= (others => '0');
+ common_stat(4) <= stat_lvl1_handler(12);
+ common_stat(13) <= stat_lvl1_handler(7);
+ common_stat(47 downto 32) <= int_trigger_num;
+ common_stat(127 downto 64) <= stat_lvl1_handler;
+ common_stat(159 downto 128) <= (others => '0');
+ common_stat(175 downto 160) <= lvl1_trg_information(15 downto 0);
+ common_stat(179 downto 176) <= lvl1_trg_type;
+ common_stat(183 downto 180) <= lvl1_trg_number(3 downto 0);
+ common_stat(191 downto 184) <= lvl1_trg_code;
+ common_stat(271 downto 192) <= stat_counters_lvl1_handler;
+ common_stat(287 downto 272) <= (others => '0');
end process;
process(CLK)
begin
if rising_edge(CLK) then
if ipu_start_readout_i = '1' then
- COMMON_STAT_REGS(63 downto 48) <= ipu_number_i;
+ common_stat(63 downto 48) <= ipu_number_i;
end if;
end if;
end process;
+
+COMMON_STAT_REGS <= common_stat;
---------------------------------------------------------------------------
-- RegIO Bus Handler
---------------------------------------------------------------------------
EXT_CLOCK : integer range 0 to 1 := c_NO;\r
USE_200_MHZ: integer range 0 to 1 := c_YES;\r
USE_125_MHZ: integer range 0 to 1 := c_NO;\r
- USE_CTC : integer range 0 to 1 := c_YES\r
+ USE_CTC : integer range 0 to 1 := c_YES;\r
+ USE_SLAVE : integer range 0 to 1 := c_NO\r
);\r
port(\r
CLK : in std_logic; -- SerDes clock\r
MED_DATAREADY_OUT : out std_logic;\r
MED_READ_IN : in std_logic;\r
REFCLK2CORE_OUT : out std_logic;\r
+ CLK_RX_HALF_OUT : out std_logic;\r
+ CLK_RX_FULL_OUT : out std_logic;\r
+ \r
--SFP Connection\r
SD_RXD_P_IN : in std_logic;\r
SD_RXD_N_IN : in std_logic;\r
SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
SD_TXDIS_OUT : out std_logic; -- SFP disable\r
+ --Control Interface\r
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
+ SCI_READ : in std_logic := '0';\r
+ SCI_WRITE : in std_logic := '0';\r
+ SCI_ACK : out std_logic := '0';\r
-- Status and control port\r
STAT_OP : out std_logic_vector (15 downto 0);\r
CTRL_OP : in std_logic_vector (15 downto 0);\r
SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable\r
+ --Control Interface\r
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
+ SCI_READ : in std_logic := '0';\r
+ SCI_WRITE : in std_logic := '0';\r
+ SCI_ACK : out std_logic := '0';\r
-- Status and control port\r
STAT_OP : out std_logic_vector (4*16-1 downto 0);\r
CTRL_OP : in std_logic_vector (4*16-1 downto 0);\r
jspc29 / trbnet.git / commitdiff