entity pulse_sync is\r
port(\r
CLK_A_IN : in std_logic;\r
- RESET_A_IN : in std_logic;\r
+ RESET_A_IN : in std_logic := '0';\r
PULSE_A_IN : in std_logic;\r
CLK_B_IN : in std_logic;\r
- RESET_B_IN : in std_logic;\r
+ RESET_B_IN : in std_logic := '0';\r
PULSE_B_OUT : out std_logic\r
);\r
end;\r
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use IEEE.std_logic_arith.all;
+
+library work;
+
+entity trb_net16_ipu2gbe is
+port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ -- IPU interface directed toward the CTS
+ CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
+ CTS_CODE_IN : in std_logic_vector (7 downto 0);
+ CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
+ CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
+ CTS_START_READOUT_IN : in std_logic;
+ CTS_READ_IN : in std_logic;
+ CTS_DATA_OUT : out std_logic_vector (31 downto 0);
+ CTS_DATAREADY_OUT : out std_logic;
+ CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
+ CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
+ -- Data from Frontends
+ FEE_DATA_IN : in std_logic_vector (15 downto 0);
+ FEE_DATAREADY_IN : in std_logic;
+ FEE_READ_OUT : out std_logic;
+ FEE_BUSY_IN : in std_logic;
+ FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
+ -- slow control interface
+ START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
+ BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
+ CONFIG_DONE_IN : in std_logic; -- configuration finished
+ DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
+ DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
+ MULT_EVT_ENABLE_IN : in std_logic;
+ MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10
+ MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10
+ READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
+ READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
+
+ SCTRL_DUMMY_SIZE_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ SCTRL_DUMMY_PAUSE_IN : in std_logic_vector(31 downto 0) := (others => '0');
+
+ -- PacketConstructor interface
+ ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
+ PC_WR_EN_OUT : out std_logic;
+ PC_DATA_OUT : out std_logic_vector (7 downto 0);
+ PC_READY_IN : in std_logic;
+ PC_SOS_OUT : out std_logic;
+ PC_EOS_OUT : out std_logic; -- gk 07.10.10
+ PC_EOD_OUT : out std_logic;
+ PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
+ PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
+ PC_PADDING_OUT : out std_logic;
+ MONITOR_OUT : out std_logic_vector(223 downto 0);
+ DEBUG_OUT : out std_logic_vector(383 downto 0)
+);
+end entity;
+
+architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is
+
+-- attribute HGROUP : string;
+-- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe";
+
+component fifo_32kx16x8_mb2
+port(
+ Data : in std_logic_vector(17 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ AmEmptyThresh : in std_logic_vector(15 downto 0);
+ AmFullThresh : in std_logic_vector(14 downto 0);
+ Q : out std_logic_vector(8 downto 0);
+ WCNT : out std_logic_vector(15 downto 0);
+ RCNT : out std_logic_vector(16 downto 0);
+ Empty : out std_logic;
+ AlmostEmpty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic
+);
+end component;
+
+type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE, RESET_FIFO);
+signal saveCurrentState, saveNextState : saveStates;
+signal state : std_logic_vector(3 downto 0);
+signal data_req_comb : std_logic;
+signal data_req : std_logic; -- request data signal, will be used for fee_read generation
+signal rst_saved_ctr_comb : std_logic;
+signal rst_saved_ctr : std_logic;
+
+signal fee_read_comb : std_logic;
+signal fee_read : std_logic; -- fee_read signal
+signal saved_ctr : std_logic_vector(16 downto 0);
+signal ce_saved_ctr : std_logic;
+
+-- header data
+signal cts_rnd : std_logic_vector(15 downto 0);
+signal cts_rnd_saved : std_logic;
+signal cts_trg : std_logic_vector(15 downto 0);
+signal cts_trg_saved : std_logic;
+signal cts_len : std_logic_vector(16 downto 0);
+signal cts_len_saved : std_logic;
+
+-- CTS interface
+signal cts_error_pattern : std_logic_vector(31 downto 0);
+signal cts_length : std_logic_vector(15 downto 0);
+signal cts_readout_finished : std_logic;
+signal cts_dataready : std_logic;
+signal cts_data : std_logic_vector(31 downto 0);
+
+-- Split FIFO signals
+signal sf_data : std_logic_vector(15 downto 0);
+signal sf_wr_en_comb : std_logic;
+signal sf_wr_en : std_logic; -- write signal for FIFO
+signal sf_rd_en_comb : std_logic;
+signal sf_rd_en : std_logic; -- read signal for FIFO
+signal sf_wcnt : std_logic_vector(15 downto 0);
+signal sf_rcnt : std_logic_vector(16 downto 0);
+signal sf_empty : std_logic;
+signal sf_aempty : std_logic;
+signal sf_full : std_logic;
+signal sf_afull : std_logic;
+
+-------------------------------------------------------------------
+type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2);
+signal loadCurrentState, loadNextState : loadStates;
+signal state2 : std_logic_vector(3 downto 0);
+
+signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data
+signal rst_rem_ctr_comb : std_logic;
+signal rst_rem_ctr : std_logic; -- reset the remove counter
+signal rst_regs_comb : std_logic;
+signal rst_regs : std_logic; -- reset storage registers
+signal rem_phase_comb : std_logic;
+signal rem_phase : std_logic; -- header remove phase
+signal data_phase_comb : std_logic;
+signal data_phase : std_logic; -- data transport phase from split fifo to PC
+signal pad_phase_comb : std_logic;
+signal pad_phase : std_logic; -- padding phase
+signal calc_pad_comb : std_logic;
+signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE
+signal pad_data_comb : std_logic;
+signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value
+
+signal pc_sos_comb : std_logic;
+signal pc_sos : std_logic; -- start of data signal
+signal pc_eod_comb : std_logic;
+signal pc_eod : std_logic; -- end of data signal
+
+signal ce_rem_ctr_comb : std_logic;
+signal ce_rem_ctr : std_logic; -- count enable for remove counter
+signal remove_done_comb : std_logic;
+signal remove_done : std_logic; -- end of header stripping process
+signal read_done_comb : std_logic;
+signal read_done : std_logic; -- end of data phase (read phase from SF)
+
+signal pc_data : std_logic_vector(7 downto 0);
+signal pc_data_q : std_logic_vector(7 downto 0);
+signal pc_trig_nr : std_logic_vector(15 downto 0);
+signal pc_sub_size : std_logic_vector(17 downto 0);
+signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo
+signal padding_needed : std_logic;
+signal pc_wr_en_comb : std_logic;
+signal pc_wr_en_q : std_logic;
+signal pc_wr_en_qq : std_logic;
+signal pc_wr_en_qqq : std_logic;
+signal pc_eod_q : std_logic;
+
+signal debug : std_logic_vector(383 downto 0);
+
+-- gk
+signal bank_select : std_logic_vector(3 downto 0);
+signal save_addr_comb : std_logic;
+signal save_addr : std_logic;
+signal addr_saved_comb : std_logic;
+signal addr_saved : std_logic;
+signal start_config : std_logic;
+signal config_done : std_logic;
+signal add_sub_state : std_logic;
+signal add_sub_state_comb : std_logic;
+signal add_sub_ctr : std_logic_vector(3 downto 0);
+signal load_sub : std_logic;
+signal load_sub_comb : std_logic;
+signal load_sub_done : std_logic;
+signal load_sub_done_comb : std_logic;
+signal load_sub_ctr : std_logic_vector(3 downto 0);
+signal load_sub_ctr_comb : std_logic;
+signal actual_message_size : std_logic_vector(31 downto 0);
+signal more_subevents : std_logic;
+signal trig_random : std_logic_vector(7 downto 0);
+signal readout_ctr : std_logic_vector(23 downto 0);
+signal readout_ctr_lock : std_logic;
+signal pc_trig_nr_q : std_logic_vector(31 downto 0);
+
+-- gk 20.07.10
+signal inc_data_ctr : std_logic_vector(31 downto 0);
+signal dropped_sm_events_ctr : std_logic_vector(31 downto 0);
+signal dropped_lr_events_ctr : std_logic_vector(31 downto 0);
+signal dropped_ctr : std_logic_vector(31 downto 0);
+-- gk 22.07.10
+signal headers_invalid : std_logic;
+signal headers_invalid_ctr : std_logic_vector(31 downto 0);
+signal cts_len_q : std_logic_vector(15 downto 0);
+signal cts_trg_q : std_logic_vector(15 downto 0);
+signal cts_rnd_q : std_logic_vector(15 downto 0);
+signal first_run_trg : std_logic_vector(15 downto 0);
+signal first_run_addr : std_logic_vector(15 downto 0);
+signal first_run_lock : std_logic;
+signal cts_addr : std_logic_vector(15 downto 0);
+signal cts_addr_q : std_logic_vector(15 downto 0);
+signal cts_addr_saved : std_logic;
+
+-- gk 24.07.10
+signal save_eod : std_logic;
+signal save_eod_comb : std_logic;
+
+signal load_eod : std_logic;
+signal endpoint_addr : std_logic_vector(15 downto 0);
+signal endp_addr_lock : std_logic;
+
+signal saved_events_ctr : std_logic_vector(15 downto 0);
+signal loaded_events_ctr : std_logic_vector(15 downto 0);
+signal constr_events_ctr : std_logic_vector(31 downto 0);
+signal event_waiting : std_logic;
+
+signal drop_sub : std_logic;
+signal drop_sub_comb : std_logic;
+signal drop_event : std_logic;
+signal drop_event_comb : std_logic;
+signal drop_small : std_logic;
+signal drop_large : std_logic;
+signal drop_headers : std_logic;
+signal drop_small_comb : std_logic;
+signal drop_large_comb : std_logic;
+signal drop_headers_comb : std_logic;
+signal inc_trg_ctr : std_logic;
+signal inc_trg_ctr_comb : std_logic;
+
+signal invalid_hsize_ctr : std_logic_vector(15 downto 0);
+signal invalid_hsize_lock : std_logic;
+
+signal load_eod_q : std_logic;
+signal read_size_q : std_logic_vector(17 downto 0);
+
+-- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked
+signal sf_real_wr_en : std_logic;
+
+-- gk 01.10.10
+signal found_empty_evt : std_logic;
+signal found_empty_evt_comb : std_logic;
+signal found_empty_evt_ctr : std_logic_vector(31 downto 0);
+
+-- gk 06.10.10
+signal message_size : std_logic_vector(31 downto 0);
+
+-- gk 07.12.10
+signal prev_bank_select : std_logic_vector(3 downto 0);
+signal first_event : std_logic;
+
+signal reset_split_fifo : std_logic;
+
+signal input_data_ctr : std_logic_vector(31 downto 0);
+
+-- SIMPLE SENDER STUFF
+type gen_states is (IDLE, WAIT_FOR_PC, GENERATE_DATA, CLEANUP);
+signal gen_current_state, gen_next_state : gen_states;
+
+signal gen_data_ctr : std_logic_vector(15 downto 0);
+
+begin
+
+BANK_SELECT_OUT <= bank_select; -- gk 27.03.10
+START_CONFIG_OUT <= start_config; -- gk 27.03.10
+config_done <= CONFIG_DONE_IN; -- gk 29.03.10
+
+-- CTS interface signals
+cts_error_pattern <= (others => '0'); -- FAKE
+
+cts_length <= x"0000"; -- length of data payload is always 0
+cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1'
+
+cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0';
+
+cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE)
+ else '0';
+
+-- Byte swapping... done here. TAKE CARE!
+-- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes
+-- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port.
+-- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped
+-- for GbE inside the packet constructor.
+--
+-- Long live the Endianess!
+
+-- Sync all critical pathes
+THE_SYNC_PROC: process( CLK )
+begin
+ if( rising_edge(CLK) ) then
+ --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below
+ sf_wr_en <= sf_wr_en_comb;
+ ce_rem_ctr <= ce_rem_ctr_comb;
+ sf_rd_en <= sf_rd_en_comb;
+ fee_read <= fee_read_comb;
+ read_done <= read_done_comb;
+ pc_eod_q <= pc_eod;
+ pc_wr_en_qqq <= pc_wr_en_qq;
+ pc_wr_en_qq <= pc_wr_en_q;
+ pc_wr_en_q <= pc_wr_en_comb;
+ end if;
+end process THE_SYNC_PROC;
+
+-- gk 27.03.10 data selector for sf to write the evt builder address on top of data
+SF_DATA_PROC : process( CLK )
+begin
+ if( rising_edge(CLK) ) then
+ if (RESET = '1') then -- gk 31.05.10
+ sf_data <= (others => '0');
+ elsif( save_addr = '1' ) then
+ sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address
+ sf_data(15 downto 4) <= x"abc";
+ -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent
+ elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then
+ sf_data <= x"0001"; -- gk 11.06.10
+ elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then
+ sf_data <= x"5555"; -- gk 11.06.10
+ elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then
+ sf_data <= FEE_STATUS_BITS_IN(31 downto 16);
+ elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then
+ sf_data <= FEE_STATUS_BITS_IN(15 downto 0);
+ else
+ sf_data <= FEE_DATA_IN;
+ end if;
+ end if;
+end process SF_DATA_PROC;
+
+-- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY
+fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled
+ else '0';
+
+-- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY
+sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled
+ (save_addr = '1') or
+ (add_sub_state = '1') -- gk 29.03.10 save the subsubevent
+ else '0';
+
+-- gk 06.08.10
+sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0';
+
+-- gk 27.03.10 do not count evt builder address as saved ipu bytes
+--ce_saved_ctr <= sf_wr_en;
+ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en;
+
+-- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO
+saveMachineProc: process( CLK )
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ saveCurrentState <= SIDLE;
+ data_req <= '0';
+ rst_saved_ctr <= '0';
+ save_addr <= '0'; -- gk 27.03.10
+ addr_saved <= '0'; -- gk 27.03.10
+ add_sub_state <= '0'; -- gk 29.03.10
+ save_eod <= '0'; -- gk 25.07.10
+ else
+ saveCurrentState <= saveNextState;
+ data_req <= data_req_comb;
+ rst_saved_ctr <= rst_saved_ctr_comb;
+ save_addr <= save_addr_comb; -- gk 27.03.10
+ addr_saved <= addr_saved_comb; -- gk 27.03.10
+ add_sub_state <= add_sub_state_comb; -- gk 29.03.10
+ save_eod <= save_eod_comb; -- gk 25.07.10
+ end if;
+ end if;
+end process saveMachineProc;
+
+saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN, input_data_ctr, MAX_MESSAGE_SIZE_IN)
+begin
+ saveNextState <= SIDLE;
+ data_req_comb <= '0';
+ rst_saved_ctr_comb <= '0';
+ save_addr_comb <= '0'; -- gk 27.03.10
+ addr_saved_comb <= '0'; -- gk 27.03.10
+ add_sub_state_comb <= '0'; -- gk 29.03.10
+ save_eod_comb <= '0'; -- gk 25.07.10
+ case saveCurrentState is
+ when SIDLE =>
+ state <= x"0";
+ if (CTS_START_READOUT_IN = '1') then
+ saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10
+ data_req_comb <= '1';
+ rst_saved_ctr_comb <= '1';
+ else
+ saveNextState <= SIDLE;
+ end if;
+ -- gk 27.03.10
+ when SAVE_EVT_ADDR =>
+ state <= x"5";
+ saveNextState <= WAIT_FOR_DATA;
+ data_req_comb <= '1';
+ save_addr_comb <= '1';
+ when WAIT_FOR_DATA =>
+ state <= x"1";
+ if (FEE_BUSY_IN = '1') then
+ saveNextState <= SAVE_DATA;
+ data_req_comb <= '1';
+ else
+ saveNextState <= WAIT_FOR_DATA;
+ data_req_comb <= '1';
+ end if;
+ addr_saved_comb <= '1'; -- gk 27.03.10
+ when SAVE_DATA =>
+ state <= x"2";
+ if (FEE_BUSY_IN = '0') then
+ saveNextState <= TERMINATE;
+ else
+ saveNextState <= SAVE_DATA;
+ data_req_comb <= '1';
+ end if;
+ when TERMINATE =>
+ state <= x"3";
+ if (CTS_READ_IN = '1') then
+ saveNextState <= SCLOSE;
+ else
+ saveNextState <= TERMINATE;
+ end if;
+ when SCLOSE =>
+ state <= x"4";
+ if (CTS_START_READOUT_IN = '0') then
+ if (input_data_ctr > MAX_MESSAGE_SIZE_IN) then -- gk 06.11.2012
+ saveNextState <= RESET_FIFO;
+ else
+ saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10
+ end if;
+ else
+ saveNextState <= SCLOSE;
+ end if;
+ -- gk 06.11.2012
+ when RESET_FIFO =>
+ saveNextState <= SIDLE;
+ state <= x"E";
+ -- gk 29.03.10 new states during which the subsub bytes are saved
+ when ADD_SUBSUB1 =>
+ state <= x"6";
+ saveNextState <= ADD_SUBSUB2;
+ add_sub_state_comb <= '1';
+ when ADD_SUBSUB2 =>
+ state<= x"7";
+ saveNextState <= ADD_SUBSUB3;
+ add_sub_state_comb <= '1';
+ save_eod_comb <= '1';
+ when ADD_SUBSUB3 =>
+ state<= x"8";
+ saveNextState <= ADD_SUBSUB4;
+ add_sub_state_comb <= '1';
+ when ADD_SUBSUB4 =>
+ state<= x"9";
+ saveNextState <= SIDLE;
+ add_sub_state_comb <= '1';
+ when others =>
+ state <= x"f";
+ saveNextState <= SIDLE;
+ end case;
+end process saveMachine;
+
+-- gk 06.11.2012
+INPUT_DATA_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or rst_saved_ctr = '1') then
+ input_data_ctr <= (others => '0');
+ elsif (saveCurrentState = SAVE_DATA and sf_real_wr_en = '1') then
+ input_data_ctr(31 downto 1) <= input_data_ctr(31 downto 1) + x"1";
+ end if;
+ end if;
+end process INPUT_DATA_CTR_PROC;
+
+-- gk 29.03.10
+ADD_SUB_CTR_PROC : process( CLK )
+begin
+ if( rising_edge( CLK ) ) then
+ if( (RESET = '1') or (rst_saved_ctr = '1') ) then
+ add_sub_ctr <= (others => '0');
+ elsif( add_sub_state = '1' ) then
+ add_sub_ctr <= add_sub_ctr + 1;
+ end if;
+ end if;
+end process ADD_SUB_CTR_PROC;
+
+--********
+-- SAVE INCOMING EVENT HEADERS
+--********
+
+-- Counter for header word storage
+THE_CTS_SAVED_CTR: process( CLK )
+begin
+ if( rising_edge(CLK) ) then
+ if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
+ saved_ctr <= (others => '0');
+ elsif( ce_saved_ctr = '1' ) then
+ saved_ctr <= saved_ctr + 1;
+ end if;
+ end if;
+end process THE_CTS_SAVED_CTR;
+
+-- save triggerRnd from incoming data for cts response
+CTS_RND_PROC: process( CLK )
+begin
+ if( rising_edge(CLK) ) then
+ if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
+ cts_rnd <= (others => '0');
+ cts_rnd_saved <= '0';
+ elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then
+ cts_rnd <= sf_data;
+ cts_rnd_saved <= '1';
+ end if;
+ end if;
+end process CTS_RND_PROC;
+
+-- save triggerNr from incoming data for cts response
+CTS_TRG_PROC: process( CLK )
+begin
+ if( rising_edge(CLK) ) then
+ if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
+ cts_trg <= (others => '0');
+ cts_trg_saved <= '0';
+ elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then
+ cts_trg <= sf_data;
+ cts_trg_saved <= '1';
+ end if;
+ end if;
+end process CTS_TRG_PROC;
+
+-- save size from incoming data for cts response (future) and to get rid of padding
+--CTS_SIZE_PROC: process( CLK )
+--begin
+-- if( rising_edge(CLK) ) then
+-- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
+-- cts_len <= (others => '0');
+-- cts_len_saved <= '0';
+-- elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then
+-- cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words
+-- cts_len(0) <= '0';
+-- elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then
+-- cts_len <= cts_len + x"4";
+-- cts_len_saved <= '1';
+-- end if;
+-- end if;
+--end process CTS_SIZE_PROC;
+
+-- gk 22.07.10
+--CTS_ADDR_PROC : process(CLK)
+--begin
+-- if( rising_edge(CLK) ) then
+-- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
+-- cts_addr <= (others => '0');
+-- cts_addr_saved <= '0';
+-- elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then
+-- cts_addr <= sf_data;
+-- cts_addr_saved <= '1';
+-- end if;
+-- end if;
+--end process CTS_ADDR_PROC;
+
+--******
+-- SAVE FIRST EVENT HEADER VALUES
+--******
+
+-- gk 22.07.10
+--FIRST_RUN_PROC : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- first_run_trg <= (others => '0');
+-- first_run_addr <= (others => '0');
+-- first_run_lock <= '0';
+-- elsif (first_run_lock = '0') and (cts_addr_saved = '1') then
+-- first_run_trg <= cts_trg;
+-- first_run_addr <= cts_addr;
+-- first_run_lock <= '1';
+-- -- important: value saved by saveMachine but incremented by loadMachine
+-- elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then
+-- first_run_trg <= first_run_trg + x"1";
+-- end if;
+-- end if;
+--end process FIRST_RUN_PROC;
+
+-- gk 25.07.10
+SAVED_EVT_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ saved_events_ctr <= (others => '0');
+ elsif (save_eod = '1') and (input_data_ctr < MAX_MESSAGE_SIZE_IN) then -- gk 06.11.2012
+ saved_events_ctr <= saved_events_ctr + x"1";
+ end if;
+ end if;
+end process SAVED_EVT_CTR_PROC;
+
+
+---- gk 20.07.10
+--INC_DATA_CTR_proc : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') or (rst_saved_ctr = '1') then
+-- inc_data_ctr <= (others => '0');
+-- elsif (sf_wr_en = '1') and (data_req = '1') then
+-- inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1";
+-- end if;
+-- end if;
+--end process INC_DATA_CTR_proc;
+
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+
+-- Split FIFO
+--THE_SPLIT_FIFO: fifo_32kx16x8_mb2
+--port map(
+-- -- Byte swapping for correct byte order on readout side of FIFO
+-- Data(7 downto 0) => sf_data(15 downto 8),
+-- Data(8) => '0',
+-- Data(16 downto 9) => sf_data(7 downto 0),
+-- Data(17) => save_eod,
+-- WrClock => CLK,
+-- RdClock => CLK,
+-- WrEn => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en,
+-- RdEn => sf_rd_en,
+-- Reset => reset_split_fifo, --RESET, -- gk 06.11.2012
+-- RPReset => reset_split_fifo, --RESET, -- gk 06.11.2012
+-- AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead
+-- AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751
+-- Q(7 downto 0) => pc_data,
+-- Q(8) => load_eod,
+-- WCNT => sf_wcnt,
+-- RCNT => sf_rcnt,
+-- Empty => sf_empty,
+-- AlmostEmpty => open, --sf_aempty,
+-- Full => sf_full,
+-- AlmostFull => sf_afull
+--);
+
+sf_aempty <= '0';
+
+reset_split_fifo <= '1' when (saveCurrentState = RESET_FIFO or RESET = '1') else '0';
+
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+
+-- gk 25.07.10
+EVENT_WAITING_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ event_waiting <= '0';
+ elsif (loaded_events_ctr /= saved_events_ctr) then
+ event_waiting <= '1';
+ else
+ event_waiting <= '0';
+ end if;
+ end if;
+end process EVENT_WAITING_PROC;
+
+-- write signal for PC data
+pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or
+ (pad_phase = '1') or
+ ((load_sub = '1') and (sf_rd_en = '1')) or
+ ((drop_sub = '1') and (sf_rd_en = '1')) or
+ ((drop_event = '1') and (sf_rd_en = '1'))
+ else '0';
+
+sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or
+ --( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or
+ ( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or -- gk 26.07.10
+ ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10
+ ( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or
+ ( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') )
+ else '0';
+
+ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') )
+ else '0';
+
+-- FIFO data delay process (also forces padding bytes to known value)
+THE_DATA_DELAY_PROC: process( CLK )
+begin
+ if( rising_edge(CLK) ) then
+ if( pad_data = '1' ) then
+ pc_data_q <= x"aa"; -- padding for 64bit
+ -- gk 21.07.10
+ -- set the error flag if a broken packet is sent
+ elsif (drop_sub = '1') and (load_sub_ctr = x"3") then
+ pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0);
+ else
+ pc_data_q <= pc_data;
+ end if;
+ end if;
+end process THE_DATA_DELAY_PROC;
+
+-- Statemachine for reading the data payload from the SPLIT_FIFO and feeding
+-- it into the packet constructor
+loadMachineProc : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ loadCurrentState <= LIDLE;
+ rst_rem_ctr <= '0';
+ rem_phase <= '0';
+ calc_pad <= '0';
+ data_phase <= '0';
+ pad_phase <= '0';
+ pc_sos <= '0';
+ pc_eod <= '0';
+ rst_regs <= '0';
+ pad_data <= '0';
+ load_sub <= '0'; -- gk 30.03.10
+ drop_sub <= '0'; -- gk 25.07.10
+ drop_event <= '0'; -- gk 25.07.10
+ drop_small <= '0'; -- gk 25.07.10
+ drop_large <= '0'; -- gk 25.07.10
+ drop_headers <= '0'; -- gk 25.07.10
+ inc_trg_ctr <= '0'; -- gk 26.07.10
+ found_empty_evt <= '0'; -- gk 01.10.10
+ else
+ loadCurrentState <= loadNextState;
+ rst_rem_ctr <= rst_rem_ctr_comb;
+ rem_phase <= rem_phase_comb;
+ calc_pad <= calc_pad_comb;
+ data_phase <= data_phase_comb;
+ pad_phase <= pad_phase_comb;
+ pc_sos <= pc_sos_comb;
+ pc_eod <= pc_eod_comb;
+ rst_regs <= rst_regs_comb;
+ pad_data <= pad_data_comb;
+ load_sub <= load_sub_comb; -- gk 30.03.1
+ drop_sub <= drop_sub_comb; -- gk 25.07.10
+ drop_event <= drop_event_comb; -- gk 25.07.10
+ drop_small <= drop_small_comb; -- gk 25.07.10
+ drop_large <= drop_large_comb; -- gk 25.07.10
+ drop_headers <= drop_headers_comb; -- gk 25.07.10
+ inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10
+ found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10
+ end if;
+ end if;
+end process loadMachineProc;
+
+loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed,
+ PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN,
+ MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr,
+ first_run_addr, load_eod, event_waiting, MULT_EVT_ENABLE_IN, message_size, DATA_GBE_ENABLE_IN, first_event,
+ prev_bank_select, bank_select)
+begin
+ loadNextState <= LIDLE;
+ rst_rem_ctr_comb <= '0';
+ rem_phase_comb <= '0';
+ calc_pad_comb <= '0';
+ data_phase_comb <= '0';
+ pad_phase_comb <= '0';
+ pc_sos_comb <= '0';
+ pc_eod_comb <= '0';
+ rst_regs_comb <= '0';
+ pad_data_comb <= '0';
+ load_sub_comb <= '0'; -- gk 30.03.10
+ drop_sub_comb <= '0'; -- gk 25.07.10
+ drop_event_comb <= '0'; -- gk 25.07.10
+ drop_small_comb <= '0'; -- gk 25.07.10
+ drop_large_comb <= '0'; -- gk 25.07.10
+ drop_headers_comb <= '0'; -- gk 25.07.10
+ inc_trg_ctr_comb <= '0'; -- gk 26.07.10
+ found_empty_evt_comb <= '0'; -- gk 01.10.10
+ case loadCurrentState is
+ when LIDLE =>
+ state2 <= x"0";
+ -- gk 23.07.10
+ if( (sf_aempty = '0') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10 -- and (PC_READY_IN = '1')
+ loadNextState <= INIT;
+ rst_rem_ctr_comb <= '1';
+ rst_regs_comb <= '1';
+ else
+ loadNextState <= LIDLE;
+ end if;
+ when INIT =>
+ state2 <= x"1";
+ loadNextState <= REMOVE;
+ rem_phase_comb <= '1';
+ when REMOVE =>
+ state2 <= x"2";
+ if( remove_done = '1' ) then
+ -- gk 06.10.10
+ if (MULT_EVT_ENABLE_IN = '1') then
+ if (message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then
+ --loadNextState <= WAIT_TO_REMOVE;
+ -- gk 07.12.10
+ if (first_event = '0') and (prev_bank_select /= bank_select) then -- check if event builder address changed, if so close the current packet
+ loadNextState <= WAIT_PC;
+ else
+ loadNextState <= WAIT_TO_REMOVE;
+ end if;
+
+ else
+ loadNextState <= WAIT_PC;
+ end if;
+ else
+ loadNextState <= WAIT_TO_REMOVE;
+ end if;
+ inc_trg_ctr_comb <= '1';
+ else
+ loadNextState <= REMOVE;
+ rem_phase_comb <= '1';
+ end if;
+ when WAIT_TO_REMOVE =>
+ if (rem_ctr = x"a") then
+ loadNextState <= DECIDE;
+ else
+ loadNextState <= WAIT_TO_REMOVE;
+ end if;
+ when DECIDE =>
+-- if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then
+-- loadNextState <= PAUSE_BEFORE_DROP1;
+-- drop_large_comb <= '1';
+-- elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10
+-- loadNextState <= CALCA;
+-- found_empty_evt_comb <= '1';
+-- elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then
+-- loadNextState <= PAUSE_BEFORE_DROP1;
+-- drop_small_comb <= '1';
+-- elsif (pc_trig_nr + x"1" /= first_run_trg) then
+-- loadNextState <= PAUSE_BEFORE_DROP1;
+-- drop_headers_comb <= '1';
+-- elsif (endpoint_addr /= first_run_addr) then
+-- loadNextState <= PAUSE_BEFORE_DROP1;
+-- drop_headers_comb <= '1';
+-- else
+ loadNextState <= CALCA;
+-- end if;
+ calc_pad_comb <= '1';
+ when CALCA =>
+ state2 <= x"3";
+ loadNextState <= CALCB;
+ pc_sos_comb <= '1';
+ when CALCB =>
+ -- we need a branch in case of length "0"!!!!
+ state2 <= x"4";
+ loadNextState <= LOAD;
+ data_phase_comb <= '1';
+ when LOAD =>
+ state2 <= x"5";
+ if (load_eod = '1') then
+ loadNextState <= LOAD_SUBSUB;
+ else
+ loadNextState <= LOAD;
+ data_phase_comb <= '1';
+ end if;
+ -- gk 31.03.10
+ when LOAD_SUBSUB =>
+ state2 <= x"d";
+ if( load_sub_done = '1' ) then
+ if( padding_needed = '0' ) then
+ loadNextState <= CALCC;
+ else
+ loadNextState <= PAD0;
+ pad_phase_comb <= '1';
+ end if;
+ else
+ loadNextState <= LOAD_SUBSUB;
+ load_sub_comb <= '1';
+ end if;
+ when PAD0 =>
+ state2 <= x"6";
+ loadNextState <= PAD1;
+ pad_phase_comb <= '1';
+ pad_data_comb <= '1';
+ when PAD1 =>
+ state2 <= x"7";
+ loadNextState <= PAD2;
+ pad_phase_comb <= '1';
+ pad_data_comb <= '1';
+ when PAD2 =>
+ state2 <= x"8";
+ loadNextState <= PAD3;
+ pad_phase_comb <= '1';
+ pad_data_comb <= '1';
+ when PAD3 =>
+ state2 <= x"9";
+ loadNextState <= CALCC;
+ pad_data_comb <= '1';
+ when CALCC =>
+ state2 <= x"a";
+ if (MULT_EVT_ENABLE_IN = '1') then
+ loadNextState <= LIDLE;
+ else
+ loadNextState <= CLOSE;
+ end if;
+ pc_eod_comb <= '1';
+ when CLOSE =>
+ state2 <= x"b";
+ loadNextState <= WAIT_PC;
+ --rst_regs_comb <= '1'; -- gk 07.10.10
+ when WAIT_PC =>
+ state2 <= x"c";
+ if( PC_READY_IN = '1' ) then
+ -- gk 06.10.10
+ if (MULT_EVT_ENABLE_IN = '1') then
+ loadNextState <= WAIT_TO_REMOVE;
+ else
+ loadNextState <= LIDLE;
+ end if;
+ else
+ loadNextState <= WAIT_PC;
+ end if;
+ when PAUSE_BEFORE_DROP1 =>
+ loadNextState <= PAUSE_BEFORE_DROP2;
+ pc_sos_comb <= '1';
+ when PAUSE_BEFORE_DROP2 =>
+ loadNextState <= DROP;
+ drop_event_comb <= '1';
+ -- gk 23.07.10
+ when DROP =>
+ state2 <= x"e";
+ -- when data is dropped the eod marker stands as its end
+ if (load_eod = '1') then
+ loadNextState <= DROP_SUBSUB;
+ else
+ loadNextState <= DROP;
+ drop_event_comb <= '1';
+ end if;
+ -- gk 25.07.10
+ when DROP_SUBSUB =>
+ if (load_sub_done = '1') then
+ if( padding_needed = '0' ) then
+ loadNextState <= CALCC;
+ else
+ loadNextState <= PAD0;
+ pad_phase_comb <= '1';
+ end if;
+ else
+ loadNextState <= DROP_SUBSUB;
+ drop_sub_comb <= '1';
+ end if;
+ when others =>
+ state2 <= x"f";
+ loadNextState <= LIDLE;
+ end case;
+end process loadMachine;
+
+-- gk 25.07.10
+--INVALID_STATS_PROC : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- dropped_lr_events_ctr <= (others => '0');
+-- dropped_sm_events_ctr <= (others => '0');
+-- headers_invalid_ctr <= (others => '0');
+-- dropped_ctr <= (others => '0');
+-- invalid_hsize_ctr <= (others => '0');
+-- found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10
+-- elsif (rst_regs = '1') then
+-- invalid_hsize_lock <= '0';
+-- elsif (drop_small = '1') then
+-- dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1";
+-- dropped_ctr <= dropped_ctr + x"1";
+-- elsif (drop_large = '1') then
+-- dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1";
+-- dropped_ctr <= dropped_ctr + x"1";
+-- elsif (drop_headers = '1') then
+-- headers_invalid_ctr <= headers_invalid_ctr + x"1";
+-- dropped_ctr <= dropped_ctr + x"1";
+-- elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ??
+-- invalid_hsize_ctr <= invalid_hsize_ctr + x"1";
+-- invalid_hsize_lock <= '1';
+-- -- gk 01.10.10
+-- elsif (found_empty_evt = '1') then
+-- found_empty_evt_ctr <= found_empty_evt_ctr + x"1";
+-- end if;
+-- end if;
+--end process INVALID_STATS_PROC;
+
+-- gk 05.08.10
+INVALID_H_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ load_eod_q <= load_eod;
+ read_size_q <= read_size;
+ end if;
+end process INVALID_H_PROC;
+
+-- gk 26.04.10
+READOUT_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then
+ readout_ctr <= READOUT_CTR_IN;
+ readout_ctr_lock <= '0';
+ elsif (pc_sos = '1') then
+ readout_ctr <= readout_ctr + x"1";
+ end if;
+ end if;
+end process READOUT_CTR_PROC;
+
+--******
+-- SELECTION OF EVENT BUILDER
+--******
+
+-- gk 27.03.10
+bank_select_proc : process( CLK )
+begin
+ if rising_edge( CLK ) then
+ -- gk 29.03.10
+ if( (RESET = '1') or (rst_regs = '1') ) then
+ bank_select <= "0000";
+ -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q
+ elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then
+ bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0);
+ end if;
+ end if;
+end process bank_select_proc;
+
+-- gk 07.12.10
+first_event_proc : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (loadCurrentState = WAIT_PC) then
+ first_event <= '1';
+ elsif (remove_done = '1') then
+ first_event <= '0';
+ end if;
+ end if;
+end process first_event_proc;
+
+-- gk 07.12.10
+prev_bank_proc : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (loadCurrentState = WAIT_PC) then
+ prev_bank_select <= "0000";
+ elsif ((sf_rd_en = '1') and (rem_ctr = x"3") and (first_event = '1')) then
+ prev_bank_select <= bank_select;
+ end if;
+ end if;
+end process prev_bank_proc;
+
+
+-- gk 29.03.10
+start_config_proc : process( CLK )
+begin
+ if rising_edge( CLK ) then
+ if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then
+ start_config <= '0';
+ elsif( (sf_rd_en = '1') and (rem_ctr = x"2") and (first_event = '1') ) then -- gk 01.06.10
+ start_config <= '1';
+ end if;
+ end if;
+end process start_config_proc;
+
+
+--******
+-- LOAD SUBSUBEVENT
+--******
+
+-- gk 30.03.10
+load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') )
+ else '0';
+
+-- gk 30.03.10
+LOAD_SUB_CTR_PROC: process( CLK )
+begin
+ if( rising_edge(CLK) ) then
+ if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
+ load_sub_ctr <= (others => '0');
+ elsif( (load_sub_ctr_comb = '1') ) then
+ load_sub_ctr <= load_sub_ctr + 1;
+ end if;
+ end if;
+end process LOAD_SUB_CTR_PROC;
+
+-- gk 30.03.10
+-- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or
+-- ((load_sub_ctr = x"4") and (drop_sub = '1'))
+-- else '0';
+load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0';
+
+-- gk 30.03.10
+LOAD_SUB_DONE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
+ load_sub_done <= '0';
+ else
+ load_sub_done <= load_sub_done_comb;
+ end if;
+ end if;
+end process LOAD_SUB_DONE_PROC;
+
+--******
+-- EXTRACT EVENT HEADERS FROM SPLITFIFO
+--******
+
+-- Counter for stripping the unneeded parts of the data stream, and saving the important parts
+THE_REMOVE_CTR: process( CLK )
+begin
+ if( rising_edge(CLK) ) then
+ if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
+ rem_ctr <= (others => '0');
+ elsif( (ce_rem_ctr = '1') ) then
+ rem_ctr <= rem_ctr + 1;
+ end if;
+ end if;
+end process THE_REMOVE_CTR;
+
+remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address
+
+THE_REM_DONE_SYNC: process( CLK )
+begin
+ if( rising_edge(CLK) ) then
+ if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
+ remove_done <= '0';
+ else
+ remove_done <= remove_done_comb;
+ end if;
+ end if;
+end process THE_REM_DONE_SYNC;
+
+-- gk 26.04.10
+TRIG_RANDOM_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if ((RESET = '1') or (rst_regs = '1')) then
+ trig_random <= (others => '0');
+ elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then
+ trig_random <= pc_data;
+ end if;
+ end if;
+end process TRIG_RANDOM_PROC;
+
+-- extract the trigger number from splitfifo data
+THE_TRG_NR_PROC: process( CLK )
+begin
+ if rising_edge(CLK) then
+ if ( (RESET = '1') or (rst_regs = '1') ) then
+ pc_trig_nr <= (others => '0');
+ elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10
+ pc_trig_nr(7 downto 0) <= pc_data;
+ elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10
+ pc_trig_nr(15 downto 8) <= pc_data;
+ end if;
+ end if;
+end process THE_TRG_NR_PROC;
+
+-- extract the subevent size from the splitfifo data, convert it from 32b to 8b units,
+-- and in case of padding needed increase it accordingly
+THE_SUB_SIZE_PROC: process( CLK )
+begin
+ if( rising_edge(CLK) ) then
+ if ( (RESET = '1') or (rst_regs = '1') ) then
+ pc_sub_size <= (others => '0');
+ elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
+ pc_sub_size(9 downto 2) <= pc_data;
+ elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
+ pc_sub_size(17 downto 10) <= pc_data;
+ -- gk 20.07.10
+ -- gk 30.03.10 bug fixed in the way that is written below
+ -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save
+ elsif( (calc_pad = '1') and (padding_needed = '1') ) then
+ pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!!
+ elsif( (calc_pad = '1') and (padding_needed = '0') ) then
+ pc_sub_size <= pc_sub_size + x"8";
+ end if;
+ end if;
+end process THE_SUB_SIZE_PROC;
+
+-- gk 06.10.10
+MESSAGE_SIZE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- message_size <= (others => '0');
+-- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then
+-- message_size <= (others => '0');
+-- elsif (pc_sos = '1') then
+-- message_size <= message_size + pc_sub_size;
+-- end if;
+ if (RESET = '1') then
+ message_size <= x"0000_0028";
+ elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then
+ message_size <= x"0000_0028";
+ elsif ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) then
+ message_size <= x"0000_0028";
+ elsif (pc_sos = '1') then
+ message_size <= message_size + pc_sub_size + x"10"; -- gk 06.12.10 add 16B for subevent headers
+ end if;
+ end if;
+end process MESSAGE_SIZE_PROC;
+
+
+-- gk 25.07.10
+ENDP_ADDRESS_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (rst_regs = '1') then
+ endpoint_addr <= (others => '0');
+ endp_addr_lock <= '0';
+ elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then
+ endpoint_addr(7 downto 0) <= pc_data;
+ endp_addr_lock <= '1';
+ elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then
+ endpoint_addr(15 downto 8) <= pc_data;
+ endp_addr_lock <= '0';
+ end if;
+ end if;
+end process ENDP_ADDRESS_PROC;
+
+
+
+-- check for padding
+THE_PADDING_NEEDED_PROC: process( CLK )
+begin
+ if rising_edge(CLK) then
+ if ( (RESET = '1') or (rst_regs = '1') ) then
+ padding_needed <= '0';
+ elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then
+ padding_needed <= '1';
+ elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then
+ padding_needed <= '0';
+ end if;
+ end if;
+end process THE_PADDING_NEEDED_PROC;
+
+-- number of bytes to read from split fifo
+THE_READ_SIZE_PROC: process( CLK )
+begin
+ if( rising_edge(CLK) ) then
+ if ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then
+ read_size <= (others => '0');
+ elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
+ read_size(9 downto 2) <= pc_data;
+ elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
+ read_size(17 downto 10) <= pc_data;
+ elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then
+ read_size <= read_size - 1;
+ -- gk 25.07.10
+ elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then
+ read_size <= read_size - 1;
+ end if;
+ end if;
+end process THE_READ_SIZE_PROC;
+
+read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2"
+
+--******
+-- EVENTS COUNTERS
+--******
+
+-- gk 25.07.10
+LOADED_EVT_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ loaded_events_ctr <= (others => '0');
+ elsif (remove_done = '1') then
+ loaded_events_ctr <= loaded_events_ctr + x"1";
+ end if;
+ end if;
+end process LOADED_EVT_CTR_PROC;
+
+---- gk 25.07.10
+--CONSTR_EVENTS_CTR_PROC : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- constr_events_ctr <= (others => '0');
+-- elsif (pc_eod = '1') then
+-- constr_events_ctr <= constr_events_ctr + x"1";
+-- end if;
+-- end if;
+--end process CONSTR_EVENTS_CTR_PROC;
+
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+
+-- Debug signals
+--debug(0) <= sf_full;
+--debug(1) <= sf_empty;
+--debug(2) <= sf_afull;
+--debug(3) <= sf_aempty;
+--
+--debug(7 downto 4) <= state2;
+--
+--debug(11 downto 8) <= state;
+--
+--dbg_bs_proc : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- debug(15 downto 12) <= (others => '0');
+-- elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then
+-- debug(15 downto 12) <= bank_select;
+-- end if;
+-- end if;
+--end process dbg_bs_proc;
+--
+--debug(16) <= config_done;
+--debug(17) <= '0'; --remove_done;
+--debug(18) <= read_done;
+--debug(19) <= padding_needed;
+--
+--debug(20) <= load_sub_done;
+--
+--dbg_cts_inf_proc : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- debug(39 downto 32) <= (others => '0');
+-- elsif ( save_addr = '1' ) then
+-- debug(39 downto 32) <= CTS_INFORMATION_IN;
+-- end if;
+-- end if;
+--end process dbg_cts_inf_proc;
+--
+--debug(47 downto 40) <= (others => '0');
+--
+--
+--debug(63 downto 48) <= actual_message_size(15 downto 0);
+--
+--dbg_pc_sub_size_proc : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- debug(81 downto 64) <= (others => '0');
+-- elsif (loadCurrentState = DECIDE) then
+-- debug(81 downto 64) <= pc_sub_size;
+-- end if;
+-- end if;
+--end process dbg_pc_sub_size_proc;
+--
+--dbg_empty_proc : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') or (rst_regs = '1') then
+-- debug(84 downto 82) <= (others => '0');
+-- elsif (read_size = 2) then
+-- debug(82) <= sf_empty;
+-- elsif (read_size = 1) then
+-- debug(83) <= sf_empty;
+-- elsif (read_size = 0) then
+-- debug(84) <= sf_empty;
+-- end if;
+-- end if;
+--end process dbg_empty_proc;
+--
+--debug(95 downto 85) <= (others => '0');
+--
+--dbg_inc_ctr_proc : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- debug(127 downto 96) <= (others => '1');
+-- elsif (saveCurrentState = SCLOSE) then
+-- debug(127 downto 96) <= inc_data_ctr;
+-- end if;
+-- end if;
+--end process dbg_inc_ctr_proc;
+--
+--debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0);
+--debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0);
+--
+--debug(175 downto 160) <= headers_invalid_ctr(15 downto 0);
+--debug(191 downto 176) <= (others => '0');
+--
+--dbg_cts_q_proc : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- cts_len_q <= (others => '0');
+-- cts_rnd_q <= (others => '0');
+-- cts_trg_q <= (others => '0');
+-- cts_addr_q <= (others => '0');
+-- elsif (cts_len_saved = '1') then
+-- cts_len_q <= cts_len(16 downto 1);
+-- cts_addr_q <= cts_addr;
+-- cts_rnd_q <= cts_rnd;
+-- cts_trg_q <= cts_trg;
+-- end if;
+-- end if;
+--end process dbg_cts_q_proc;
+--
+--debug(207 downto 192) <= cts_trg_q;
+--debug(223 downto 208) <= cts_rnd_q;
+--debug(239 downto 224) <= cts_addr_q;
+--debug(255 downto 240) <= cts_len_q;
+--debug(271 downto 256) <= first_run_trg;
+--debug(287 downto 272) <= first_run_addr;
+--
+--debug(303 downto 288) <= saved_events_ctr;
+--debug(319 downto 304) <= loaded_events_ctr;
+--
+--debug(335 downto 320) <= constr_events_ctr(15 downto 0);
+--debug(351 downto 336) <= dropped_ctr(15 downto 0);
+--
+--debug(367 downto 352) <= invalid_hsize_ctr;
+--debug(383 downto 368) <= (others => '0');
+--
+--MONITOR_OUT(31 downto 0) <= constr_events_ctr;
+--MONITOR_OUT(63 downto 32) <= dropped_ctr;
+--MONITOR_OUT(95 downto 64) <= headers_invalid_ctr;
+--MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr;
+--MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr;
+--MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000";
+--MONITOR_OUT(191 downto 164) <= (others => '0');
+--MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10
+
+-- Outputs
+FEE_READ_OUT <= fee_read;
+CTS_ERROR_PATTERN_OUT <= cts_error_pattern;
+CTS_DATA_OUT <= cts_data;
+CTS_DATAREADY_OUT <= cts_dataready;
+CTS_READOUT_FINISHED_OUT <= cts_readout_finished;
+CTS_LENGTH_OUT <= cts_length;
+
+--PC_SOS_OUT <= pc_sos;
+--PC_EOD_OUT <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (pc_eod = '1'))
+-- or ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1'))
+-- -- gk 07.12.10
+-- or ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1'))
+-- else '0'; -- gk 07.10.10
+--PC_DATA_OUT <= pc_data_q;
+--PC_WR_EN_OUT <= pc_wr_en_qq;
+
+PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random;
+
+--PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size;
+--PC_PADDING_OUT <= padding_needed;
+-- gk 07.10.10
+--PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0';
+
+DEBUG_OUT <= debug;
+
+-- SIMPLE SENDER STUFF
+
+
+
+PC_SOS_OUT <= '0'; --'1' when gen_current_state = WAIT_FOR_PC and PC_READY_IN = '1' else '0';
+PC_EOS_OUT <= '0';
+PC_EOD_OUT <= '0'; --'1' when gen_current_state = GENERATE_DATA and gen_data_ctr = SCTRL_DUMMY_SIZE_IN else '0';
+PC_DATA_OUT <= gen_data_ctr(7 downto 0);
+PC_WR_EN_OUT <= '0'; --'1' when gen_current_state = GENERATE_DATA else '0';
+PC_SUB_SIZE_OUT <= x"0000" & SCTRL_DUMMY_SIZE_IN + x"1";
+PC_PADDING_OUT <= '0';
+
+GEN_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ gen_current_state <= IDLE;
+ else
+ gen_current_state <= gen_next_state;
+ end if;
+ end if;
+end process GEN_MACHINE_PROC;
+
+GEN_MACHINE : process(gen_current_state, gen_data_ctr, event_waiting, DATA_GBE_ENABLE_IN, SCTRL_DUMMY_SIZE_IN, PC_READY_IN)
+begin
+ case (gen_current_state) is
+
+ when IDLE =>
+ if (event_waiting = '1' and DATA_GBE_ENABLE_IN = '1') then
+ gen_next_state <= WAIT_FOR_PC;
+ else
+ gen_next_state <= IDLE;
+ end if;
+
+ when WAIT_FOR_PC =>
+ if (PC_READY_IN = '1') then
+ gen_next_state <= GENERATE_DATA;
+ else
+ gen_next_state <= WAIT_FOR_PC;
+ end if;
+
+ when GENERATE_DATA =>
+ if (gen_data_ctr = SCTRL_DUMMY_SIZE_IN) then
+ gen_next_state <= CLEANUP;
+ else
+ gen_next_state <= GENERATE_DATA;
+ end if;
+
+ when CLEANUP =>
+ gen_next_state <= IDLE;
+
+ end case;
+end process GEN_MACHINE;
+
+GEN_DATA_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (gen_current_state = IDLE) then
+ gen_data_ctr <= (others => '0');
+ elsif (gen_current_state = GENERATE_DATA) then
+ gen_data_ctr <= gen_data_ctr + x"1";
+ end if;
+ end if;
+end process GEN_DATA_CTR_PROC;
+
+end architecture;
\ No newline at end of file
Z : out std_logic);
end component;
-component rx_reset_sm
+component rx_reset_sm_1254
generic (count_index: integer :=18);
port (
rst_n : in std_logic;
);
end component ;
-component tx_reset_sm
+component tx_reset_sm_1254
generic (count_index: integer :=18);
port (
rst_n : in std_logic;
END IF;
END PROCESS;
-rx_reset_sm_ch0 : rx_reset_sm
+rx_reset_sm_ch0 : rx_reset_sm_1254
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch1 : rx_reset_sm
+rx_reset_sm_ch1 : rx_reset_sm_1254
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch2 : rx_reset_sm
+rx_reset_sm_ch2 : rx_reset_sm_1254
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch3 : rx_reset_sm
+rx_reset_sm_ch3 : rx_reset_sm_1254
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END PROCESS;
-- reset sequence for tx
-tx_reset_sm_ch : tx_reset_sm
+tx_reset_sm_ch : tx_reset_sm_1254
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_0" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 01 25 19:02:13.519" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_0" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 03 11 18:56:35.024" version="8.1" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="serdes_sync_0.lpc" type="lpc" modified="2013 01 25 19:02:03.000"/>
- <File name="serdes_sync_0.pp" type="pp" modified="2013 01 25 19:02:03.000"/>
- <File name="serdes_sync_0.sym" type="sym" modified="2013 01 25 19:02:03.000"/>
- <File name="serdes_sync_0.tft" type="tft" modified="2013 01 25 19:02:03.000"/>
- <File name="serdes_sync_0.txt" type="pcs_module" modified="2013 01 25 19:02:03.000"/>
- <File name="serdes_sync_0.vhd" type="top_level_vhdl" modified="2013 01 25 19:02:03.000"/>
+ <File name="serdes_sync_0.lpc" type="lpc" modified="2013 03 11 18:56:32.000"/>
+ <File name="serdes_sync_0.pp" type="pp" modified="2013 03 11 18:56:32.000"/>
+ <File name="serdes_sync_0.sym" type="sym" modified="2013 03 11 18:56:32.000"/>
+ <File name="serdes_sync_0.tft" type="tft" modified="2013 03 11 18:56:32.000"/>
+ <File name="serdes_sync_0.txt" type="pcs_module" modified="2013 03 11 18:56:32.000"/>
+ <File name="serdes_sync_0.vhd" type="top_level_vhdl" modified="2013 03 11 18:56:32.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_0
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=01/25/2013
-Time=19:02:03
+Date=03/11/2013
+Time=18:56:32
[Parameters]
Verilog=0
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_sync_125_0" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 03 11 19:01:27.978" version="8.1" type="Module" synthesis="" source_format="VHDL">
+ <Package>
+ <File name="serdes_sync_125_0.lpc" type="lpc" modified="2013 03 11 19:00:55.000"/>
+ <File name="serdes_sync_125_0.pp" type="pp" modified="2013 03 11 19:00:55.000"/>
+ <File name="serdes_sync_125_0.sym" type="sym" modified="2013 03 11 19:00:55.000"/>
+ <File name="serdes_sync_125_0.tft" type="tft" modified="2013 03 11 19:00:55.000"/>
+ <File name="serdes_sync_125_0.txt" type="pcs_module" modified="2013 03 11 19:00:55.000"/>
+ <File name="serdes_sync_125_0.vhd" type="top_level_vhdl" modified="2013 03 11 19:00:55.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN1156C
+SpeedGrade=6
+Package=FPBGA1156
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.1
+ModuleName=serdes_sync_125_0
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/11/2013
+Time=19:00:55
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=RXTX
+_mode1=DISABLED
+_mode2=DISABLED
+_mode3=DISABLED
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=2.5
+_pll_txsrc=INTERNAL
+_refclk_mult=20X
+_refclk_rate=125.0
+_tx_protocol0=G8B10B
+_tx_protocol1=DISABLED
+_tx_protocol2=DISABLED
+_tx_protocol3=DISABLED
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=FULL
+_tx_data_width0=8
+_tx_data_width1=8
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=DISABLED
+_tx_fifo1=ENABLED
+_tx_fifo2=ENABLED
+_tx_fifo3=ENABLED
+_tx_ficlk_rate0=250.0
+_tx_ficlk_rate1=250.0
+_tx_ficlk_rate2=250.0
+_tx_ficlk_rate3=250.0
+_pll_rxsrc0=INTERNAL
+_pll_rxsrc1=EXTERNAL
+_pll_rxsrc2=EXTERNAL
+_pll_rxsrc3=EXTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=2.5
+_rx_datarange1=2.5
+_rx_datarange2=2.5
+_rx_datarange3=2.5
+_rx_protocol0=G8B10B
+_rx_protocol1=DISABLED
+_rx_protocol2=DISABLED
+_rx_protocol3=DISABLED
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=125.0
+_rxrefclk_rate1=125.0
+_rxrefclk_rate2=125.0
+_rxrefclk_rate3=125.0
+_rx_data_width0=8
+_rx_data_width1=8
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=ENABLED
+_rx_ficlk_rate0=250.0
+_rx_ficlk_rate1=250.0
+_rx_ficlk_rate2=250.0
+_rx_ficlk_rate3=250.0
+_tdrv_ch0=0
+_tdrv_ch1=0
+_tdrv_ch2=0
+_tdrv_ch3=0
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=DC
+_rx_dcc1=AC
+_rx_dcc2=AC
+_rx_dcc3=AC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=0
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=K28P157
+_scomma1=K28P157
+_scomma2=K28P157
+_scomma3=K28P157
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111100
+_comma_m1=1111111100
+_comma_m2=1111111100
+_comma_m3=1111111100
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=1
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=01
+_k01=00
+_k02=00
+_k03=00
+_k10=00
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00011100
+_byten01=00000000
+_byten02=00000000
+_byten03=00000000
+_byten10=00000000
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=3
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=DISABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=DISABLED
+Regen=auto
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+serdes_sync_125_0.pp=pp
+serdes_sync_125_0.tft=tft
+serdes_sync_125_0.txt=pcs_module
+serdes_sync_125_0.sym=sym
--- /dev/null
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH0_PROTOCOL "G8B10B"
+CH0_MODE "RXTX"
+CH1_MODE "DISABLED"
+CH2_MODE "DISABLED"
+CH3_MODE "DISABLED"
+CH0_CDR_SRC "REFCLK_CORE"
+PLL_SRC "REFCLK_CORE"
+TX_DATARATE_RANGE "MEDHIGH"
+CH0_RX_DATARATE_RANGE "MEDHIGH"
+REFCK_MULT "20X"
+#REFCLK_RATE 125.0
+CH0_RX_DATA_RATE "FULL"
+CH0_TX_DATA_RATE "FULL"
+CH0_TX_DATA_WIDTH "8"
+CH0_RX_DATA_WIDTH "8"
+CH0_TX_FIFO "DISABLED"
+CH0_RX_FIFO "ENABLED"
+CH0_TDRV "0"
+#CH0_TX_FICLK_RATE 250.0
+#CH0_RXREFCLK_RATE "125.0"
+#CH0_RX_FICLK_RATE 250.0
+CH0_TX_PRE "DISABLED"
+CH0_RTERM_TX "50"
+CH0_RX_EQ "DISABLED"
+CH0_RTERM_RX "50"
+CH0_RX_DCC "DC"
+CH0_LOS_THRESHOLD_LO "2"
+PLL_TERM "50"
+PLL_DCC "AC"
+PLL_LOL_SET "0"
+CH0_TX_SB "DISABLED"
+CH0_RX_SB "DISABLED"
+CH0_TX_8B10B "ENABLED"
+CH0_RX_8B10B "ENABLED"
+CH0_COMMA_A "1100000101"
+CH0_COMMA_B "0011111010"
+CH0_COMMA_M "1111111100"
+CH0_RXWA "ENABLED"
+CH0_ILSM "ENABLED"
+CH0_CTC "DISABLED"
+CH0_CC_MATCH4 "0100011100"
+CH0_CC_MATCH_MODE "1"
+CH0_CC_MIN_IPG "3"
+CCHMARK "9"
+CCLMARK "7"
+CH0_SSLB "DISABLED"
+CH0_SPLBPORTS "DISABLED"
+CH0_PCSLBPORTS "DISABLED"
+INT_ALL "DISABLED"
+QD_REFCK2CORE "DISABLED"
+
+
--- /dev/null
+
+
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+-- CONFIG_FILE : String := "serdes_sync_125_0.txt";
+-- QUAD_MODE : String := "SINGLE";
+-- CH0_CDR_SRC : String := "REFCLK_CORE";
+-- CH1_CDR_SRC : String := "REFCLK_EXT";
+-- CH2_CDR_SRC : String := "REFCLK_EXT";
+-- CH3_CDR_SRC : String := "REFCLK_EXT";
+-- PLL_SRC : String := "REFCLK_CORE"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String;
+ CH1_CDR_SRC : String;
+ CH2_CDR_SRC : String;
+ CH3_CDR_SRC : String;
+ PLL_SRC : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE,
+ QUAD_MODE => QUAD_MODE,
+ CH0_CDR_SRC => CH0_CDR_SRC,
+ CH1_CDR_SRC => CH1_CDR_SRC,
+ CH2_CDR_SRC => CH2_CDR_SRC,
+ CH3_CDR_SRC => CH3_CDR_SRC,
+ PLL_SRC => PLL_SRC
+ )
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+ FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+ FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+ FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+ FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+ FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+ FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+ FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+ FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+ FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+ FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+ FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+ FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+ FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+ FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+ FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+ FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+ FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+ FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+ LDR_CORE2TX_0 => LDR_CORE2TX_0,
+ LDR_CORE2TX_1 => LDR_CORE2TX_1,
+ LDR_CORE2TX_2 => LDR_CORE2TX_2,
+ LDR_CORE2TX_3 => LDR_CORE2TX_3,
+ FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+ FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+ FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+ FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+ PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+ PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+ PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+ PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+ PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+ PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+ PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+ PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+ PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+ PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+ PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+ PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+ PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+ PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+ PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+ PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+ PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+ PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+ PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+ PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+ FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+ FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+ FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+ FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+ FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+ FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+ FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+ FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+ FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+ FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+ FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+ FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+ FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+ PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+ PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+ PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+ PCIE_RXVALID_0 => PCIE_RXVALID_0,
+ PCIE_RXVALID_1 => PCIE_RXVALID_1,
+ PCIE_RXVALID_2 => PCIE_RXVALID_2,
+ PCIE_RXVALID_3 => PCIE_RXVALID_3,
+ FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+ FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+ FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+ FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+ FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+ FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+ FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+ FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+ LDR_RX2CORE_0 => LDR_RX2CORE_0,
+ LDR_RX2CORE_1 => LDR_RX2CORE_1,
+ LDR_RX2CORE_2 => LDR_RX2CORE_2,
+ LDR_RX2CORE_3 => LDR_RX2CORE_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7,
+ REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+ REFCLK_TO_NQ => REFCLK_TO_NQ
+ );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity serdes_sync_125_0 is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_sync_125_0.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (7 downto 0);
+ tx_k_ch0 : in std_logic;
+ tx_force_disp_ch0 : in std_logic;
+ tx_disp_sel_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ rx_serdes_rst_ch0_c : in std_logic;
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pcs_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pcs_rst_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+-- CH2 --
+-- CH3 --
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_qd_c : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end serdes_sync_125_0;
+
+
+architecture serdes_sync_125_0_arch of serdes_sync_125_0 is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+ attribute QUAD_MODE: string;
+ attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+ attribute PLL_SRC: string;
+ attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH0_CDR_SRC: string;
+ attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "125.000";
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal tx_full_clk_ch0_sig : std_logic;
+
+signal refclk2fpga_sig : std_logic;
+signal tx_pll_lol_qd_sig : std_logic;
+signal rx_los_low_ch0_sig : std_logic;
+signal rx_los_low_ch1_sig : std_logic;
+signal rx_los_low_ch2_sig : std_logic;
+signal rx_los_low_ch3_sig : std_logic;
+signal rx_cdr_lol_ch0_sig : std_logic;
+signal rx_cdr_lol_ch1_sig : std_logic;
+signal rx_cdr_lol_ch2_sig : std_logic;
+signal rx_cdr_lol_ch3_sig : std_logic;
+
+
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+ rx_los_low_ch0_s <= rx_los_low_ch0_sig;
+ rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
+ tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+ tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE,
+ QUAD_MODE => "SINGLE",
+ CH0_CDR_SRC => "REFCLK_CORE",
+ PLL_SRC => "REFCLK_CORE"
+ )
+--synopsys translate_on
+port map (
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+ HDOUTP0 => hdoutp_ch0,
+ HDOUTN0 => hdoutn_ch0,
+ HDINP0 => hdinp_ch0,
+ HDINN0 => hdinn_ch0,
+ PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+ PCIE_RXPOLARITY_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_1 => fpsc_vlo,
+ PCIE_RXVALID_0 => open,
+ PCIE_PHYSTATUS_0 => open,
+ SCISELCH0 => sci_sel_ch0,
+ SCIENCH0 => fpsc_vhi,
+ FF_RXI_CLK_0 => rxiclk_ch0,
+ FF_TXI_CLK_0 => txiclk_ch0,
+ FF_EBRD_CLK_0 => fpsc_vlo,
+ FF_RX_F_CLK_0 => rx_full_clk_ch0,
+ FF_RX_H_CLK_0 => rx_half_clk_ch0,
+ FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
+ FF_TX_H_CLK_0 => tx_half_clk_ch0,
+ FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
+ FF_TX_D_0_0 => txdata_ch0(0),
+ FF_TX_D_0_1 => txdata_ch0(1),
+ FF_TX_D_0_2 => txdata_ch0(2),
+ FF_TX_D_0_3 => txdata_ch0(3),
+ FF_TX_D_0_4 => txdata_ch0(4),
+ FF_TX_D_0_5 => txdata_ch0(5),
+ FF_TX_D_0_6 => txdata_ch0(6),
+ FF_TX_D_0_7 => txdata_ch0(7),
+ FF_TX_D_0_8 => tx_k_ch0,
+ FF_TX_D_0_9 => tx_force_disp_ch0,
+ FF_TX_D_0_10 => tx_disp_sel_ch0,
+ FF_TX_D_0_11 => fpsc_vlo,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => rxdata_ch0(0),
+ FF_RX_D_0_1 => rxdata_ch0(1),
+ FF_RX_D_0_2 => rxdata_ch0(2),
+ FF_RX_D_0_3 => rxdata_ch0(3),
+ FF_RX_D_0_4 => rxdata_ch0(4),
+ FF_RX_D_0_5 => rxdata_ch0(5),
+ FF_RX_D_0_6 => rxdata_ch0(6),
+ FF_RX_D_0_7 => rxdata_ch0(7),
+ FF_RX_D_0_8 => rx_k_ch0,
+ FF_RX_D_0_9 => rx_disp_err_ch0,
+ FF_RX_D_0_10 => rx_cv_err_ch0,
+ FF_RX_D_0_11 => open,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+
+ FFC_RRST_0 => rx_serdes_rst_ch0_c,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
+ FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
+ FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
+ FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
+ FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
+ FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
+ FFS_RLOS_HI_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
+ FFS_CC_OVERRUN_0 => open,
+ FFS_CC_UNDERRUN_0 => open,
+ FFS_SKP_ADDED_0 => open,
+ FFS_SKP_DELETED_0 => open,
+ FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
+ FFS_RXFBFIFO_ERROR_0 => open,
+ FFS_TXFBFIFO_ERROR_0 => open,
+ LDR_CORE2TX_0 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+ LDR_RX2CORE_0 => open,
+ FFS_CDR_TRAIN_DONE_0 => open,
+ FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+ FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c,
+ FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+ FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
+
+----- CH1 -----
+ HDOUTP1 => open,
+ HDOUTN1 => open,
+ HDINP1 => fpsc_vlo,
+ HDINN1 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+ PCIE_RXPOLARITY_1 => fpsc_vlo,
+ PCIE_POWERDOWN_1_0 => fpsc_vlo,
+ PCIE_POWERDOWN_1_1 => fpsc_vlo,
+ PCIE_RXVALID_1 => open,
+ PCIE_PHYSTATUS_1 => open,
+ SCISELCH1 => fpsc_vlo,
+ SCIENCH1 => fpsc_vlo,
+ FF_RXI_CLK_1 => fpsc_vlo,
+ FF_TXI_CLK_1 => fpsc_vlo,
+ FF_EBRD_CLK_1 => fpsc_vlo,
+ FF_RX_F_CLK_1 => open,
+ FF_RX_H_CLK_1 => open,
+ FF_TX_F_CLK_1 => open,
+ FF_TX_H_CLK_1 => open,
+ FFC_CK_CORE_RX_1 => fpsc_vlo,
+ FF_TX_D_1_0 => fpsc_vlo,
+ FF_TX_D_1_1 => fpsc_vlo,
+ FF_TX_D_1_2 => fpsc_vlo,
+ FF_TX_D_1_3 => fpsc_vlo,
+ FF_TX_D_1_4 => fpsc_vlo,
+ FF_TX_D_1_5 => fpsc_vlo,
+ FF_TX_D_1_6 => fpsc_vlo,
+ FF_TX_D_1_7 => fpsc_vlo,
+ FF_TX_D_1_8 => fpsc_vlo,
+ FF_TX_D_1_9 => fpsc_vlo,
+ FF_TX_D_1_10 => fpsc_vlo,
+ FF_TX_D_1_11 => fpsc_vlo,
+ FF_TX_D_1_12 => fpsc_vlo,
+ FF_TX_D_1_13 => fpsc_vlo,
+ FF_TX_D_1_14 => fpsc_vlo,
+ FF_TX_D_1_15 => fpsc_vlo,
+ FF_TX_D_1_16 => fpsc_vlo,
+ FF_TX_D_1_17 => fpsc_vlo,
+ FF_TX_D_1_18 => fpsc_vlo,
+ FF_TX_D_1_19 => fpsc_vlo,
+ FF_TX_D_1_20 => fpsc_vlo,
+ FF_TX_D_1_21 => fpsc_vlo,
+ FF_TX_D_1_22 => fpsc_vlo,
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => open,
+ FF_RX_D_1_1 => open,
+ FF_RX_D_1_2 => open,
+ FF_RX_D_1_3 => open,
+ FF_RX_D_1_4 => open,
+ FF_RX_D_1_5 => open,
+ FF_RX_D_1_6 => open,
+ FF_RX_D_1_7 => open,
+ FF_RX_D_1_8 => open,
+ FF_RX_D_1_9 => open,
+ FF_RX_D_1_10 => open,
+ FF_RX_D_1_11 => open,
+ FF_RX_D_1_12 => open,
+ FF_RX_D_1_13 => open,
+ FF_RX_D_1_14 => open,
+ FF_RX_D_1_15 => open,
+ FF_RX_D_1_16 => open,
+ FF_RX_D_1_17 => open,
+ FF_RX_D_1_18 => open,
+ FF_RX_D_1_19 => open,
+ FF_RX_D_1_20 => open,
+ FF_RX_D_1_21 => open,
+ FF_RX_D_1_22 => open,
+ FF_RX_D_1_23 => open,
+
+ FFC_RRST_1 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => fpsc_vlo,
+ FFC_PFIFO_CLR_1 => fpsc_vlo,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => fpsc_vlo,
+ FFC_TXPWDNB_1 => fpsc_vlo,
+ FFC_LANE_RX_RST_1 => fpsc_vlo,
+ FFC_RXPWDNB_1 => fpsc_vlo,
+ FFS_RLOS_LO_1 => open,
+ FFS_RLOS_HI_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFS_LS_SYNC_STATUS_1 => open,
+ FFS_CC_OVERRUN_1 => open,
+ FFS_CC_UNDERRUN_1 => open,
+ FFS_SKP_ADDED_1 => open,
+ FFS_SKP_DELETED_1 => open,
+ FFS_RLOL_1 => open,
+ FFS_RXFBFIFO_ERROR_1 => open,
+ FFS_TXFBFIFO_ERROR_1 => open,
+ LDR_CORE2TX_1 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+ LDR_RX2CORE_1 => open,
+ FFS_CDR_TRAIN_DONE_1 => open,
+ FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+ FFC_RATE_MODE_TX_1 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+ FFC_RATE_MODE_RX_1 => fpsc_vlo,
+
+----- CH2 -----
+ HDOUTP2 => open,
+ HDOUTN2 => open,
+ HDINP2 => fpsc_vlo,
+ HDINN2 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+ PCIE_RXPOLARITY_2 => fpsc_vlo,
+ PCIE_POWERDOWN_2_0 => fpsc_vlo,
+ PCIE_POWERDOWN_2_1 => fpsc_vlo,
+ PCIE_RXVALID_2 => open,
+ PCIE_PHYSTATUS_2 => open,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => fpsc_vlo,
+ FF_TXI_CLK_2 => fpsc_vlo,
+ FF_EBRD_CLK_2 => fpsc_vlo,
+ FF_RX_F_CLK_2 => open,
+ FF_RX_H_CLK_2 => open,
+ FF_TX_F_CLK_2 => open,
+ FF_TX_H_CLK_2 => open,
+ FFC_CK_CORE_RX_2 => fpsc_vlo,
+ FF_TX_D_2_0 => fpsc_vlo,
+ FF_TX_D_2_1 => fpsc_vlo,
+ FF_TX_D_2_2 => fpsc_vlo,
+ FF_TX_D_2_3 => fpsc_vlo,
+ FF_TX_D_2_4 => fpsc_vlo,
+ FF_TX_D_2_5 => fpsc_vlo,
+ FF_TX_D_2_6 => fpsc_vlo,
+ FF_TX_D_2_7 => fpsc_vlo,
+ FF_TX_D_2_8 => fpsc_vlo,
+ FF_TX_D_2_9 => fpsc_vlo,
+ FF_TX_D_2_10 => fpsc_vlo,
+ FF_TX_D_2_11 => fpsc_vlo,
+ FF_TX_D_2_12 => fpsc_vlo,
+ FF_TX_D_2_13 => fpsc_vlo,
+ FF_TX_D_2_14 => fpsc_vlo,
+ FF_TX_D_2_15 => fpsc_vlo,
+ FF_TX_D_2_16 => fpsc_vlo,
+ FF_TX_D_2_17 => fpsc_vlo,
+ FF_TX_D_2_18 => fpsc_vlo,
+ FF_TX_D_2_19 => fpsc_vlo,
+ FF_TX_D_2_20 => fpsc_vlo,
+ FF_TX_D_2_21 => fpsc_vlo,
+ FF_TX_D_2_22 => fpsc_vlo,
+ FF_TX_D_2_23 => fpsc_vlo,
+ FF_RX_D_2_0 => open,
+ FF_RX_D_2_1 => open,
+ FF_RX_D_2_2 => open,
+ FF_RX_D_2_3 => open,
+ FF_RX_D_2_4 => open,
+ FF_RX_D_2_5 => open,
+ FF_RX_D_2_6 => open,
+ FF_RX_D_2_7 => open,
+ FF_RX_D_2_8 => open,
+ FF_RX_D_2_9 => open,
+ FF_RX_D_2_10 => open,
+ FF_RX_D_2_11 => open,
+ FF_RX_D_2_12 => open,
+ FF_RX_D_2_13 => open,
+ FF_RX_D_2_14 => open,
+ FF_RX_D_2_15 => open,
+ FF_RX_D_2_16 => open,
+ FF_RX_D_2_17 => open,
+ FF_RX_D_2_18 => open,
+ FF_RX_D_2_19 => open,
+ FF_RX_D_2_20 => open,
+ FF_RX_D_2_21 => open,
+ FF_RX_D_2_22 => open,
+ FF_RX_D_2_23 => open,
+
+ FFC_RRST_2 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+ FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => fpsc_vlo,
+ FFC_TXPWDNB_2 => fpsc_vlo,
+ FFC_LANE_RX_RST_2 => fpsc_vlo,
+ FFC_RXPWDNB_2 => fpsc_vlo,
+ FFS_RLOS_LO_2 => open,
+ FFS_RLOS_HI_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFS_PCIE_DONE_2 => open,
+ FFS_LS_SYNC_STATUS_2 => open,
+ FFS_CC_OVERRUN_2 => open,
+ FFS_CC_UNDERRUN_2 => open,
+ FFS_SKP_ADDED_2 => open,
+ FFS_SKP_DELETED_2 => open,
+ FFS_RLOL_2 => open,
+ FFS_RXFBFIFO_ERROR_2 => open,
+ FFS_TXFBFIFO_ERROR_2 => open,
+ LDR_CORE2TX_2 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+ LDR_RX2CORE_2 => open,
+ FFS_CDR_TRAIN_DONE_2 => open,
+ FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => fpsc_vlo,
+
+----- CH3 -----
+ HDOUTP3 => open,
+ HDOUTN3 => open,
+ HDINP3 => fpsc_vlo,
+ HDINN3 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+ PCIE_RXPOLARITY_3 => fpsc_vlo,
+ PCIE_POWERDOWN_3_0 => fpsc_vlo,
+ PCIE_POWERDOWN_3_1 => fpsc_vlo,
+ PCIE_RXVALID_3 => open,
+ PCIE_PHYSTATUS_3 => open,
+ SCISELCH3 => fpsc_vlo,
+ SCIENCH3 => fpsc_vlo,
+ FF_RXI_CLK_3 => fpsc_vlo,
+ FF_TXI_CLK_3 => fpsc_vlo,
+ FF_EBRD_CLK_3 => fpsc_vlo,
+ FF_RX_F_CLK_3 => open,
+ FF_RX_H_CLK_3 => open,
+ FF_TX_F_CLK_3 => open,
+ FF_TX_H_CLK_3 => open,
+ FFC_CK_CORE_RX_3 => fpsc_vlo,
+ FF_TX_D_3_0 => fpsc_vlo,
+ FF_TX_D_3_1 => fpsc_vlo,
+ FF_TX_D_3_2 => fpsc_vlo,
+ FF_TX_D_3_3 => fpsc_vlo,
+ FF_TX_D_3_4 => fpsc_vlo,
+ FF_TX_D_3_5 => fpsc_vlo,
+ FF_TX_D_3_6 => fpsc_vlo,
+ FF_TX_D_3_7 => fpsc_vlo,
+ FF_TX_D_3_8 => fpsc_vlo,
+ FF_TX_D_3_9 => fpsc_vlo,
+ FF_TX_D_3_10 => fpsc_vlo,
+ FF_TX_D_3_11 => fpsc_vlo,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => open,
+ FF_RX_D_3_1 => open,
+ FF_RX_D_3_2 => open,
+ FF_RX_D_3_3 => open,
+ FF_RX_D_3_4 => open,
+ FF_RX_D_3_5 => open,
+ FF_RX_D_3_6 => open,
+ FF_RX_D_3_7 => open,
+ FF_RX_D_3_8 => open,
+ FF_RX_D_3_9 => open,
+ FF_RX_D_3_10 => open,
+ FF_RX_D_3_11 => open,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+
+ FFC_RRST_3 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+ FFC_PFIFO_CLR_3 => fpsc_vlo,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => fpsc_vlo,
+ FFC_TXPWDNB_3 => fpsc_vlo,
+ FFC_LANE_RX_RST_3 => fpsc_vlo,
+ FFC_RXPWDNB_3 => fpsc_vlo,
+ FFS_RLOS_LO_3 => open,
+ FFS_RLOS_HI_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFS_PCIE_DONE_3 => open,
+ FFS_LS_SYNC_STATUS_3 => open,
+ FFS_CC_OVERRUN_3 => open,
+ FFS_CC_UNDERRUN_3 => open,
+ FFS_SKP_ADDED_3 => open,
+ FFS_SKP_DELETED_3 => open,
+ FFS_RLOL_3 => open,
+ FFS_RXFBFIFO_ERROR_3 => open,
+ FFS_TXFBFIFO_ERROR_3 => open,
+ LDR_CORE2TX_3 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+ LDR_RX2CORE_3 => open,
+ FFS_CDR_TRAIN_DONE_3 => open,
+ FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => fpsc_vlo,
+
+----- Auxilliary ----
+ SCIWDATA7 => sci_wrdata(7),
+ SCIWDATA6 => sci_wrdata(6),
+ SCIWDATA5 => sci_wrdata(5),
+ SCIWDATA4 => sci_wrdata(4),
+ SCIWDATA3 => sci_wrdata(3),
+ SCIWDATA2 => sci_wrdata(2),
+ SCIWDATA1 => sci_wrdata(1),
+ SCIWDATA0 => sci_wrdata(0),
+ SCIADDR5 => sci_addr(5),
+ SCIADDR4 => sci_addr(4),
+ SCIADDR3 => sci_addr(3),
+ SCIADDR2 => sci_addr(2),
+ SCIADDR1 => sci_addr(1),
+ SCIADDR0 => sci_addr(0),
+ SCIRDATA7 => sci_rddata(7),
+ SCIRDATA6 => sci_rddata(6),
+ SCIRDATA5 => sci_rddata(5),
+ SCIRDATA4 => sci_rddata(4),
+ SCIRDATA3 => sci_rddata(3),
+ SCIRDATA2 => sci_rddata(2),
+ SCIRDATA1 => sci_rddata(1),
+ SCIRDATA0 => sci_rddata(0),
+ SCIENAUX => fpsc_vhi,
+ SCISELAUX => sci_sel_quad,
+ SCIRD => sci_rd,
+ SCIWSTN => sci_wrn,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_CK_CORE_TX => fpga_txrefclk,
+ FFC_MACRO_RST => serdes_rst_qd_c,
+ FFC_QUAD_RST => rst_qd_c,
+ FFC_TRST => tx_serdes_rst_c,
+ FFS_PLOL => tx_pll_lol_qd_sig,
+ FFC_SYNC_TOGGLE => fpsc_vlo,
+ REFCK2CORE => refclk2fpga_sig,
+ CIN0 => fpsc_vlo,
+ CIN1 => fpsc_vlo,
+ CIN2 => fpsc_vlo,
+ CIN3 => fpsc_vlo,
+ CIN4 => fpsc_vlo,
+ CIN5 => fpsc_vlo,
+ CIN6 => fpsc_vlo,
+ CIN7 => fpsc_vlo,
+ CIN8 => fpsc_vlo,
+ CIN9 => fpsc_vlo,
+ CIN10 => fpsc_vlo,
+ CIN11 => fpsc_vlo,
+ COUT0 => open,
+ COUT1 => open,
+ COUT2 => open,
+ COUT3 => open,
+ COUT4 => open,
+ COUT5 => open,
+ COUT6 => open,
+ COUT7 => open,
+ COUT8 => open,
+ COUT9 => open,
+ COUT10 => open,
+ COUT11 => open,
+ COUT12 => open,
+ COUT13 => open,
+ COUT14 => open,
+ COUT15 => open,
+ COUT16 => open,
+ COUT17 => open,
+ COUT18 => open,
+ COUT19 => open,
+ REFCLK_FROM_NQ => refclk_from_nq,
+ REFCLK_TO_NQ => open);
+
+
+
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+end serdes_sync_125_0_arch ;
entity med_ecp3_sfp_sync is
generic(
SERDES_NUM : integer range 0 to 3 := 0;
- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO
+-- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO
IS_SYNC_SLAVE : integer := c_NO --select slave mode
);
port(
CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
--Sync operation
- IS_SLAVE : in std_logic := '0'; --0 if generic is used
RX_DLM : out std_logic := '0';
RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
TX_DLM : in std_logic := '0';
attribute syn_sharing : string;
attribute syn_sharing of med_ecp3_sfp_sync_arch : architecture is "off";
-component serdes_sync_0 is
- generic (
- USER_CONFIG_FILE : String := "serdes_sync_0.txt"
- );
- port (
- hdinp_ch0, hdinn_ch0 : in std_logic;
- hdoutp_ch0, hdoutn_ch0 : out std_logic;
- sci_sel_ch0 : in std_logic;
- rxiclk_ch0 : in std_logic;
- txiclk_ch0 : in std_logic;
- rx_full_clk_ch0 : out std_logic;
- rx_half_clk_ch0 : out std_logic;
- tx_full_clk_ch0 : out std_logic;
- tx_half_clk_ch0 : out std_logic;
- fpga_rxrefclk_ch0 : in std_logic;
- txdata_ch0 : in std_logic_vector (7 downto 0);
- tx_k_ch0 : in std_logic;
- tx_force_disp_ch0 : in std_logic;
- tx_disp_sel_ch0 : in std_logic;
- rxdata_ch0 : out std_logic_vector (7 downto 0);
- rx_k_ch0 : out std_logic;
- rx_disp_err_ch0 : out std_logic;
- rx_cv_err_ch0 : out std_logic;
- rx_serdes_rst_ch0_c : in std_logic;
- sb_felb_ch0_c : in std_logic;
- sb_felb_rst_ch0_c : in std_logic;
- tx_pcs_rst_ch0_c : in std_logic;
- tx_pwrup_ch0_c : in std_logic;
- rx_pcs_rst_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
- rx_los_low_ch0_s : out std_logic;
- lsm_status_ch0_s : out std_logic;
- rx_cdr_lol_ch0_s : out std_logic;
- tx_div2_mode_ch0_c : in std_logic;
- rx_div2_mode_ch0_c : in std_logic;
-
- sci_wrdata : in std_logic_vector (7 downto 0);
- sci_addr : in std_logic_vector (5 downto 0);
- sci_rddata : out std_logic_vector (7 downto 0);
- sci_sel_quad : in std_logic;
- sci_rd : in std_logic;
- sci_wrn : in std_logic;
-
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- rst_qd_c : in std_logic;
- serdes_rst_qd_c : in std_logic
- );
-end component;
-
component DCS
-- synthesis translate_off
rst_n <= not CLEAR;
---Temporary clock switch for debugging, should be not used!
-gen_clock_switch : if MASTER_CLOCK_SWITCH = 1 generate
- DCSInst0: DCS
- -- synthesis translate_off
- generic map (
- DCSMODE => “POS”
- );
- -- synthesis translate_on
- port map (
- SEL => IS_SLAVE,
- CLK0 => clk_200_internal,
- CLK1 => clk_rx_full,
- DCSOUT => clk_200_i
- );
-end generate;
-
-gen_slave_clock : if MASTER_CLOCK_SWITCH = 0 and IS_SYNC_SLAVE = c_YES generate
+gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
clk_200_i <= clk_rx_full;
end generate;
-gen_master_clock : if MASTER_CLOCK_SWITCH = 0 and IS_SYNC_SLAVE = c_NO generate
+gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
clk_200_i <= clk_200_internal;
end generate;
-------------------------------------------------
-- Serdes
-------------------------------------------------
-THE_SERDES : serdes_sync_0
+THE_SERDES : entity work.serdes_sync_0
port map(
hdinp_ch0 => SD_RXD_P_IN,
hdinn_ch0 => SD_RXD_N_IN,
STATE_OUT => tx_fsm_state
);
--- Master can't do bit-locking
-wa_position_rx <= wa_position when (IS_SLAVE = '1' or IS_SYNC_SLAVE = 1) else x"0000";
+-- Master does not do bit-locking
+wa_position_rx <= wa_position when (IS_SYNC_SLAVE = 1) else x"0000";
--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
PROC_ALLOW : process begin
wait until rising_edge(clk_200_i);
- if rx_fsm_state = x"6" and ((IS_SLAVE = '1' or IS_SYNC_SLAVE = 1) or start_timer(start_timer'left) = '1') then
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
rx_allow <= '1';
else
rx_allow <= '0';
end if;
- if rx_fsm_state = x"6" and ((IS_SLAVE = '1' or IS_SYNC_SLAVE = 1) or start_timer(start_timer'left) = '1') then
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
tx_allow <= '1';
else
tx_allow <= '0';
debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
debug_reg(35 downto 32) <= wa_position(3 downto 0);
-debug_reg(39 downto 36) <= x"0";
+debug_reg(36) <= debug_tx_control_i(6);
+debug_reg(39 downto 37) <= "000";
debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
STAT_DEBUG <= debug_reg;
-internal_make_link_reset_out <= make_link_reset_i when IS_SLAVE = '1' or IS_SYNC_SLAVE = 1 else '0';
+internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = 1 else '0';
STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
component med_ecp3_sfp_sync is
generic(
SERDES_NUM : integer range 0 to 3 := 0;
- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO
+-- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO
IS_SYNC_SLAVE : integer := c_NO --select slave mode
);
port(
CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
--Sync operation
- IS_SLAVE : in std_logic := '0'; --0 if generic is used
+-- IS_SLAVE : in std_logic := '0'; --0 if generic is used
RX_DLM : out std_logic := '0';
RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
TX_DLM : in std_logic := '0';
----------------------------------------------------------------------
GOT_LINK_READY <= got_link_ready_i;
-START_RETRANSMIT_OUT <= start_retr_i;
-START_POSITION_OUT <= start_retr_pos_i;
+START_RETRANSMIT_OUT <= start_retr_i when rising_edge(CLK_200);
+START_POSITION_OUT <= start_retr_pos_i when rising_edge(CLK_200);
-RX_DLM <= rx_dlm_i;
-RX_DLM_WORD <= rx_dlm_word_i;
+RX_DLM <= rx_dlm_i when rising_edge(CLK_200);
+RX_DLM_WORD <= rx_dlm_word_i when rising_edge(CLK_200);
REQUEST_RETRANSMIT_OUT <= '0'; --TODO: check incoming data
REQUEST_POSITION_OUT <= x"00"; --TODO: check incoming data
-SEND_LINK_RESET_OUT <= send_link_reset_i;
-MAKE_RESET_OUT <= make_reset_i;
+SEND_LINK_RESET_OUT <= send_link_reset_i when rising_edge(CLK_200);
+MAKE_RESET_OUT <= make_reset_i when rising_edge(CLK_200);
----------------------------------------------------------------------
signal ct_fifo_reset : std_logic;
signal last_ct_fifo_empty : std_logic;
signal last_ct_fifo_read : std_logic;
+ signal debug_sending_dlm : std_logic;
-- gk 05.10.10
signal save_sop : std_logic;
if rising_edge(CLK_200) then
-- ram_read <= '0';
TX_K_OUT <= '0';
-
+ debug_sending_dlm <= '0';
case current_state is
when SEND_IDLE_L =>
TX_DATA_OUT <= K_IDLE;
TX_DATA_OUT <= K_DLM;
TX_K_OUT <= '1';
current_state <= SEND_DLM_H;
+ debug_sending_dlm <= '1';
when SEND_DLM_H =>
TX_DATA_OUT <= SEND_DLM_WORD;
+ debug_sending_dlm <= '1';
when SEND_REQUEST_H =>
TX_DATA_OUT <= request_position_i;
DEBUG_OUT(3) <= tx_allow_qtx;
DEBUG_OUT(4) <= ram_empty;
DEBUG_OUT(5) <= ram_afull;
-
+ DEBUG_OUT(6) <= debug_sending_dlm when rising_edge(CLK_200);
+ DEBUG_OUT(31 downto 7) <= (others => '0');
process(CLK_100)
begin
clk_txref <= ff_rxfullclk;
end generate;
+
+gen_clocks_125_noctc : if USE_125_MHZ = c_YES and USE_CTC = c_NO and USE_SLAVE = c_NO generate
+ clk_sys <= SYSCLK;
+ clk_tx <= SYSCLK;
+ clk_rx <= ff_rxhalfclk;
+ clk_rxref <= CLK;
+ clk_txref <= CLK;
+end generate;
+
--------------------------------------------------------------------------
-- Internal Lane Resets
--------------------------------------------------------------------------
);
end generate;
-
+ gen_serdes_1_125 : if SERDES_NUM = 1 and EXT_CLOCK = c_NO and USE_125_MHZ = c_YES and USE_CTC = c_NO generate
+ THE_SERDES: entity work.sfp_1_125_int
+ port map(
+ HDINP_CH1 => sd_rxd_p_in,
+ HDINN_CH1 => sd_rxd_n_in,
+ HDOUTP_CH1 => sd_txd_p_out,
+ HDOUTN_CH1 => sd_txd_n_out,
+
+ RXICLK_CH1 => clk_rx,
+ TXICLK_CH1 => clk_tx,
+ FPGA_RXREFCLK_CH1 => clk_rxref,
+ FPGA_TXREFCLK => clk_txref,
+ RX_FULL_CLK_CH1 => ff_rxfullclk,
+ RX_HALF_CLK_CH1 => ff_rxhalfclk,
+ TX_FULL_CLK_CH1 => open,
+ TX_HALF_CLK_CH1 => ff_txhalfclk,
+
+ TXDATA_CH1 => tx_data,
+ TX_K_CH1 => tx_k,
+ TX_FORCE_DISP_CH1 => tx_correct,
+ TX_DISP_SEL_CH1 => "00",
+
+ SB_FELB_CH1_C => '0', --loopback enable
+ SB_FELB_RST_CH1_C => '0', --loopback reset
+
+ TX_PWRUP_CH1_C => '1', --tx power up
+ RX_PWRUP_CH1_C => '1', --rx power up
+ TX_DIV2_MODE_CH1_C => '0', --full rate
+ RX_DIV2_MODE_CH1_C => '0', --full rate
+
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_SEL_QUAD => sci_addr_i(8),
+ SCI_SEL_CH1 => sci_ch_i(1),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
+
+
+ TX_SERDES_RST_C => CLEAR,
+ RST_N => '1',
+ SERDES_RST_QD_C => ffc_quad_rst,
+
+ RXDATA_CH1 => comb_rx_data,
+ RX_K_CH1 => comb_rx_k,
+ RX_DISP_ERR_CH1 => open,
+ RX_CV_ERR_CH1 => link_error(7 downto 6),
+
+ RX_LOS_LOW_CH1_S => link_error(8),
+ LSM_STATUS_CH1_S => link_ok(0),
+ RX_CDR_LOL_CH1_S => link_error(4),
+ TX_PLL_LOL_QD_S => link_error(5)
+ );
+ end generate;
-------------------------------------------------------------------------
-- RX Fifo & Data output
-------------------------------------------------------------------------
end entity;
architecture arch_ecp3_sfp_4 of trb_net16_med_ecp3_sfp_4 is
-
- component serdes_full_ctc
- port(
- hdinp_ch0 : in std_logic;
- hdinn_ch0 : in std_logic;
- hdinp_ch1 : in std_logic;
- hdinn_ch1 : in std_logic;
- hdinp_ch2 : in std_logic;
- hdinn_ch2 : in std_logic;
- hdinp_ch3 : in std_logic;
- hdinn_ch3 : in std_logic;
- hdoutp_ch0 : out std_logic;
- hdoutn_ch0 : out std_logic;
- hdoutp_ch1 : out std_logic;
- hdoutn_ch1 : out std_logic;
- hdoutp_ch2 : out std_logic;
- hdoutn_ch2 : out std_logic;
- hdoutp_ch3 : out std_logic;
- hdoutn_ch3 : out std_logic;
-
- rxiclk_ch0 : in std_logic;
- txiclk_ch0 : in std_logic;
- rxiclk_ch1 : in std_logic;
- txiclk_ch1 : in std_logic;
- rxiclk_ch2 : in std_logic;
- txiclk_ch2 : in std_logic;
- rxiclk_ch3 : in std_logic;
- txiclk_ch3 : in std_logic;
- fpga_rxrefclk_ch0 : in std_logic;
- fpga_rxrefclk_ch1 : in std_logic;
- fpga_rxrefclk_ch2 : in std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- rx_full_clk_ch0 : out std_logic;
- rx_half_clk_ch0 : out std_logic;
- tx_full_clk_ch0 : out std_logic;
- tx_half_clk_ch0 : out std_logic;
- rx_full_clk_ch1 : out std_logic;
- rx_half_clk_ch1 : out std_logic;
- tx_full_clk_ch1 : out std_logic;
- tx_half_clk_ch1 : out std_logic;
- rx_full_clk_ch2 : out std_logic;
- rx_half_clk_ch2 : out std_logic;
- tx_full_clk_ch2 : out std_logic;
- tx_half_clk_ch2 : out std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- tx_full_clk_ch3 : out std_logic;
- tx_half_clk_ch3 : out std_logic;
-
- txdata_ch0 : in std_logic_vector(15 downto 0);
- txdata_ch1 : in std_logic_vector(15 downto 0);
- txdata_ch2 : in std_logic_vector(15 downto 0);
- txdata_ch3 : in std_logic_vector(15 downto 0);
- tx_k_ch0 : in std_logic_vector(1 downto 0);
- tx_k_ch1 : in std_logic_vector(1 downto 0);
- tx_k_ch2 : in std_logic_vector(1 downto 0);
- tx_k_ch3 : in std_logic_vector(1 downto 0);
- tx_force_disp_ch0 : in std_logic_vector(1 downto 0);
- tx_force_disp_ch1 : in std_logic_vector(1 downto 0);
- tx_force_disp_ch2 : in std_logic_vector(1 downto 0);
- tx_force_disp_ch3 : in std_logic_vector(1 downto 0);
- tx_disp_sel_ch0 : in std_logic_vector(1 downto 0);
- tx_disp_sel_ch1 : in std_logic_vector(1 downto 0);
- tx_disp_sel_ch2 : in std_logic_vector(1 downto 0);
- tx_disp_sel_ch3 : in std_logic_vector(1 downto 0);
-
- sb_felb_ch0_c : in std_logic;
- sb_felb_ch1_c : in std_logic;
- sb_felb_ch2_c : in std_logic;
- sb_felb_ch3_c : in std_logic;
- sb_felb_rst_ch0_c : in std_logic;
- sb_felb_rst_ch1_c : in std_logic;
- sb_felb_rst_ch2_c : in std_logic;
- sb_felb_rst_ch3_c : in std_logic;
-
- tx_pwrup_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
- tx_pwrup_ch1_c : in std_logic;
- rx_pwrup_ch1_c : in std_logic;
- tx_pwrup_ch2_c : in std_logic;
- rx_pwrup_ch2_c : in std_logic;
- tx_pwrup_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- tx_div2_mode_ch0_c : in std_logic;
- rx_div2_mode_ch0_c : in std_logic;
- tx_div2_mode_ch1_c : in std_logic;
- rx_div2_mode_ch1_c : in std_logic;
- tx_div2_mode_ch2_c : in std_logic;
- rx_div2_mode_ch2_c : in std_logic;
- tx_div2_mode_ch3_c : in std_logic;
- rx_div2_mode_ch3_c : in std_logic;
-
- rxdata_ch0 : out std_logic_vector(15 downto 0);
- rxdata_ch1 : out std_logic_vector(15 downto 0);
- rxdata_ch2 : out std_logic_vector(15 downto 0);
- rxdata_ch3 : out std_logic_vector(15 downto 0);
- rx_k_ch0 : out std_logic_vector(1 downto 0);
- rx_k_ch1 : out std_logic_vector(1 downto 0);
- rx_k_ch2 : out std_logic_vector(1 downto 0);
- rx_k_ch3 : out std_logic_vector(1 downto 0);
- rx_disp_err_ch0 : out std_logic_vector(1 downto 0);
- rx_disp_err_ch1 : out std_logic_vector(1 downto 0);
- rx_disp_err_ch2 : out std_logic_vector(1 downto 0);
- rx_disp_err_ch3 : out std_logic_vector(1 downto 0);
- rx_cv_err_ch0 : out std_logic_vector(1 downto 0);
- rx_cv_err_ch1 : out std_logic_vector(1 downto 0);
- rx_cv_err_ch2 : out std_logic_vector(1 downto 0);
- rx_cv_err_ch3 : out std_logic_vector(1 downto 0);
-
- rx_los_low_ch0_s : out std_logic;
- rx_los_low_ch1_s : out std_logic;
- rx_los_low_ch2_s : out std_logic;
- rx_los_low_ch3_s : out std_logic;
- lsm_status_ch0_s : out std_logic;
- lsm_status_ch1_s : out std_logic;
- lsm_status_ch2_s : out std_logic;
- lsm_status_ch3_s : out std_logic;
- rx_cdr_lol_ch0_s : out std_logic;
- rx_cdr_lol_ch1_s : out std_logic;
- rx_cdr_lol_ch2_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
-
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_sync_qd_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- rst_n : in std_logic;
- serdes_rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
-
- sci_sel_ch0 : in std_logic;
- sci_sel_ch1 : in std_logic;
- sci_sel_ch2 : in std_logic;
- sci_sel_ch3 : in std_logic;
- sci_wrdata : in std_logic_vector(7 downto 0);
- sci_addr : in std_logic_vector(5 downto 0);
- sci_sel_quad : in std_logic;
- sci_rd : in std_logic;
- sci_wrn : in std_logic;
- sci_rddata : out std_logic_vector(7 downto 0)
-
- );
- end component;
-- Placer Directives
--------------------------------------------------------------------------
-- Select proper clock configuration
--------------------------------------------------------------------------
-gen_clocks_200 : if FREQUENCY = 200 generate
+-- gen_clocks_200 : if FREQUENCY = 200 generate
clk_sys <= SYSCLK;
clk_tx <= SYSCLK;
clk_rx <= SYSCLK;
clk_ref <= CLK;
-end generate;
+-- end generate;
-- gen_clocks_125 : if FREQUENCY = 125 generate
-- clk_sys <= SYSCLK;
-- Instantiation of serdes module
gen_serdes_200 : if FREQUENCY = 200 generate
- THE_SERDES: serdes_full_ctc
+ THE_SERDES: entity work.serdes_full_ctc
port map(
HDINP_CH0 => sd_rxd_p_in(0),
HDINN_CH0 => sd_rxd_n_in(0),
);
end generate;
--- gen_serdes_125 : if FREQUENCY = 125 generate
--- THE_SERDES: serdes_onboard_full_125
--- port map(
--- HDINP_CH0 => sd_rxd_p_in(0),
--- HDINN_CH0 => sd_rxd_n_in(0),
--- HDINP_CH1 => sd_rxd_p_in(1),
--- HDINN_CH1 => sd_rxd_n_in(1),
--- HDINP_CH2 => sd_rxd_p_in(2),
--- HDINN_CH2 => sd_rxd_n_in(2),
--- HDINP_CH3 => sd_rxd_p_in(3),
--- HDINN_CH3 => sd_rxd_n_in(3),
--- HDOUTP_CH0 => sd_txd_p_out(0),
--- HDOUTN_CH0 => sd_txd_n_out(0),
--- HDOUTP_CH1 => sd_txd_p_out(1),
--- HDOUTN_CH1 => sd_txd_n_out(1),
--- HDOUTP_CH2 => sd_txd_p_out(2),
--- HDOUTN_CH2 => sd_txd_n_out(2),
--- HDOUTP_CH3 => sd_txd_p_out(3),
--- HDOUTN_CH3 => sd_txd_n_out(3),
---
--- RXICLK_CH0 => clk_rx,
--- TXICLK_CH0 => clk_tx,
--- RXICLK_CH1 => clk_rx,
--- TXICLK_CH1 => clk_tx,
--- RXICLK_CH2 => clk_rx,
--- TXICLK_CH2 => clk_tx,
--- RXICLK_CH3 => clk_rx,
--- TXICLK_CH3 => clk_tx,
--- FPGA_RXREFCLK_CH0 => clk_ref,
--- FPGA_RXREFCLK_CH1 => clk_ref,
--- FPGA_RXREFCLK_CH2 => clk_ref,
--- FPGA_RXREFCLK_CH3 => clk_ref,
--- FPGA_TXREFCLK => clk_ref,
--- RX_FULL_CLK_CH0 => open,
--- RX_HALF_CLK_CH0 => open,
--- TX_FULL_CLK_CH0 => open,
--- TX_HALF_CLK_CH0 => open,
--- RX_FULL_CLK_CH1 => open,
--- RX_HALF_CLK_CH1 => open,
--- TX_FULL_CLK_CH1 => open,
--- TX_HALF_CLK_CH1 => open,
--- RX_FULL_CLK_CH2 => open,
--- RX_HALF_CLK_CH2 => open,
--- TX_FULL_CLK_CH2 => open,
--- TX_HALF_CLK_CH2 => open,
--- RX_FULL_CLK_CH3 => open,
--- RX_HALF_CLK_CH3 => open,
--- TX_FULL_CLK_CH3 => open,
--- TX_HALF_CLK_CH3 => open,
---
--- TXDATA_CH0 => tx_data(15 downto 0),
--- TXDATA_CH1 => tx_data(31 downto 16),
--- TXDATA_CH2 => tx_data(47 downto 32),
--- TXDATA_CH3 => tx_data(63 downto 48),
--- TX_K_CH0 => tx_k(1 downto 0),
--- TX_K_CH1 => tx_k(3 downto 2),
--- TX_K_CH2 => tx_k(5 downto 4),
--- TX_K_CH3 => tx_k(7 downto 6),
--- TX_FORCE_DISP_CH0 => tx_correct(1 downto 0),
--- TX_FORCE_DISP_CH1 => tx_correct(3 downto 2),
--- TX_FORCE_DISP_CH2 => tx_correct(5 downto 4),
--- TX_FORCE_DISP_CH3 => tx_correct(7 downto 6),
--- TX_DISP_SEL_CH0 => "00",
--- TX_DISP_SEL_CH1 => "00",
--- TX_DISP_SEL_CH2 => "00",
--- TX_DISP_SEL_CH3 => "00",
---
--- SB_FELB_CH0_C => '0', --loopback enable
--- SB_FELB_CH1_C => '0', --loopback enable
--- SB_FELB_CH2_C => '0', --loopback enable
--- SB_FELB_CH3_C => '0', --loopback enable
--- SB_FELB_RST_CH0_C => '0', --loopback reset
--- SB_FELB_RST_CH1_C => '0', --loopback reset
--- SB_FELB_RST_CH2_C => '0', --loopback reset
--- SB_FELB_RST_CH3_C => '0', --loopback reset
---
--- TX_PWRUP_CH0_C => '1', --tx power up
--- RX_PWRUP_CH0_C => '1', --rx power up
--- TX_PWRUP_CH1_C => '1', --tx power up
--- RX_PWRUP_CH1_C => '1', --rx power up
--- TX_PWRUP_CH2_C => '1', --tx power up
--- RX_PWRUP_CH2_C => '1', --rx power up
--- TX_PWRUP_CH3_C => '1', --tx power up
--- RX_PWRUP_CH3_C => '1', --rx power up
--- TX_DIV2_MODE_CH0_C => '0', --full rate
--- RX_DIV2_MODE_CH0_C => '0', --full rate
--- TX_DIV2_MODE_CH1_C => '0', --full rate
--- RX_DIV2_MODE_CH1_C => '0', --full rate
--- TX_DIV2_MODE_CH2_C => '0', --full rate
--- RX_DIV2_MODE_CH2_C => '0', --full rate
--- TX_DIV2_MODE_CH3_C => '0', --full rate
--- RX_DIV2_MODE_CH3_C => '0', --full rate
---
--- SCI_WRDATA => (others => '0'),
--- SCI_RDDATA => open,
--- SCI_ADDR => (others => '0'),
--- SCI_SEL_QUAD => '0',
--- SCI_SEL_CH0 => '0',
--- SCI_SEL_CH1 => '0',
--- SCI_SEL_CH2 => '0',
--- SCI_SEL_CH3 => '0',
--- SCI_RD => '0',
--- SCI_WRN => '0',
---
--- TX_SERDES_RST_C => CLEAR,
--- TX_SYNC_QD_C => '0',
--- RST_N => '1',
--- SERDES_RST_QD_C => ffc_quad_rst,
---
--- RXDATA_CH0 => comb_rx_data(15 downto 0),
--- RXDATA_CH1 => comb_rx_data(31 downto 16),
--- RXDATA_CH2 => comb_rx_data(47 downto 32),
--- RXDATA_CH3 => comb_rx_data(63 downto 48),
--- RX_K_CH0 => comb_rx_k(1 downto 0),
--- RX_K_CH1 => comb_rx_k(3 downto 2),
--- RX_K_CH2 => comb_rx_k(5 downto 4),
--- RX_K_CH3 => comb_rx_k(7 downto 6),
---
--- RX_DISP_ERR_CH0 => open,
--- RX_DISP_ERR_CH1 => open,
--- RX_DISP_ERR_CH2 => open,
--- RX_DISP_ERR_CH3 => open,
--- RX_CV_ERR_CH0 => link_error(0*9+7 downto 0*9+6),
--- RX_CV_ERR_CH1 => link_error(1*9+7 downto 1*9+6),
--- RX_CV_ERR_CH2 => link_error(2*9+7 downto 2*9+6),
--- RX_CV_ERR_CH3 => link_error(3*9+7 downto 3*9+6),
---
--- RX_LOS_LOW_CH0_S => link_error(0*9+8),
--- RX_LOS_LOW_CH1_S => link_error(1*9+8),
--- RX_LOS_LOW_CH2_S => link_error(2*9+8),
--- RX_LOS_LOW_CH3_S => link_error(3*9+8),
--- LSM_STATUS_CH0_S => link_ok(0),
--- LSM_STATUS_CH1_S => link_ok(1),
--- LSM_STATUS_CH2_S => link_ok(2),
--- LSM_STATUS_CH3_S => link_ok(3),
--- RX_CDR_LOL_CH0_S => link_error(0*9+4),
--- RX_CDR_LOL_CH1_S => link_error(1*9+4),
--- RX_CDR_LOL_CH2_S => link_error(2*9+4),
--- RX_CDR_LOL_CH3_S => link_error(3*9+4),
--- TX_PLL_LOL_QD_S => link_error(5)
--- );
--- end generate;
+gen_serdes_125 : if FREQUENCY = 125 generate
+ THE_SERDES: entity work.serdes_onboard_full_125
+ port map(
+ HDINP_CH0 => sd_rxd_p_in(0),
+ HDINN_CH0 => sd_rxd_n_in(0),
+ HDINP_CH1 => sd_rxd_p_in(1),
+ HDINN_CH1 => sd_rxd_n_in(1),
+ HDINP_CH2 => sd_rxd_p_in(2),
+ HDINN_CH2 => sd_rxd_n_in(2),
+ HDINP_CH3 => sd_rxd_p_in(3),
+ HDINN_CH3 => sd_rxd_n_in(3),
+ HDOUTP_CH0 => sd_txd_p_out(0),
+ HDOUTN_CH0 => sd_txd_n_out(0),
+ HDOUTP_CH1 => sd_txd_p_out(1),
+ HDOUTN_CH1 => sd_txd_n_out(1),
+ HDOUTP_CH2 => sd_txd_p_out(2),
+ HDOUTN_CH2 => sd_txd_n_out(2),
+ HDOUTP_CH3 => sd_txd_p_out(3),
+ HDOUTN_CH3 => sd_txd_n_out(3),
+
+ RXICLK_CH0 => clk_rx,
+ TXICLK_CH0 => clk_tx,
+ RXICLK_CH1 => clk_rx,
+ TXICLK_CH1 => clk_tx,
+ RXICLK_CH2 => clk_rx,
+ TXICLK_CH2 => clk_tx,
+ RXICLK_CH3 => clk_rx,
+ TXICLK_CH3 => clk_tx,
+ FPGA_RXREFCLK_CH0 => clk_ref,
+ FPGA_RXREFCLK_CH1 => clk_ref,
+ FPGA_RXREFCLK_CH2 => clk_ref,
+ FPGA_RXREFCLK_CH3 => clk_ref,
+ FPGA_TXREFCLK => clk_ref,
+ RX_FULL_CLK_CH0 => open,
+ RX_HALF_CLK_CH0 => open,
+ TX_FULL_CLK_CH0 => open,
+ TX_HALF_CLK_CH0 => open,
+ RX_FULL_CLK_CH1 => open,
+ RX_HALF_CLK_CH1 => open,
+ TX_FULL_CLK_CH1 => open,
+ TX_HALF_CLK_CH1 => open,
+ RX_FULL_CLK_CH2 => open,
+ RX_HALF_CLK_CH2 => open,
+ TX_FULL_CLK_CH2 => open,
+ TX_HALF_CLK_CH2 => open,
+ RX_FULL_CLK_CH3 => open,
+ RX_HALF_CLK_CH3 => open,
+ TX_FULL_CLK_CH3 => open,
+ TX_HALF_CLK_CH3 => open,
+
+ TXDATA_CH0 => tx_data(15 downto 0),
+ TXDATA_CH1 => tx_data(31 downto 16),
+ TXDATA_CH2 => tx_data(47 downto 32),
+ TXDATA_CH3 => tx_data(63 downto 48),
+ TX_K_CH0 => tx_k(1 downto 0),
+ TX_K_CH1 => tx_k(3 downto 2),
+ TX_K_CH2 => tx_k(5 downto 4),
+ TX_K_CH3 => tx_k(7 downto 6),
+ TX_FORCE_DISP_CH0 => tx_correct(1 downto 0),
+ TX_FORCE_DISP_CH1 => tx_correct(3 downto 2),
+ TX_FORCE_DISP_CH2 => tx_correct(5 downto 4),
+ TX_FORCE_DISP_CH3 => tx_correct(7 downto 6),
+ TX_DISP_SEL_CH0 => "00",
+ TX_DISP_SEL_CH1 => "00",
+ TX_DISP_SEL_CH2 => "00",
+ TX_DISP_SEL_CH3 => "00",
+
+ SB_FELB_CH0_C => '0', --loopback enable
+ SB_FELB_CH1_C => '0', --loopback enable
+ SB_FELB_CH2_C => '0', --loopback enable
+ SB_FELB_CH3_C => '0', --loopback enable
+ SB_FELB_RST_CH0_C => '0', --loopback reset
+ SB_FELB_RST_CH1_C => '0', --loopback reset
+ SB_FELB_RST_CH2_C => '0', --loopback reset
+ SB_FELB_RST_CH3_C => '0', --loopback reset
+
+ TX_PWRUP_CH0_C => '1', --tx power up
+ RX_PWRUP_CH0_C => '1', --rx power up
+ TX_PWRUP_CH1_C => '1', --tx power up
+ RX_PWRUP_CH1_C => '1', --rx power up
+ TX_PWRUP_CH2_C => '1', --tx power up
+ RX_PWRUP_CH2_C => '1', --rx power up
+ TX_PWRUP_CH3_C => '1', --tx power up
+ RX_PWRUP_CH3_C => '1', --rx power up
+ TX_DIV2_MODE_CH0_C => '0', --full rate
+ RX_DIV2_MODE_CH0_C => '0', --full rate
+ TX_DIV2_MODE_CH1_C => '0', --full rate
+ RX_DIV2_MODE_CH1_C => '0', --full rate
+ TX_DIV2_MODE_CH2_C => '0', --full rate
+ RX_DIV2_MODE_CH2_C => '0', --full rate
+ TX_DIV2_MODE_CH3_C => '0', --full rate
+ RX_DIV2_MODE_CH3_C => '0', --full rate
+
+ SCI_WRDATA => (others => '0'),
+ SCI_RDDATA => open,
+ SCI_ADDR => (others => '0'),
+ SCI_SEL_QUAD => '0',
+ SCI_SEL_CH0 => '0',
+ SCI_SEL_CH1 => '0',
+ SCI_SEL_CH2 => '0',
+ SCI_SEL_CH3 => '0',
+ SCI_RD => '0',
+ SCI_WRN => '0',
+
+ TX_SERDES_RST_C => CLEAR,
+ TX_SYNC_QD_C => '0',
+ RST_N => '1',
+ SERDES_RST_QD_C => ffc_quad_rst,
+
+ RXDATA_CH0 => comb_rx_data(15 downto 0),
+ RXDATA_CH1 => comb_rx_data(31 downto 16),
+ RXDATA_CH2 => comb_rx_data(47 downto 32),
+ RXDATA_CH3 => comb_rx_data(63 downto 48),
+ RX_K_CH0 => comb_rx_k(1 downto 0),
+ RX_K_CH1 => comb_rx_k(3 downto 2),
+ RX_K_CH2 => comb_rx_k(5 downto 4),
+ RX_K_CH3 => comb_rx_k(7 downto 6),
+
+ RX_DISP_ERR_CH0 => open,
+ RX_DISP_ERR_CH1 => open,
+ RX_DISP_ERR_CH2 => open,
+ RX_DISP_ERR_CH3 => open,
+ RX_CV_ERR_CH0 => link_error(0*9+7 downto 0*9+6),
+ RX_CV_ERR_CH1 => link_error(1*9+7 downto 1*9+6),
+ RX_CV_ERR_CH2 => link_error(2*9+7 downto 2*9+6),
+ RX_CV_ERR_CH3 => link_error(3*9+7 downto 3*9+6),
+
+ RX_LOS_LOW_CH0_S => link_error(0*9+8),
+ RX_LOS_LOW_CH1_S => link_error(1*9+8),
+ RX_LOS_LOW_CH2_S => link_error(2*9+8),
+ RX_LOS_LOW_CH3_S => link_error(3*9+8),
+ LSM_STATUS_CH0_S => link_ok(0),
+ LSM_STATUS_CH1_S => link_ok(1),
+ LSM_STATUS_CH2_S => link_ok(2),
+ LSM_STATUS_CH3_S => link_ok(3),
+ RX_CDR_LOL_CH0_S => link_error(0*9+4),
+ RX_CDR_LOL_CH1_S => link_error(1*9+4),
+ RX_CDR_LOL_CH2_S => link_error(2*9+4),
+ RX_CDR_LOL_CH3_S => link_error(3*9+4),
+ TX_PLL_LOL_QD_S => link_error(5)
+ );
+end generate;
-------------------------------------------------------------------------
--- /dev/null
+
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+
+entity spi_flash_and_fpga_reload is
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ BUS_ADDR_IN : in std_logic_vector(8 downto 0);
+ BUS_READ_IN : in std_logic;
+ BUS_WRITE_IN : in std_logic;
+ BUS_DATAREADY_OUT : out std_logic;
+ BUS_WRITE_ACK_OUT : out std_logic;
+ BUS_UNKNOWN_ADDR_OUT : out std_logic;
+ BUS_NO_MORE_DATA_OUT : out std_logic;
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);
+
+ DO_REBOOT_IN : in std_logic;
+ PROGRAMN : out std_logic;
+
+ SPI_CS_OUT : out std_logic;
+ SPI_SCK_OUT : out std_logic;
+ SPI_SDO_OUT : out std_logic;
+ SPI_SDI_IN : in std_logic
+ );
+end entity;
+
+
+architecture flash_reboot_arch of spi_flash_and_fpga_reload is
+
+ signal spictrl_read_en : std_logic;
+ signal spictrl_write_en : std_logic;
+ signal spictrl_data_in : std_logic_vector(31 downto 0);
+ signal spictrl_addr : std_logic;
+ signal spictrl_data_out : std_logic_vector(31 downto 0);
+ signal spictrl_ack : std_logic;
+ signal spictrl_busy : std_logic;
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(5 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_ack : std_logic;
+
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+begin
+
+
+
+THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 2,
+ PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0)
+ )
+ port map(
+ CLK => CLK_IN,
+ RESET => RESET_IN,
+
+ DAT_ADDR_IN(8 downto 0) => BUS_ADDR_IN,
+ DAT_ADDR_IN(15 downto 9)=>(others => '0'),
+ DAT_DATA_IN => BUS_DATA_IN,
+ DAT_DATA_OUT => BUS_DATA_OUT,
+ DAT_READ_ENABLE_IN => BUS_READ_IN,
+ DAT_WRITE_ENABLE_IN => BUS_WRITE_IN,
+ DAT_TIMEOUT_IN => '0',
+ DAT_DATAREADY_OUT => BUS_DATAREADY_OUT,
+ DAT_WRITE_ACK_OUT => BUS_WRITE_ACK_OUT,
+ DAT_NO_MORE_DATA_OUT => BUS_NO_MORE_DATA_OUT,
+ DAT_UNKNOWN_ADDR_OUT => BUS_UNKNOWN_ADDR_OUT,
+
+ --Bus Handler (SPI CTRL)
+ BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_ADDR_OUT(0*16) => spictrl_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+
+ --Bus Handler (SPI Memory)
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
+ BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ STAT_DEBUG => open
+ );
+
+
+THE_SPI_MASTER: spi_master
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ -- Slave bus
+ BUS_READ_IN => spictrl_read_en,
+ BUS_WRITE_IN => spictrl_write_en,
+ BUS_BUSY_OUT => spictrl_busy,
+ BUS_ACK_OUT => spictrl_ack,
+ BUS_ADDR_IN(0) => spictrl_addr,
+ BUS_DATA_IN => spictrl_data_in,
+ BUS_DATA_OUT => spictrl_data_out,
+ -- SPI connections
+ SPI_CS_OUT => SPI_CS_OUT,
+ SPI_SDI_IN => SPI_SDI_IN,
+ SPI_SDO_OUT => SPI_SDO_OUT,
+ SPI_SCK_OUT => SPI_SCK_OUT,
+ -- BRAM for read/write data
+ BRAM_A_OUT => spi_bram_addr,
+ BRAM_WR_D_IN => spi_bram_wr_d,
+ BRAM_RD_D_OUT => spi_bram_rd_d,
+ BRAM_WE_OUT => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+-- data memory for SPI accesses
+THE_SPI_MEMORY: spi_databus_memory
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ -- Slave bus
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_ACK_OUT => spimem_ack,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+ -- state machine connections
+ BRAM_ADDR_IN => spi_bram_addr,
+ BRAM_WR_D_OUT => spi_bram_wr_d,
+ BRAM_RD_D_IN => spi_bram_rd_d,
+ BRAM_WE_IN => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+THE_FPGA_REBOOT : fpga_reboot
+ port map(
+ CLK => CLK_IN,
+ RESET => RESET_IN,
+ DO_REBOOT => DO_REBOOT_IN,
+ PROGRAMN => PROGRAMN
+ );
+
+
+end architecture;
\ No newline at end of file
--- /dev/null
+-- the full endpoint for HADES: trg, data, unused, regio
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+
+entity trb_net16_endpoint_sctrl is
+ generic (
+ USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
+ INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+ REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+ USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
+ --standard values for output registers
+ REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');
+ --set to 0 for unused ctrl registers to save resources
+ REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');
+ --set to 0 for each unused bit in a register
+ REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
+ REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
+ REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic := '1';
+
+ -- Media direction port
+ MED_DATAREADY_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic;
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic;
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
+
+ -- LVL1 trigger APL
+ TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received or real timing trigger signal
+
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid
+ LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received
+ LVL1_TRG_VALID_NOTIMING_OUT : out std_logic; --valid trigger without timing trigger has been received
+ LVL1_TRG_INVALID_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
+
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";
+ LVL1_TRG_RELEASE_IN : in std_logic := '0';
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT : out std_logic;
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;
+ TRG_SPURIOUS_TRG_OUT : out std_logic;
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;
+ TRG_SPIKE_DETECTED_OUT : out std_logic;
+ TRG_LONG_TRG_OUT : out std_logic;
+
+ --Data Port
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ --start strobe
+ IPU_START_READOUT_OUT : out std_logic;
+ --detector data, equipped with DHDR
+ IPU_DATA_IN : in std_logic_vector (31 downto 0);
+ IPU_DATAREADY_IN : in std_logic;
+ --no more data, end transfer, send TRM
+ IPU_READOUT_FINISHED_IN : in std_logic;
+ --will be low every second cycle due to 32bit -> 16bit conversion
+ IPU_READ_OUT : out std_logic;
+ IPU_LENGTH_IN : in std_logic_vector (15 downto 0);
+ IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+ REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);
+ STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+ CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ --following ports only used when using internal data port
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
+ REGIO_DATAREADY_IN : in std_logic := '0';
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';
+ REGIO_WRITE_ACK_IN : in std_logic := '0';
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
+ REGIO_TIMEOUT_OUT : out std_logic;
+ --IDRAM is used if no 1-wire interface, onewire used otherwise
+ REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
+ REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";
+ REGIO_IDRAM_WR_IN : in std_logic := '0';
+ REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor
+ REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0';
+ REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');
+
+ GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds
+ LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
+ TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick
+ --Debugging & Status information
+ STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);
+ STAT_DEBUG_1 : out std_logic_vector (31 downto 0);
+ STAT_DEBUG_2 : out std_logic_vector (31 downto 0);
+ MED_STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');
+ IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');
+ STAT_ONEWIRE : out std_logic_vector (31 downto 0);
+ STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);
+ STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0);
+ DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)
+ );
+end entity;
+
+
+
+
+
+architecture trb_net16_endpoint_sctrl_arch of trb_net16_endpoint_sctrl is
+
+
+ signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0);
+ signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+ signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+ signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0);
+
+ signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0);
+ signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+ signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+ signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0);
+
+ signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0);
+ signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+ signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+ signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0);
+
+ signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0);
+ signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+ signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+ signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0);
+
+ -- for the connection to the multiplexer
+ signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0);
+ signal MED_IO_DATA_IN : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+ signal MED_IO_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+ signal MED_IO_READ_OUT : std_logic_vector(3 downto 0);
+
+ signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0);
+ signal MED_IO_DATA_OUT : std_logic_vector (8*c_DATA_WIDTH-1 downto 0);
+ signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0);
+ signal MED_IO_READ_IN : std_logic_vector(7 downto 0);
+
+ signal buf_APL_DATA_IN : std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+ signal buf_APL_PACKET_NUM_IN : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+ signal buf_APL_DATAREADY_IN : std_logic_vector(3 downto 0);
+ signal buf_APL_READ_OUT : std_logic_vector(3 downto 0);
+ signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(3 downto 0);
+ signal buf_APL_DTYPE_IN : std_logic_vector(4*4-1 downto 0);
+ signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(4*32-1 downto 0);
+ signal buf_APL_SEND_IN : std_logic_vector(3 downto 0);
+ signal buf_APL_DATA_OUT : std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+ signal buf_APL_PACKET_NUM_OUT : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+ signal buf_APL_DATAREADY_OUT : std_logic_vector(3 downto 0);
+ signal buf_APL_READ_IN : std_logic_vector(3 downto 0);
+ signal buf_APL_TYP_OUT : std_logic_vector(4*3-1 downto 0);
+ signal buf_APL_RUN_OUT : std_logic_vector(3 downto 0);
+ signal buf_APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0);
+ signal buf_APL_LENGTH_IN : std_logic_vector(16*4-1 downto 0);
+
+ signal MY_ADDRESS : std_logic_vector(15 downto 0);
+
+ signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0);
+ signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0);
+ signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);
+ signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0);
+ signal buf_STAT_INIT_OBUF_DEBUG : std_logic_vector (32*4-1 downto 0);
+ signal buf_STAT_REPLY_OBUF_DEBUG : std_logic_vector (32*4-1 downto 0);
+
+ signal REGIO_REGIO_STAT : std_logic_vector(31 downto 0);
+
+ signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal buf_REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0);
+ signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0);
+ signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
+ signal buf_IDRAM_WR_IN : std_logic;
+ signal reset_no_link : std_logic;
+ signal ONEWIRE_DATA : std_logic_vector(15 downto 0);
+ signal ONEWIRE_ADDR : std_logic_vector(2 downto 0);
+ signal ONEWIRE_WRITE : std_logic;
+
+ signal buf_COMMON_STAT_REG_STROBE : std_logic_vector((std_COMSTATREG)-1 downto 0);
+ signal buf_COMMON_CTRL_REG_STROBE : std_logic_vector((std_COMCTRLREG)-1 downto 0);
+ signal buf_STAT_REG_STROBE : std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+ signal buf_CTRL_REG_STROBE : std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ signal int_trigger_num : std_logic_vector(15 downto 0);
+
+ signal buf_LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0);
+ signal buf_LVL1_TRG_RECEIVED_OUT : std_logic;
+ signal buf_LVL1_TRG_NUMBER_OUT : std_logic_vector(15 downto 0);
+ signal buf_LVL1_TRG_CODE_OUT : std_logic_vector(7 downto 0);
+ signal buf_LVL1_TRG_INFORMATION_OUT : std_logic_vector(23 downto 0);
+ signal last_LVL1_TRG_RECEIVED_OUT : std_logic;
+ signal LVL1_TRG_RECEIVED_OUT_rising : std_logic;
+ signal LVL1_TRG_RECEIVED_OUT_falling: std_logic;
+ signal buf_LVL1_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
+
+ signal temperature : std_logic_vector(11 downto 0);
+ signal got_timing_trigger : std_logic;
+ signal got_timingless_trigger : std_logic;
+ signal trigger_number_match : std_logic;
+ signal buf_TIMER_TICKS_OUT : std_logic_vector(1 downto 0);
+-- signal timing_trigger_missing : std_logic;
+
+ signal buf_LVL1_VALID_TIMING_TRG_OUT : std_logic;
+ signal buf_LVL1_VALID_NOTIMING_TRG_OUT : std_logic;
+ signal buf_LVL1_INVALID_TRG_OUT : std_logic;
+ signal buf_LVL1_TRG_RELEASE_IN : std_logic;
+ signal buf_LVL1_TRG_DATA_VALID_OUT : std_logic;
+
+ signal int_lvl1_delay : std_logic_vector(15 downto 0);
+ signal int_trg_reset : std_logic;
+ signal reset_trg_logic : std_logic;
+ signal stat_lvl1_handler : std_logic_vector(63 downto 0);
+ signal stat_counters_lvl1_handler: std_logic_vector(79 downto 0);
+ signal trg_invert_i : std_logic;
+ signal int_multiple_trg : std_logic;
+ signal int_lvl1_timeout_detected : std_logic;
+ signal int_lvl1_spurious_trg : std_logic;
+ signal int_lvl1_missing_tmg_trg : std_logic;
+ signal int_spike_detected : std_logic;
+ signal int_lvl1_long_trg : std_logic;
+
+
+ signal last_TRG_TIMING_TRG_RECEIVED_IN : std_logic;
+ signal last_timingtrg_counter_write : std_logic;
+ signal last_timingtrg_counter_read : std_logic;
+
+ signal reg_timing_trigger : std_logic;
+ signal trigger_timing_rising : std_logic;
+ signal last_reg_timing_trigger : std_logic;
+-- signal timing_trigger_missing_stat : std_logic;
+
+ signal link_error_i : std_logic;
+ signal link_and_reset_status : std_logic_vector(31 downto 0);
+
+ signal make_trbnet_reset : std_logic;
+ signal last_make_trbnet_reset : std_logic;
+ signal lvl1_tmg_trg_missing_flag : std_logic;
+
+ component edge_to_pulse is
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+begin
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ reset_no_link <= MED_STAT_OP_IN(14) or RESET;
+ reset_trg_logic <= RESET or buf_REGIO_COMMON_CTRL_REG_OUT(1);
+ end if;
+ end process;
+
+ MED_CTRL_OP_OUT(7 downto 0) <= (others => '0');
+ MED_CTRL_OP_OUT(8) <= buf_REGIO_COMMON_CTRL_REG_OUT(64+27);
+ MED_CTRL_OP_OUT(15 downto 9) <= (others => '0');
+ MED_STAT_OP <= MED_STAT_OP_IN;
+
+ --Connections for data channel
+ genbuffers : for i in 0 to 3 generate
+ geniobuf: if USE_CHANNEL(i) = c_YES generate
+ IOBUF: trb_net16_iobuf
+ generic map (
+ IBUF_DEPTH => 6,
+ IBUF_SECURE_MODE => c_YES,
+ SBUF_VERSION => 0,
+ SBUF_VERSION_OBUF => 6,
+ OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH,
+ USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(i),
+ USE_CHECKSUM => USE_CHECKSUM(i),
+ USE_VENDOR_CORES => c_YES,
+ INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA(i),
+ REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA(i),
+ REPLY_CAN_RECEIVE_DATA => REPLY_CAN_RECEIVE_DATA(i)
+ )
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => reset_no_link,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),
+ MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
+ MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
+ MED_INIT_READ_IN => MED_IO_READ_IN(i*2),
+
+ MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
+ MED_DATA_IN => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ MED_READ_OUT => MED_IO_READ_OUT(i),
+ MED_ERROR_IN => MED_STAT_OP_IN(2 downto 0),
+
+ MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
+ MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
+ MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1),
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i),
+ INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_INIT_READ_IN => buf_to_apl_INIT_READ(i),
+
+ INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i),
+ INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i),
+
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i),
+ INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i),
+
+ INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i),
+ INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i),
+
+ -- Status and control port
+ STAT_GEN => buf_STAT_GEN(32*(i+1)-1 downto i*32),
+ STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32),
+ CTRL_GEN => buf_CTRL_GEN(32*(i+1)-1 downto i*32),
+ STAT_INIT_OBUF_DEBUG => buf_STAT_INIT_OBUF_DEBUG(32*(i+1)-1 downto i*32),
+ STAT_REPLY_OBUF_DEBUG => buf_STAT_REPLY_OBUF_DEBUG(32*(i+1)-1 downto i*32),
+ TIMER_TICKS_IN => buf_TIMER_TICKS_OUT,
+ CTRL_STAT => x"0000"
+ );
+
+ gen_api : if i /= c_TRG_LVL1_CHANNEL generate
+ constant j : integer := i;
+ begin
+ DAT_PASSIVE_API: trb_net16_api_base
+ generic map (
+ API_TYPE => c_API_PASSIVE,
+ FIFO_TO_INT_DEPTH => 6,
+ FIFO_TO_APL_DEPTH => 6,
+ FORCE_REPLY => cfg_FORCE_REPLY(i),
+ SBUF_VERSION => 0,
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS=> APL_WRITE_ALL_WORDS(i),
+ ADDRESS_MASK => ADDRESS_MASK,
+ BROADCAST_BITMASK => BROADCAST_BITMASK,
+ BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => buf_APL_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
+ APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
+ APL_DATAREADY_IN => buf_APL_DATAREADY_IN(j),
+ APL_READ_OUT => buf_APL_READ_OUT(j),
+ APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(j),
+ APL_DTYPE_IN => buf_APL_DTYPE_IN((j+1)*4-1 downto j*4),
+ APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((j+1)*32-1 downto j*32),
+ APL_SEND_IN => buf_APL_SEND_IN(j),
+ APL_TARGET_ADDRESS_IN => (others => '0'),
+ -- Receiver port
+ APL_DATA_OUT => buf_APL_DATA_OUT((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
+ APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
+ APL_TYP_OUT => buf_APL_TYP_OUT((j+1)*3-1 downto j*3),
+ APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(j),
+ APL_READ_IN => buf_APL_READ_IN(j),
+ -- APL Control port
+ APL_RUN_OUT => buf_APL_RUN_OUT(j),
+ APL_MY_ADDRESS_IN => MY_ADDRESS,
+ APL_SEQNR_OUT => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8),
+ APL_LENGTH_IN => buf_APL_LENGTH_IN((j+1)*16-1 downto j*16),
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
+ INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i),
+ INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
+ INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i),
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
+ INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i),
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
+ INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i),
+ -- Status and control port
+ CTRL_SEQNR_RESET => buf_REGIO_COMMON_CTRL_REG_OUT(10),
+ STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
+ STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)
+ );
+ end generate;
+
+ gentrgapi : if i = c_TRG_LVL1_CHANNEL generate
+ buf_APL_READ_OUT(i) <= '0';
+ buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ buf_APL_DATAREADY_OUT(i) <= '0';
+ buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8) <= (others => '0');
+ buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ buf_APL_DTYPE_IN((i+1)*4-1 downto i*4) <= (others => '0');
+ buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');
+ buf_APL_RUN_OUT(i) <= '0';
+ buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_APL_READ_IN(i) <= '0';
+ buf_APL_SHORT_TRANSFER_IN(i) <= '0';
+ buf_APL_TYP_OUT((i+1)*3-1 downto i*3) <= (others => '0');
+ buf_APL_DATAREADY_IN(i) <= '0';
+ buf_APL_SEND_IN(i) <= '0';
+ buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+
+ apl_to_buf_INIT_DATAREADY(i) <= '0';
+ apl_to_buf_INIT_DATA((i+1)*16-1 downto i*16) <= (others => '0');
+ apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ apl_to_buf_INIT_READ(i) <= '0';
+
+ buf_to_apl_REPLY_READ(i) <= '1';
+ buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ buf_to_apl_REPLY_DATAREADY(i) <= '0';
+ buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+
+ buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32) <= (others => '0');
+
+
+ the_trigger_apl : trb_net16_trigger
+ generic map(
+ USE_TRG_PORT => c_YES,
+ SECURE_MODE => std_TERM_SECURE_MODE
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
+ INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_READ_IN => apl_to_buf_REPLY_READ(i),
+ INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
+ INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_READ_OUT => buf_to_apl_INIT_READ(i),
+ TRG_RECEIVED_OUT => buf_LVL1_TRG_RECEIVED_OUT,
+ TRG_TYPE_OUT => buf_LVL1_TRG_TYPE_OUT,
+ TRG_NUMBER_OUT => buf_LVL1_TRG_NUMBER_OUT,
+ TRG_CODE_OUT => buf_LVL1_TRG_CODE_OUT,
+ TRG_INFORMATION_OUT => buf_LVL1_TRG_INFORMATION_OUT,
+ TRG_RELEASE_IN => buf_LVL1_TRG_RELEASE_IN,
+ TRG_ERROR_PATTERN_IN => buf_LVL1_ERROR_PATTERN_IN
+ );
+ end generate;
+
+ gen_ipu_apl : if i = c_DATA_CHANNEL generate
+ the_ipudata_apl : trb_net16_ipudata
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ API_DATA_OUT => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ API_DATAREADY_OUT => buf_APL_DATAREADY_IN(i),
+ API_READ_IN => buf_APL_READ_OUT(i),
+ API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(i),
+ API_DTYPE_OUT => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4),
+ API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),
+ API_SEND_OUT => buf_APL_SEND_IN(i),
+ API_DATA_IN => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ API_TYP_IN => buf_APL_TYP_OUT((i+1)*3-1 downto i*3),
+ API_DATAREADY_IN => buf_APL_DATAREADY_OUT(i),
+ API_READ_OUT => buf_APL_READ_IN(i),
+ API_RUN_IN => buf_APL_RUN_OUT(i),
+ API_SEQNR_IN => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),
+ API_LENGTH_OUT => buf_APL_LENGTH_IN((i+1)*16-1 downto i*16),
+ MY_ADDRESS_IN => MY_ADDRESS,
+ --Information received with request
+ IPU_NUMBER_OUT => IPU_NUMBER_OUT,
+ IPU_READOUT_TYPE_OUT => IPU_READOUT_TYPE_OUT,
+ IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
+ --start strobe
+ IPU_START_READOUT_OUT => IPU_START_READOUT_OUT,
+ --detector data, equipped with DHDR
+ IPU_DATA_IN => IPU_DATA_IN,
+ IPU_DATAREADY_IN => IPU_DATAREADY_IN,
+ --no more data, end transfer, send TRM
+ IPU_READOUT_FINISHED_IN=> IPU_READOUT_FINISHED_IN,
+ --will be low every second cycle due to 32bit -> 16bit conversion
+ IPU_READ_OUT => IPU_READ_OUT,
+ IPU_LENGTH_IN => IPU_LENGTH_IN,
+ IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,
+ STAT_DEBUG => STAT_DEBUG_IPU
+ );
+ end generate;
+
+ gen_regio : if i = c_SLOW_CTRL_CHANNEL generate
+ buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');
+
+ regIO : trb_net16_regIO
+ generic map(
+ NUM_STAT_REGS => REGIO_NUM_STAT_REGS,
+ NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,
+ --standard values for output registers
+ INIT_CTRL_REGS => REGIO_INIT_CTRL_REGS,
+ --set to 0 for unused ctrl registers to save resources
+ USED_CTRL_REGS => REGIO_USED_CTRL_REGS,
+ --set to 0 for each unused bit in a register
+ USED_CTRL_BITMASK => REGIO_USED_CTRL_BITMASK,
+ --no data / address out?
+ USE_DAT_PORT => REGIO_USE_DAT_PORT,
+ INIT_ADDRESS => REGIO_INIT_ADDRESS,
+ INIT_UNIQUE_ID => REGIO_INIT_UNIQUE_ID,
+ INIT_ENDPOINT_ID => REGIO_INIT_ENDPOINT_ID,
+ COMPILE_TIME => REGIO_COMPILE_TIME,
+ COMPILE_VERSION => REGIO_COMPILE_VERSION,
+ HARDWARE_VERSION => REGIO_HARDWARE_VERSION,
+ CLOCK_FREQ => CLOCK_FREQUENCY
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Port to API
+ API_DATA_OUT => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ API_DATAREADY_OUT => buf_APL_DATAREADY_IN(i),
+ API_READ_IN => buf_APL_READ_OUT(i),
+ API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(i),
+ API_DTYPE_OUT => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4),
+ API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),
+ API_SEND_OUT => buf_APL_SEND_IN(3),
+ API_DATA_IN => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ API_TYP_IN => buf_APL_TYP_OUT((i+1)*3-1 downto i*3),
+ API_DATAREADY_IN => buf_APL_DATAREADY_OUT(i),
+ API_READ_OUT => buf_APL_READ_IN(i),
+ API_RUN_IN => buf_APL_RUN_OUT(i),
+ API_SEQNR_IN => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),
+ --Port to write Unique ID
+ IDRAM_DATA_IN => buf_IDRAM_DATA_IN,
+ IDRAM_DATA_OUT => buf_IDRAM_DATA_OUT,
+ IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN,
+ IDRAM_WR_IN => buf_IDRAM_WR_IN,
+ MY_ADDRESS_OUT => MY_ADDRESS,
+ TRIGGER_MONITOR => buf_LVL1_VALID_TIMING_TRG_OUT,
+ GLOBAL_TIME => GLOBAL_TIME_OUT,
+ LOCAL_TIME => LOCAL_TIME_OUT,
+ TIME_SINCE_LAST_TRG => TIME_SINCE_LAST_TRG_OUT,
+ TIMER_US_TICK => buf_TIMER_TICKS_OUT(0),
+ TIMER_MS_TICK => buf_TIMER_TICKS_OUT(1),
+ --Common Register in / out
+ COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN,
+ COMMON_CTRL_REG_OUT => buf_REGIO_COMMON_CTRL_REG_OUT,
+ --Custom Register in / out
+ REGISTERS_IN => REGIO_REGISTERS_IN,
+ REGISTERS_OUT => REGIO_REGISTERS_OUT,
+ COMMON_STAT_REG_STROBE => buf_COMMON_STAT_REG_STROBE,
+ COMMON_CTRL_REG_STROBE => buf_COMMON_CTRL_REG_STROBE,
+ STAT_REG_STROBE => buf_STAT_REG_STROBE,
+ CTRL_REG_STROBE => buf_CTRL_REG_STROBE,
+ --following ports only used when no internal register is accessed
+ DAT_ADDR_OUT => REGIO_ADDR_OUT,
+ DAT_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
+ DAT_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,
+ DAT_DATA_OUT => REGIO_DATA_OUT,
+ DAT_DATA_IN => REGIO_DATA_IN,
+ DAT_DATAREADY_IN => REGIO_DATAREADY_IN,
+ DAT_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN,
+ DAT_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
+ DAT_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
+ DAT_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
+ STAT => REGIO_REGIO_STAT,
+ STAT_ADDR_DEBUG => STAT_ADDR_DEBUG
+ );
+ gen_no1wire : if REGIO_USE_1WIRE_INTERFACE = c_NO generate
+ ONEWIRE_DATA <= REGIO_IDRAM_DATA_IN;
+ ONEWIRE_ADDR <= REGIO_IDRAM_ADDR_IN;
+ ONEWIRE_WRITE <= REGIO_IDRAM_WR_IN;
+ REGIO_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT;
+ REGIO_ONEWIRE_INOUT <= '0';
+ REGIO_ONEWIRE_MONITOR_OUT <= '0';
+
+ end generate;
+ gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate
+
+
+ REGIO_IDRAM_DATA_OUT <= (others => '0');
+
+ onewire_interface : trb_net_onewire
+ generic map(
+ USE_TEMPERATURE_READOUT => c_YES,
+ CLK_PERIOD => 10
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ --connection to 1-wire interface
+ ONEWIRE => REGIO_ONEWIRE_INOUT,
+ MONITOR_OUT => REGIO_ONEWIRE_MONITOR_OUT,
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT => ONEWIRE_DATA,
+ ADDR_OUT => ONEWIRE_ADDR,
+ WRITE_OUT=> ONEWIRE_WRITE,
+ TEMP_OUT => temperature,
+ STAT => STAT_ONEWIRE
+ );
+ end generate;
+ gen_1wire_monitor : if REGIO_USE_1WIRE_INTERFACE = c_MONITOR generate
+ REGIO_IDRAM_DATA_OUT <= (others => '0');
+ REGIO_ONEWIRE_MONITOR_OUT <= '0';
+
+ onewire_interface : trb_net_onewire_listener
+ port map(
+ CLK => CLK,
+ CLK_EN => CLK_EN,
+ RESET => RESET,
+ --connection to 1-wire interface
+ MONITOR_IN => REGIO_ONEWIRE_MONITOR_IN,
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT => ONEWIRE_DATA,
+ ADDR_OUT => ONEWIRE_ADDR,
+ WRITE_OUT=> ONEWIRE_WRITE,
+ TEMP_OUT => temperature,
+ STAT => STAT_ONEWIRE
+ );
+ end generate;
+ end generate;
+ end generate;
+ gentermbuf: if USE_CHANNEL(i) = c_NO generate
+ buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ buf_APL_READ_OUT(i) <= '0';
+ buf_APL_DATAREADY_OUT(i) <= '0';
+ buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8) <= (others => '0');
+ buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ buf_APL_DTYPE_IN((i+1)*4-1 downto i*4) <= (others => '0');
+ buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');
+ buf_APL_RUN_OUT(i) <= '0';
+ buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_APL_READ_IN(i) <= '0';
+ buf_APL_SHORT_TRANSFER_IN(i) <= '0';
+ buf_APL_TYP_OUT((i+1)*3-1 downto i*3) <= (others => '0');
+ buf_APL_DATAREADY_IN(i) <= '0';
+ buf_APL_SEND_IN(i) <= '0';
+
+ apl_to_buf_INIT_READ(i) <= '0';
+ apl_to_buf_INIT_DATAREADY(i) <= '0';
+ apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ apl_to_buf_REPLY_DATAREADY(i) <= '0';
+ apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ apl_to_buf_REPLY_READ(i) <= '0';
+ apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+
+ buf_to_apl_INIT_READ(i) <= '0';
+ buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ buf_to_apl_INIT_DATAREADY(i) <= '0';
+ buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ buf_to_apl_REPLY_DATAREADY(i) <= '0';
+ buf_to_apl_REPLY_READ(i) <= '0';
+ buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+
+ buf_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_STAT_GEN((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_STAT_INIT_BUFFER((i+1)*32-1 downto i*32) <= (others => '0');
+
+ termbuf: trb_net16_term_buf
+ port map(
+ CLK => CLK,
+ RESET => reset_no_link,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
+ MED_DATA_IN => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ MED_READ_OUT => MED_IO_READ_OUT(i),
+
+ MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),
+ MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
+ MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
+ MED_INIT_READ_IN => MED_IO_READ_IN(i*2),
+ MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
+ MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
+ MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1)
+ );
+ end generate;
+ end generate;
+
+
+ MPLEX: trb_net16_io_multiplexer
+ generic map(
+ USE_INPUT_SBUF => (1,1,1,1,0,0,1,1)
+ )
+ port map (
+ CLK => CLK,
+ RESET => reset_no_link,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ INT_DATAREADY_OUT => MED_IO_DATAREADY_IN,
+ INT_DATA_OUT => MED_IO_DATA_IN,
+ INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN,
+ INT_READ_IN => MED_IO_READ_OUT,
+ INT_DATAREADY_IN => MED_IO_DATAREADY_OUT,
+ INT_DATA_IN => MED_IO_DATA_OUT,
+ INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT,
+ INT_READ_OUT => MED_IO_READ_IN,
+ STAT => open,
+ CTRL => CTRL_MPLEX
+ );
+
+-------------------------------------------------
+-- Include variable Endpoint ID
+-------------------------------------------------
+ gen_var_endpoint_id : if REGIO_USE_VAR_ENDPOINT_ID = c_YES generate
+ buf_IDRAM_DATA_IN <= REGIO_VAR_ENDPOINT_ID when RESET = '1' else ONEWIRE_DATA;
+ buf_IDRAM_ADDR_IN <= "100" when RESET = '1' else ONEWIRE_ADDR;
+ buf_IDRAM_WR_IN <= '1' when RESET = '1' else ONEWIRE_WRITE;
+ end generate;
+
+ gen_no_var_endpoint_id : if REGIO_USE_VAR_ENDPOINT_ID = c_NO generate
+ buf_IDRAM_DATA_IN <= ONEWIRE_DATA;
+ buf_IDRAM_ADDR_IN <= ONEWIRE_ADDR;
+ buf_IDRAM_WR_IN <= ONEWIRE_WRITE;
+ end generate;
+
+
+
+-------------------------------------------------
+-- Common Status Register
+-------------------------------------------------
+ proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, trigger_number_match, temperature, int_trigger_num,
+ link_error_i, link_and_reset_status, stat_lvl1_handler)
+ begin
+ buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN;
+ buf_COMMON_STAT_REG_IN(4) <= stat_lvl1_handler(12);
+ buf_COMMON_STAT_REG_IN(8) <= lvl1_tmg_trg_missing_flag;
+ buf_COMMON_STAT_REG_IN(13) <= stat_lvl1_handler(7);
+ buf_COMMON_STAT_REG_IN(15) <= link_error_i;
+ if REGIO_USE_1WIRE_INTERFACE = c_YES then
+ buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature;
+ end if;
+ buf_COMMON_STAT_REG_IN(47 downto 32) <= int_trigger_num;
+ buf_COMMON_STAT_REG_IN(127 downto 64) <= stat_lvl1_handler;
+ buf_COMMON_STAT_REG_IN(159 downto 128) <= link_and_reset_status(31 downto 0);
+ buf_COMMON_STAT_REG_IN(175 downto 160) <= buf_LVL1_TRG_INFORMATION_OUT(15 downto 0);
+ buf_COMMON_STAT_REG_IN(179 downto 176) <= buf_LVL1_TRG_TYPE_OUT;
+ buf_COMMON_STAT_REG_IN(183 downto 180) <= buf_LVL1_TRG_NUMBER_OUT(3 downto 0);
+ buf_COMMON_STAT_REG_IN(191 downto 184) <= buf_LVL1_TRG_CODE_OUT;
+ buf_COMMON_STAT_REG_IN(271 downto 192) <= stat_counters_lvl1_handler;
+ buf_COMMON_STAT_REG_IN(287 downto 272) <= (others => '0');
+ end process;
+
+
+
+ REG_LINK_ERROR : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if buf_REGIO_COMMON_CTRL_REG_OUT(4) = '1' then
+ link_error_i <= '0';
+ elsif MED_STAT_OP_IN(15) = '0' and MED_STAT_OP_IN(13) = '0' and MED_STAT_OP_IN(7 downto 4) = "0111" then
+ link_error_i <= '1';
+ end if;
+
+ if buf_REGIO_COMMON_CTRL_REG_OUT(4) = '1' then
+ lvl1_tmg_trg_missing_flag <= '0';
+ elsif int_lvl1_missing_tmg_trg = '1' or int_lvl1_spurious_trg = '1' or int_spike_detected = '1' then
+ lvl1_tmg_trg_missing_flag <= '1';
+ end if;
+
+-- if LVL1_TRG_RECEIVED_OUT_falling = '1' then
+-- timing_trigger_missing_stat <= timing_trigger_missing;
+-- end if;
+
+ if make_trbnet_reset = '1' then
+ link_and_reset_status(3 downto 0) <= link_and_reset_status(3 downto 0) + '1';
+ end if;
+
+ if MED_STAT_OP_IN(12) = '1' then
+ link_and_reset_status(31 downto 24) <= link_and_reset_status(31 downto 24) + '1';
+ end if;
+
+ if MED_STAT_OP_IN(8) = '1' then
+ link_and_reset_status(23 downto 16) <= link_and_reset_status(23 downto 16) + '1';
+ end if;
+
+ if buf_REGIO_COMMON_CTRL_REG_OUT(5) = '1' then
+ link_and_reset_status <= (others => '0');
+ end if;
+
+ end if;
+ end process;
+
+ PROC_FIND_TRBNET_RESET : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ last_make_trbnet_reset <= MED_STAT_OP_IN(13);
+ make_trbnet_reset <= MED_STAT_OP_IN(13) and not last_make_trbnet_reset;
+ end if;
+ end process;
+
+-------------------------------------------------
+-- Check LVL1 trigger number
+-------------------------------------------------
+
+ THE_LVL1_HANDLER : handler_lvl1
+ generic map (
+ TIMING_TRIGGER_RAW => TIMING_TRIGGER_RAW
+ )
+ port map(
+ RESET => reset_trg_logic,
+ RESET_FLAGS_IN => buf_REGIO_COMMON_CTRL_REG_OUT(4),
+ RESET_STATS_IN => buf_REGIO_COMMON_CTRL_REG_OUT(5),
+ CLOCK => CLK,
+ --Timing Trigger
+ LVL1_TIMING_TRG_IN => TRG_TIMING_TRG_RECEIVED_IN,
+ LVL1_PSEUDO_TMG_TRG_IN => buf_REGIO_COMMON_CTRL_REG_OUT(16),
+ --LVL1_handler connection
+ LVL1_TRG_RECEIVED_IN => buf_LVL1_TRG_RECEIVED_OUT,
+ LVL1_TRG_TYPE_IN => buf_LVL1_TRG_TYPE_OUT,
+ LVL1_TRG_NUMBER_IN => buf_LVL1_TRG_NUMBER_OUT,
+ LVL1_TRG_CODE_IN => buf_LVL1_TRG_CODE_OUT,
+ LVL1_TRG_INFORMATION_IN => buf_LVL1_TRG_INFORMATION_OUT,
+ LVL1_ERROR_PATTERN_OUT => buf_LVL1_ERROR_PATTERN_IN,
+ LVL1_TRG_RELEASE_OUT => buf_LVL1_TRG_RELEASE_IN,
+
+ LVL1_INT_TRG_NUMBER_OUT => int_trigger_num,
+ LVL1_INT_TRG_LOAD_IN => buf_COMMON_CTRL_REG_STROBE(1),
+ LVL1_INT_TRG_COUNTER_IN => buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32),
+
+ --FEE logic / Data Handler
+ LVL1_TRG_DATA_VALID_OUT => buf_LVL1_TRG_DATA_VALID_OUT,
+ LVL1_VALID_TIMING_TRG_OUT => buf_LVL1_VALID_TIMING_TRG_OUT,
+ LVL1_VALID_NOTIMING_TRG_OUT => buf_LVL1_VALID_NOTIMING_TRG_OUT,
+ LVL1_INVALID_TRG_OUT => buf_LVL1_INVALID_TRG_OUT,
+ LVL1_MULTIPLE_TRG_OUT => int_multiple_trg,
+ LVL1_DELAY_OUT => int_lvl1_delay,
+ LVL1_TIMEOUT_DETECTED_OUT => int_lvl1_timeout_detected,
+ LVL1_SPURIOUS_TRG_OUT => int_lvl1_spurious_trg,
+ LVL1_MISSING_TMG_TRG_OUT => int_lvl1_missing_tmg_trg,
+ LVL1_LONG_TRG_OUT => int_lvl1_long_trg,
+ SPIKE_DETECTED_OUT => int_spike_detected,
+
+ LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,
+ LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
+
+ --Stat/Control
+ STATUS_OUT => stat_lvl1_handler,
+ TRG_ENABLE_IN => buf_REGIO_COMMON_CTRL_REG_OUT(95),
+ TRG_INVERT_IN => buf_REGIO_COMMON_CTRL_REG_OUT(93),
+ COUNTERS_STATUS_OUT => stat_counters_lvl1_handler,
+ --Debug
+ DEBUG_OUT => DEBUG_LVL1_HANDLER_OUT
+ );
+
+ TRG_SPIKE_DETECTED_OUT <= int_spike_detected;
+ TRG_SPURIOUS_TRG_OUT <= int_lvl1_spurious_trg;
+ TRG_TIMEOUT_DETECTED_OUT <= int_lvl1_timeout_detected;
+ TRG_MULTIPLE_TRG_OUT <= int_multiple_trg;
+ TRG_MISSING_TMG_TRG_OUT <= int_lvl1_missing_tmg_trg;
+ TRG_LONG_TRG_OUT <= int_lvl1_long_trg;
+
+
+ LVL1_TRG_DATA_VALID_OUT <= buf_LVL1_TRG_DATA_VALID_OUT; --changed back
+
+ LVL1_TRG_VALID_TIMING_OUT <= buf_LVL1_VALID_TIMING_TRG_OUT;
+ LVL1_TRG_VALID_NOTIMING_OUT <= buf_LVL1_VALID_NOTIMING_TRG_OUT;
+ LVL1_TRG_INVALID_OUT <= buf_LVL1_INVALID_TRG_OUT;
+
+ LVL1_TRG_TYPE_OUT <= buf_LVL1_TRG_TYPE_OUT;
+ LVL1_TRG_NUMBER_OUT <= buf_LVL1_TRG_NUMBER_OUT;
+ LVL1_TRG_CODE_OUT <= buf_LVL1_TRG_CODE_OUT;
+ LVL1_TRG_INFORMATION_OUT <= buf_LVL1_TRG_INFORMATION_OUT;
+ LVL1_INT_TRG_NUMBER_OUT <= int_trigger_num;
+
+ COMMON_STAT_REG_STROBE <= buf_COMMON_STAT_REG_STROBE;
+ COMMON_CTRL_REG_STROBE <= buf_COMMON_CTRL_REG_STROBE;
+ STAT_REG_STROBE <= buf_STAT_REG_STROBE;
+ CTRL_REG_STROBE <= buf_CTRL_REG_STROBE;
+
+ TIMER_TICKS_OUT <= buf_TIMER_TICKS_OUT;
+
+ buf_CTRL_GEN <= IOBUF_CTRL_GEN;
+ REGIO_COMMON_CTRL_REG_OUT <= buf_REGIO_COMMON_CTRL_REG_OUT;
+
+ STAT_DEBUG_1 <= REGIO_REGIO_STAT;
+ STAT_DEBUG_2(3 downto 0) <= MED_IO_DATA_OUT(7*16+3 downto 7*16);
+ STAT_DEBUG_2(7 downto 4) <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16);
+ STAT_DEBUG_2(8) <= apl_to_buf_REPLY_DATAREADY(3);
+ STAT_DEBUG_2(11 downto 9) <= apl_to_buf_REPLY_PACKET_NUM(3*3+2 downto 3*3);
+ STAT_DEBUG_2(15 downto 12) <= (others => '0');
+ STAT_DEBUG_2(31 downto 16) <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32);
+
+ STAT_TRIGGER_OUT <= stat_counters_lvl1_handler;
+
+end architecture;
+
HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_YES; --not used any more
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) :=
generic map (
IBUF_DEPTH => calc_depth(i,MII_IBUF_DEPTH, INT_IBUF_DEPTH, MII_NUMBER, INT_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
USE_CHECKSUM => USE_CHECKSUM(k),
- IBUF_SECURE_MODE => IBUF_SECURE_MODE,
SBUF_VERSION => 0,
SBUF_VERSION_OBUF => 6,
OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH,
--type for hub arrays
type hub_iobuf_config_t is array(0 to 67) of integer; --2**(c_MUX_WIDTH-1)*c_MAX_MII_PER_HUB-1
- type hub_api_config_t is array(0 to 9) of integer;
+ type hub_api_config_t is array(0 to 16) of integer;
type hub_api_broadcast_t is array(0 to 7) of std_logic_vector(7 downto 0);
type hub_channel_config_t is array(0 to 2**(3-1)-1) of integer;
type hub_mii_config_t is array(0 to 16) of integer;
component trb_net16_hub_streaming_port_sctrl is
generic(
--hub control
+ HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_YES;
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
entity trb_net16_hub_streaming_port_sctrl is
generic(
--hub control
+ HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
--hub control
HUB_CTRL_CHANNELNUM => c_SLOW_CTRL_CHANNEL,
HUB_CTRL_DEPTH => c_FIFO_BRAM,
- HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES),
+ HUB_USED_CHANNELS => HUB_USED_CHANNELS,
USE_CHECKSUM => (c_NO,c_YES,c_YES,c_YES),
USE_VENDOR_CORES => c_YES,
IBUF_SECURE_MODE => c_NO,
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
-
+use work.version.all;
INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; --not used any more!
COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
CLOCK_FREQ : integer range 1 to 200 := 100 --MHz
-- for whole architecture
attribute HGROUP of trb_net16_regIO_arch : architecture is "RegIO_group";
-
+ constant COMPILE_TIME_LIB : std_logic_vector(31 downto 0) := conv_std_logic_vector(VERSION_NUMBER_TIME,32);
type fsm_state_t is (IDLE, HEADER_RECV, REG_READ, REG_WRITE, ONE_READ, ONE_WRITE, SEND_REPLY_SHORT_TRANSFER, MEM_START_WRITE,
MEM_READ, MEM_WRITE, DAT_START_READ, DAT_READ, SEND_REPLY_DATA_finish, ADDRESS_ACK, ADDRESS_RECV,
---------------------------------------------------------------------
board_rom : rom_16x8
generic map(
- INIT0 => COMPILE_TIME(15 downto 0),
- INIT1 => COMPILE_TIME(31 downto 16),
+ INIT0 => COMPILE_TIME_LIB(15 downto 0),
+ INIT1 => COMPILE_TIME_LIB(31 downto 16),
INIT2 => COMPILE_VERSION,
INIT3 => (others => '0'),
INIT4 => HARDWARE_VERSION(15 downto 0),
architecture regio_bus_handler_arch of trb_net16_regio_bus_handler is
-- Placer Directives
- attribute HGROUP : string;
+-- attribute HGROUP : string;
-- for whole architecture
- attribute HGROUP of regio_bus_handler_arch : architecture is "Bus_handler_group";
+-- attribute HGROUP of regio_bus_handler_arch : architecture is "Bus_handler_group";
signal port_select_int : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS;
signal next_port_select_int : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS;
signal buf_BUS_NO_MORE_DATA_IN : std_logic_vector(PORT_NUMBER downto 0);
signal buf_BUS_UNKNOWN_ADDR_IN : std_logic_vector(PORT_NUMBER downto 0);
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_preserve of buf_BUS_ADDR_OUT : signal is true;
+ attribute syn_keep of buf_BUS_ADDR_OUT : signal is true;
+ attribute syn_preserve of buf_BUS_DATA_OUT : signal is true;
+ attribute syn_keep of buf_BUS_DATA_OUT : signal is true;
+
begin
---------------------------------------------------------------------
jspc29 / trbnet.git / commitdiff