-- Slow Control
-------------------------------------------------------------------------------
- BUS_SLOWCTRL: entity work.BusHandler_record
+ TheSlowcontrolBus: entity work.BusHandler_record
generic map (
BUS_LENGTH => 8)
port map (
-- Slow control signals
- logic_anal_control <= ctrl_reg(0)(3 downto 0) when rising_edge(CLK_READOUT);
+ logic_anal_control <= ctrl_reg(0)(3 downto 0);
debug_mode_en <= ctrl_reg(0)(4);
- light_mode_en <= ctrl_reg(0)(5) when rising_edge(CLK_READOUT);
+ light_mode_en <= ctrl_reg(0)(5);
reset_counters <= ctrl_reg(0)(8) or reset_tdc when rising_edge(CLK_TDC);
--run_mode <= ctrl_reg(0)(12);
--run_mode_200 <= run_mode when rising_edge(CLK_TDC);
trg_win_pre <= ctrl_reg(1)(10 downto 0);
trg_win_post <= ctrl_reg(1)(26 downto 16);
trg_win_en <= ctrl_reg(1)(31);
-
ch_en <= ctrl_reg(3) & ctrl_reg(2);
- ring_buffer_full_thres <= ctrl_reg(4)(6 downto 0) when rising_edge(CLK_READOUT);
+ ring_buffer_full_thres <= ctrl_reg(4)(6 downto 0);
ch_invert <= ctrl_reg(6) & ctrl_reg(5);
-- Reset signals
end generate GenHitDetectNumber;
-- Status register
- BusHandler_record_1: entity work.BusHandler_record
+ TheStatusRegisterBus: entity work.BusHandler_record
generic map (
BUS_LENGTH => STATUS_REG_NR-1)
port map (
-- Channel debug
- BusHandler_record_2: entity work.BusHandler_record
+ TheChannelDebugBus: entity work.BusHandler_record
generic map (
BUS_LENGTH => CHANNEL_NUMBER-1)
port map (
---------------------------------------------------------------------------
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 6,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d400", 2 => x"c000", 3 => x"cf00", 4 => x"cf80",
- 5 => x"d500",
- others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 12, 3 => 6, 4 => 7,
- 5 => 4,
- others => 0)
+ PORT_NUMBER => 6,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d400", 2 => x"c000", 3 => x"cf00", 4 => x"cf80",
+ 5 => x"d500",
+ others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 12, 3 => 6, 4 => 7,
+ 5 => 4,
+ others => 0),
+ PORT_MASK_ENABLE => 1
)
port map(
CLK => clk_100_i,
BUS_NO_MORE_DATA_IN(4) => '0',
BUS_UNKNOWN_ADDR_IN(4) => stat_nack,
--SEU Detection
- BUS_READ_ENABLE_OUT(5) => bussed_rx.read,
- BUS_WRITE_ENABLE_OUT(5) => bussed_rx.write,
- BUS_DATA_OUT(5*32+31 downto 5*32) => bussed_rx.data,
- BUS_ADDR_OUT(5*16+15 downto 5*16) => bussed_rx.addr,
+ BUS_READ_ENABLE_OUT(5) => bussed_rx.read,
+ BUS_WRITE_ENABLE_OUT(5) => bussed_rx.write,
+ BUS_DATA_OUT(5*32+31 downto 5*32) => bussed_rx.data,
+ BUS_ADDR_OUT(5*16+15 downto 5*16) => bussed_rx.addr,
BUS_TIMEOUT_OUT(5) => bussed_rx.timeout,
- BUS_DATA_IN(5*32+31 downto 5*32) => bussed_tx.data,
- BUS_DATAREADY_IN(5) => bussed_tx.ack,
- BUS_WRITE_ACK_IN(5) => bussed_tx.ack,
- BUS_NO_MORE_DATA_IN(5) => bussed_tx.nack,
+ BUS_DATA_IN(5*32+31 downto 5*32) => bussed_tx.data,
+ BUS_DATAREADY_IN(5) => bussed_tx.ack,
+ BUS_WRITE_ACK_IN(5) => bussed_tx.ack,
+ BUS_NO_MORE_DATA_IN(5) => bussed_tx.nack,
BUS_UNKNOWN_ADDR_IN(5) => bussed_tx.unknown,
STAT_DEBUG => open
#############################################################################
## Unimportant Data Lines ##
#############################################################################
+BLOCK PATH FROM CLKNET "THE_TDC/edge_rising[*]";
+BLOCK NET "THE_TDC/hit_in_s*";
+
+USE SECONDARY NET "THE_TDC/coarse_cntr_reset";
+USE SECONDARY NET "THE_TDC/trg_win_end_tdc";
+
+
MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x;
+MULTICYCLE FROM CELL "THE_TDC/reset_tdc" 4x;
MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/ReferenceChannel/Channel200/ringBuffer_almost_full_sync*" 2x;
MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/ringBuffer_almost_full_sync*" 2x;
MULTICYCLE FROM CELL "THE_TDC/hit_edge[*]" TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/memory_ram" 2.000000 X ;
-#MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/data_out_reg[*]" 4 x;
-
-#MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "CLK_OSC_c" 4.000000 X ;
-
MULTICYCLE TO CELL "THE_TDC/edge_rising_100_r[*]" 4 x;
MULTICYCLE FROM CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/ringBuffer_almost_full_flag*" TO CELL "THE_TDC/TheReadout/data_out_r[*]" 2 x;
MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*" 4x;
MULTICYCLE TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/SimAdderNo.FC/FF*" 4x;
+MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/CHANNEL_200_DEBUG_OUT_1[*]" 4x;
+MULTICYCLE TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/CHANNEL_200_DEBUG_OUT_1[*]" 4x;
-BLOCK NET "THE_TDC/hit_in_s*";
+MULTICYCLE FROM CELL "THE_TDC/TheSlowcontrolBus/DATA_OUT*" 20 ns;
+MULTICYCLE TO CELL "THE_TDC/TheHitCounterBus/BUS_TX[data][*]" 20 ns;
+MULTICYCLE TO CELL "THE_TDC/TheStatusRegisterBus/BUS_TX[data][*]" 20 ns;
+MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/BUS_TX[data][*]" 20 ns;
+MULTICYCLE FROM CELL "THE_ENDPOINT/THE_ENDPOINT/*" TO CELL "THE_TDC/TheTriggerHandler/STATE_TW_CURRENT*" 10 ns;
MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ;
-USE SECONDARY NET "THE_TDC/coarse_cntr_reset";
-USE SECONDARY NET "THE_TDC/trg_win_end_tdc";
-
-
-
-# MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x;
-
-## Maybe effective
-
-# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X;
PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.62.Channels/Channel200/ff_array_en";
PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.63.Channels/Channel200/ff_array_en";
PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.64.Channels/Channel200/ff_array_en";
-
-
jspc29 / tdc.git / commitdiff