added sfp with external clock

diff --git a/media_interfaces/ecp2m_sfp/msg_file.log b/media_interfaces/ecp2m_sfp/msg_file.log
index 89d628bf2cb15d04802cffd89e38bc19d571404d..e9e3604e556b29086d1ec5c7eca145c1f477d95f 100644 (file)
--- a/media_interfaces/ecp2m_sfp/msg_file.log
+++ b/media_interfaces/ecp2m_sfp/msg_file.log
@@ -1,13 +1,13 @@
-    Module Name: serdes_sfp_3
+    Module Name: serdes_sfp_0_extclock
     Core Name: PCS
-    LPC file : serdes_sfp_3.lpc
-    Parameter File : serdes_sfp_3.pp
-    Command line: /opt/lattice/ispLEVER7.1/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_sfp_3.pp
+    LPC file : serdes_sfp_0_extclock.lpc
+    Parameter File : serdes_sfp_0_extclock.pp
+    Command line: /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_sfp_0_extclock.pp
     Return Value:
     
     
- Module PCS has been generated in /home/janm/jspc22/med_interface/ecp2m_sfp/. successfully!
+ Module PCS has been generated in /home/hadaq/jan/cvs/trbnet/media_interfaces/ecp2m_sfp/. successfully!
 
-/home/janm/.isplever_lin/ispcpld/bin/vhd2naf -tfi -mod serdes_sfp_3 -ext readme -out serdes_sfp_3 -p /opt/lattice/ispLEVER7.1/isptools/ispcpld/generic -tpl serdes_sfp_3.tft serdes_sfp_3.vhd
+/home/hadaq/.isplever_lin/ispcpld/bin/hdl2jhd -tfi -mod serdes_sfp_0_extclock -ext readme -out serdes_sfp_0_extclock -tpl serdes_sfp_0_extclock.tft serdes_sfp_0_extclock.vhd
 
 Done successfully!

diff --git a/media_interfaces/ecp2m_sfp/serdes_sfp_0_extclock.txt b/media_interfaces/ecp2m_sfp/serdes_sfp_0_extclock.txt
new file mode 100644 (file)
index 0000000..f66a84b
--- /dev/null
+++ b/media_interfaces/ecp2m_sfp/serdes_sfp_0_extclock.txt
@@ -0,0 +1,49 @@
+
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSC quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSC quad to the final design requirements.
+
+DEVICE_NAME "LFE2M20E"
+PROTOCOL    "G8B10B" 
+CH0_MODE    "SINGLE" 
+CH1_MODE    "DISABLE" 
+CH2_MODE    "DISABLE" 
+CH3_MODE    "DISABLE" 
+PLL_SRC     "REFCLK" 
+DATARANGE     "MEDHIGH" 
+CH0_CDR_SRC     "REFCLK" 
+CH0_DATA_WIDTH     "16" 
+CH0_REFCK_MULT     "20X" 
+#REFCLK_RATE     100
+#FPGAINTCLK_RATE     100
+CH0_TDRV_AMP     "0" 
+CH0_TX_PRE     "DISABLE" 
+CH0_RTERM_TX     "50" 
+CH0_RX_EQ     "DISABLE" 
+CH0_RTERM_RX     "50" 
+CH0_RX_DCC     "DC" 
+LOS_THRESHOLD     "0" 
+PLL_TERM     "50" 
+PLL_DCC     "DC" 
+PLL_LOL_SET     "0" 
+CH0_TX_SB     "NORMAL" 
+CH0_RX_SB     "NORMAL" 
+CH0_8B10B     "NORMAL" 
+COMMA_A     "1100000101" 
+COMMA_B     "0011111010" 
+COMMA_M     "1111111111" 
+CH0_COMMA_ALIGN     "AUTO" 
+CH0_CTC_BYP     "BYPASS" 
+CC_MATCH1     "0000000000" 
+CC_MATCH2     "0000000000" 
+CC_MATCH3     "0100011100" 
+CC_MATCH4     "0100011100" 
+CC_MATCH_MODE     "MATCH_4" 
+CC_MIN_IPG     "0" 
+CCHMARK     "4" 
+CCLMARK     "4" 
+OS_REFCK2CORE     "1"
+OS_PLLQCLKPORTS     "0"
+OS_INT_ALL     "0"
+

diff --git a/media_interfaces/ecp2m_sfp/serdes_sfp_0_extclock.vhd b/media_interfaces/ecp2m_sfp/serdes_sfp_0_extclock.vhd
new file mode 100644 (file)
index 0000000..394967a
--- /dev/null
+++ b/media_interfaces/ecp2m_sfp/serdes_sfp_0_extclock.vhd
@@ -0,0 +1,2186 @@
+
+
+--synopsys translate_off
+
+library pcsc_work;
+use pcsc_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSC is
+GENERIC(
+  CONFIG_FILE : String  := "serdes_sfp_0_extclock.txt"
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX             : in std_logic;
+  FFC_CK_CORE_TX             : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD             : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN             : in std_logic;
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_RX_Q_CLK_0             : out std_logic;
+  FF_RX_Q_CLK_1             : out std_logic;
+  FF_RX_Q_CLK_2             : out std_logic;
+  FF_RX_Q_CLK_3             : out std_logic;
+  FF_TX_F_CLK             : out std_logic;
+  FF_TX_H_CLK             : out std_logic;
+  FF_TX_Q_CLK             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  OOB_OUT_0             : out std_logic;
+  OOB_OUT_1             : out std_logic;
+  OOB_OUT_2             : out std_logic;
+  OOB_OUT_3             : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT             : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic
+);
+
+end PCSC;
+
+architecture PCSC_arch of PCSC is
+
+component PCSC_sim
+GENERIC(
+  CONFIG_FILE : String
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX             : in std_logic;
+  FFC_CK_CORE_TX             : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD             : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN             : in std_logic;
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_RX_Q_CLK_0             : out std_logic;
+  FF_RX_Q_CLK_1             : out std_logic;
+  FF_RX_Q_CLK_2             : out std_logic;
+  FF_RX_Q_CLK_3             : out std_logic;
+  FF_TX_F_CLK             : out std_logic;
+  FF_TX_H_CLK             : out std_logic;
+  FF_TX_Q_CLK             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  OOB_OUT_0             : out std_logic;
+  OOB_OUT_1             : out std_logic;
+  OOB_OUT_2             : out std_logic;
+  OOB_OUT_3             : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT             : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic
+);
+end component;
+
+begin
+
+PCSC_sim_inst : PCSC_sim
+generic map (
+  CONFIG_FILE => CONFIG_FILE)
+port map (
+  HDINN0 => HDINN0,
+  HDINN1 => HDINN1,
+  HDINN2 => HDINN2,
+  HDINN3 => HDINN3,
+  HDINP0 => HDINP0,
+  HDINP1 => HDINP1,
+  HDINP2 => HDINP2,
+  HDINP3 => HDINP3,
+  REFCLKN => REFCLKN,
+  REFCLKP => REFCLKP,
+  CIN11 => CIN11,
+  CIN10 => CIN10,
+  CIN9 => CIN9,
+  CIN8 => CIN8,
+  CIN7 => CIN7,
+  CIN6 => CIN6,
+  CIN5 => CIN5,
+  CIN4 => CIN4,
+  CIN3 => CIN3,
+  CIN2 => CIN2,
+  CIN1 => CIN1,
+  CIN0 => CIN0,
+  CYAWSTN => CYAWSTN,
+  FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+  FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+  FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+  FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+  FF_RXI_CLK_3 => FF_RXI_CLK_3,
+  FF_RXI_CLK_2 => FF_RXI_CLK_2,
+  FF_RXI_CLK_1 => FF_RXI_CLK_1,
+  FF_RXI_CLK_0 => FF_RXI_CLK_0,
+
+  FF_TX_D_0_0 => FF_TX_D_0_0,
+  FF_TX_D_0_1 => FF_TX_D_0_1,
+  FF_TX_D_0_2 => FF_TX_D_0_2,
+  FF_TX_D_0_3 => FF_TX_D_0_3,
+  FF_TX_D_0_4 => FF_TX_D_0_4,
+  FF_TX_D_0_5 => FF_TX_D_0_5,
+  FF_TX_D_0_6 => FF_TX_D_0_6,
+  FF_TX_D_0_7 => FF_TX_D_0_7,
+  FF_TX_D_0_8 => FF_TX_D_0_8,
+  FF_TX_D_0_9 => FF_TX_D_0_9,
+  FF_TX_D_0_10 => FF_TX_D_0_10,
+  FF_TX_D_0_11 => FF_TX_D_0_11,
+  FF_TX_D_0_12 => FF_TX_D_0_12,
+  FF_TX_D_0_13 => FF_TX_D_0_13,
+  FF_TX_D_0_14 => FF_TX_D_0_14,
+  FF_TX_D_0_15 => FF_TX_D_0_15,
+  FF_TX_D_0_16 => FF_TX_D_0_16,
+  FF_TX_D_0_17 => FF_TX_D_0_17,
+  FF_TX_D_0_18 => FF_TX_D_0_18,
+  FF_TX_D_0_19 => FF_TX_D_0_19,
+  FF_TX_D_0_20 => FF_TX_D_0_20,
+  FF_TX_D_0_21 => FF_TX_D_0_21,
+  FF_TX_D_0_22 => FF_TX_D_0_22,
+  FF_TX_D_0_23 => FF_TX_D_0_23,
+  FF_TX_D_1_0 => FF_TX_D_1_0,
+  FF_TX_D_1_1 => FF_TX_D_1_1,
+  FF_TX_D_1_2 => FF_TX_D_1_2,
+  FF_TX_D_1_3 => FF_TX_D_1_3,
+  FF_TX_D_1_4 => FF_TX_D_1_4,
+  FF_TX_D_1_5 => FF_TX_D_1_5,
+  FF_TX_D_1_6 => FF_TX_D_1_6,
+  FF_TX_D_1_7 => FF_TX_D_1_7,
+  FF_TX_D_1_8 => FF_TX_D_1_8,
+  FF_TX_D_1_9 => FF_TX_D_1_9,
+  FF_TX_D_1_10 => FF_TX_D_1_10,
+  FF_TX_D_1_11 => FF_TX_D_1_11,
+  FF_TX_D_1_12 => FF_TX_D_1_12,
+  FF_TX_D_1_13 => FF_TX_D_1_13,
+  FF_TX_D_1_14 => FF_TX_D_1_14,
+  FF_TX_D_1_15 => FF_TX_D_1_15,
+  FF_TX_D_1_16 => FF_TX_D_1_16,
+  FF_TX_D_1_17 => FF_TX_D_1_17,
+  FF_TX_D_1_18 => FF_TX_D_1_18,
+  FF_TX_D_1_19 => FF_TX_D_1_19,
+  FF_TX_D_1_20 => FF_TX_D_1_20,
+  FF_TX_D_1_21 => FF_TX_D_1_21,
+  FF_TX_D_1_22 => FF_TX_D_1_22,
+  FF_TX_D_1_23 => FF_TX_D_1_23,
+  FF_TX_D_2_0 => FF_TX_D_2_0,
+  FF_TX_D_2_1 => FF_TX_D_2_1,
+  FF_TX_D_2_2 => FF_TX_D_2_2,
+  FF_TX_D_2_3 => FF_TX_D_2_3,
+  FF_TX_D_2_4 => FF_TX_D_2_4,
+  FF_TX_D_2_5 => FF_TX_D_2_5,
+  FF_TX_D_2_6 => FF_TX_D_2_6,
+  FF_TX_D_2_7 => FF_TX_D_2_7,
+  FF_TX_D_2_8 => FF_TX_D_2_8,
+  FF_TX_D_2_9 => FF_TX_D_2_9,
+  FF_TX_D_2_10 => FF_TX_D_2_10,
+  FF_TX_D_2_11 => FF_TX_D_2_11,
+  FF_TX_D_2_12 => FF_TX_D_2_12,
+  FF_TX_D_2_13 => FF_TX_D_2_13,
+  FF_TX_D_2_14 => FF_TX_D_2_14,
+  FF_TX_D_2_15 => FF_TX_D_2_15,
+  FF_TX_D_2_16 => FF_TX_D_2_16,
+  FF_TX_D_2_17 => FF_TX_D_2_17,
+  FF_TX_D_2_18 => FF_TX_D_2_18,
+  FF_TX_D_2_19 => FF_TX_D_2_19,
+  FF_TX_D_2_20 => FF_TX_D_2_20,
+  FF_TX_D_2_21 => FF_TX_D_2_21,
+  FF_TX_D_2_22 => FF_TX_D_2_22,
+  FF_TX_D_2_23 => FF_TX_D_2_23,
+  FF_TX_D_3_0 => FF_TX_D_3_0,
+  FF_TX_D_3_1 => FF_TX_D_3_1,
+  FF_TX_D_3_2 => FF_TX_D_3_2,
+  FF_TX_D_3_3 => FF_TX_D_3_3,
+  FF_TX_D_3_4 => FF_TX_D_3_4,
+  FF_TX_D_3_5 => FF_TX_D_3_5,
+  FF_TX_D_3_6 => FF_TX_D_3_6,
+  FF_TX_D_3_7 => FF_TX_D_3_7,
+  FF_TX_D_3_8 => FF_TX_D_3_8,
+  FF_TX_D_3_9 => FF_TX_D_3_9,
+  FF_TX_D_3_10 => FF_TX_D_3_10,
+  FF_TX_D_3_11 => FF_TX_D_3_11,
+  FF_TX_D_3_12 => FF_TX_D_3_12,
+  FF_TX_D_3_13 => FF_TX_D_3_13,
+  FF_TX_D_3_14 => FF_TX_D_3_14,
+  FF_TX_D_3_15 => FF_TX_D_3_15,
+  FF_TX_D_3_16 => FF_TX_D_3_16,
+  FF_TX_D_3_17 => FF_TX_D_3_17,
+  FF_TX_D_3_18 => FF_TX_D_3_18,
+  FF_TX_D_3_19 => FF_TX_D_3_19,
+  FF_TX_D_3_20 => FF_TX_D_3_20,
+  FF_TX_D_3_21 => FF_TX_D_3_21,
+  FF_TX_D_3_22 => FF_TX_D_3_22,
+  FF_TX_D_3_23 => FF_TX_D_3_23,
+  FF_TXI_CLK_0 => FF_TXI_CLK_0,
+  FF_TXI_CLK_1 => FF_TXI_CLK_1,
+  FF_TXI_CLK_2 => FF_TXI_CLK_2,
+  FF_TXI_CLK_3 => FF_TXI_CLK_3,
+  FFC_CK_CORE_RX => FFC_CK_CORE_RX,
+  FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+  FFC_EI_EN_0 => FFC_EI_EN_0,
+  FFC_EI_EN_1 => FFC_EI_EN_1,
+  FFC_EI_EN_2 => FFC_EI_EN_2,
+  FFC_EI_EN_3 => FFC_EI_EN_3,
+  FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+  FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+  FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+  FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+  FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+  FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+  FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+  FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+  FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+  FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+  FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+  FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+  FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+  FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+  FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+  FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+  FFC_MACRO_RST => FFC_MACRO_RST,
+  FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+  FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+  FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+  FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+  FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+  FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+  FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+  FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+  FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+  FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+  FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+  FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+  FFC_QUAD_RST => FFC_QUAD_RST,
+  FFC_RRST_0 => FFC_RRST_0,
+  FFC_RRST_1 => FFC_RRST_1,
+  FFC_RRST_2 => FFC_RRST_2,
+  FFC_RRST_3 => FFC_RRST_3,
+  FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+  FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+  FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+  FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+  FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+  FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+  FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+  FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+  FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+  FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+  FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+  FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+  FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+  FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+  FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+  FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+  FFC_TRST => FFC_TRST,
+  FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+  FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+  FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+  FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+  SCIADDR0 => SCIADDR0,
+  SCIADDR1 => SCIADDR1,
+  SCIADDR2 => SCIADDR2,
+  SCIADDR3 => SCIADDR3,
+  SCIADDR4 => SCIADDR4,
+  SCIADDR5 => SCIADDR5,
+  SCIENAUX => SCIENAUX,
+  SCIENCH0 => SCIENCH0,
+  SCIENCH1 => SCIENCH1,
+  SCIENCH2 => SCIENCH2,
+  SCIENCH3 => SCIENCH3,
+  SCIRD => SCIRD,
+  SCISELAUX => SCISELAUX,
+  SCISELCH0 => SCISELCH0,
+  SCISELCH1 => SCISELCH1,
+  SCISELCH2 => SCISELCH2,
+  SCISELCH3 => SCISELCH3,
+  SCIWDATA0 => SCIWDATA0,
+  SCIWDATA1 => SCIWDATA1,
+  SCIWDATA2 => SCIWDATA2,
+  SCIWDATA3 => SCIWDATA3,
+  SCIWDATA4 => SCIWDATA4,
+  SCIWDATA5 => SCIWDATA5,
+  SCIWDATA6 => SCIWDATA6,
+  SCIWDATA7 => SCIWDATA7,
+  SCIWSTN => SCIWSTN,
+  HDOUTN0 => HDOUTN0,
+  HDOUTN1 => HDOUTN1,
+  HDOUTN2 => HDOUTN2,
+  HDOUTN3 => HDOUTN3,
+  HDOUTP0 => HDOUTP0,
+  HDOUTP1 => HDOUTP1,
+  HDOUTP2 => HDOUTP2,
+  HDOUTP3 => HDOUTP3,
+  COUT19 => COUT19,
+  COUT18 => COUT18,
+  COUT17 => COUT17,
+  COUT16 => COUT16,
+  COUT15 => COUT15,
+  COUT14 => COUT14,
+  COUT13 => COUT13,
+  COUT12 => COUT12,
+  COUT11 => COUT11,
+  COUT10 => COUT10,
+  COUT9 => COUT9,
+  COUT8 => COUT8,
+  COUT7 => COUT7,
+  COUT6 => COUT6,
+  COUT5 => COUT5,
+  COUT4 => COUT4,
+  COUT3 => COUT3,
+  COUT2 => COUT2,
+  COUT1 => COUT1,
+  COUT0 => COUT0,
+  FF_RX_D_0_0 => FF_RX_D_0_0,
+  FF_RX_D_0_1 => FF_RX_D_0_1,
+  FF_RX_D_0_2 => FF_RX_D_0_2,
+  FF_RX_D_0_3 => FF_RX_D_0_3,
+  FF_RX_D_0_4 => FF_RX_D_0_4,
+  FF_RX_D_0_5 => FF_RX_D_0_5,
+  FF_RX_D_0_6 => FF_RX_D_0_6,
+  FF_RX_D_0_7 => FF_RX_D_0_7,
+  FF_RX_D_0_8 => FF_RX_D_0_8,
+  FF_RX_D_0_9 => FF_RX_D_0_9,
+  FF_RX_D_0_10 => FF_RX_D_0_10,
+  FF_RX_D_0_11 => FF_RX_D_0_11,
+  FF_RX_D_0_12 => FF_RX_D_0_12,
+  FF_RX_D_0_13 => FF_RX_D_0_13,
+  FF_RX_D_0_14 => FF_RX_D_0_14,
+  FF_RX_D_0_15 => FF_RX_D_0_15,
+  FF_RX_D_0_16 => FF_RX_D_0_16,
+  FF_RX_D_0_17 => FF_RX_D_0_17,
+  FF_RX_D_0_18 => FF_RX_D_0_18,
+  FF_RX_D_0_19 => FF_RX_D_0_19,
+  FF_RX_D_0_20 => FF_RX_D_0_20,
+  FF_RX_D_0_21 => FF_RX_D_0_21,
+  FF_RX_D_0_22 => FF_RX_D_0_22,
+  FF_RX_D_0_23 => FF_RX_D_0_23,
+  FF_RX_D_1_0 => FF_RX_D_1_0,
+  FF_RX_D_1_1 => FF_RX_D_1_1,
+  FF_RX_D_1_2 => FF_RX_D_1_2,
+  FF_RX_D_1_3 => FF_RX_D_1_3,
+  FF_RX_D_1_4 => FF_RX_D_1_4,
+  FF_RX_D_1_5 => FF_RX_D_1_5,
+  FF_RX_D_1_6 => FF_RX_D_1_6,
+  FF_RX_D_1_7 => FF_RX_D_1_7,
+  FF_RX_D_1_8 => FF_RX_D_1_8,
+  FF_RX_D_1_9 => FF_RX_D_1_9,
+  FF_RX_D_1_10 => FF_RX_D_1_10,
+  FF_RX_D_1_11 => FF_RX_D_1_11,
+  FF_RX_D_1_12 => FF_RX_D_1_12,
+  FF_RX_D_1_13 => FF_RX_D_1_13,
+  FF_RX_D_1_14 => FF_RX_D_1_14,
+  FF_RX_D_1_15 => FF_RX_D_1_15,
+  FF_RX_D_1_16 => FF_RX_D_1_16,
+  FF_RX_D_1_17 => FF_RX_D_1_17,
+  FF_RX_D_1_18 => FF_RX_D_1_18,
+  FF_RX_D_1_19 => FF_RX_D_1_19,
+  FF_RX_D_1_20 => FF_RX_D_1_20,
+  FF_RX_D_1_21 => FF_RX_D_1_21,
+  FF_RX_D_1_22 => FF_RX_D_1_22,
+  FF_RX_D_1_23 => FF_RX_D_1_23,
+  FF_RX_D_2_0 => FF_RX_D_2_0,
+  FF_RX_D_2_1 => FF_RX_D_2_1,
+  FF_RX_D_2_2 => FF_RX_D_2_2,
+  FF_RX_D_2_3 => FF_RX_D_2_3,
+  FF_RX_D_2_4 => FF_RX_D_2_4,
+  FF_RX_D_2_5 => FF_RX_D_2_5,
+  FF_RX_D_2_6 => FF_RX_D_2_6,
+  FF_RX_D_2_7 => FF_RX_D_2_7,
+  FF_RX_D_2_8 => FF_RX_D_2_8,
+  FF_RX_D_2_9 => FF_RX_D_2_9,
+  FF_RX_D_2_10 => FF_RX_D_2_10,
+  FF_RX_D_2_11 => FF_RX_D_2_11,
+  FF_RX_D_2_12 => FF_RX_D_2_12,
+  FF_RX_D_2_13 => FF_RX_D_2_13,
+  FF_RX_D_2_14 => FF_RX_D_2_14,
+  FF_RX_D_2_15 => FF_RX_D_2_15,
+  FF_RX_D_2_16 => FF_RX_D_2_16,
+  FF_RX_D_2_17 => FF_RX_D_2_17,
+  FF_RX_D_2_18 => FF_RX_D_2_18,
+  FF_RX_D_2_19 => FF_RX_D_2_19,
+  FF_RX_D_2_20 => FF_RX_D_2_20,
+  FF_RX_D_2_21 => FF_RX_D_2_21,
+  FF_RX_D_2_22 => FF_RX_D_2_22,
+  FF_RX_D_2_23 => FF_RX_D_2_23,
+  FF_RX_D_3_0 => FF_RX_D_3_0,
+  FF_RX_D_3_1 => FF_RX_D_3_1,
+  FF_RX_D_3_2 => FF_RX_D_3_2,
+  FF_RX_D_3_3 => FF_RX_D_3_3,
+  FF_RX_D_3_4 => FF_RX_D_3_4,
+  FF_RX_D_3_5 => FF_RX_D_3_5,
+  FF_RX_D_3_6 => FF_RX_D_3_6,
+  FF_RX_D_3_7 => FF_RX_D_3_7,
+  FF_RX_D_3_8 => FF_RX_D_3_8,
+  FF_RX_D_3_9 => FF_RX_D_3_9,
+  FF_RX_D_3_10 => FF_RX_D_3_10,
+  FF_RX_D_3_11 => FF_RX_D_3_11,
+  FF_RX_D_3_12 => FF_RX_D_3_12,
+  FF_RX_D_3_13 => FF_RX_D_3_13,
+  FF_RX_D_3_14 => FF_RX_D_3_14,
+  FF_RX_D_3_15 => FF_RX_D_3_15,
+  FF_RX_D_3_16 => FF_RX_D_3_16,
+  FF_RX_D_3_17 => FF_RX_D_3_17,
+  FF_RX_D_3_18 => FF_RX_D_3_18,
+  FF_RX_D_3_19 => FF_RX_D_3_19,
+  FF_RX_D_3_20 => FF_RX_D_3_20,
+  FF_RX_D_3_21 => FF_RX_D_3_21,
+  FF_RX_D_3_22 => FF_RX_D_3_22,
+  FF_RX_D_3_23 => FF_RX_D_3_23,
+  FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+  FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+  FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+  FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+  FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+  FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+  FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+  FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+  FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,
+  FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,
+  FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,
+  FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,
+  FF_TX_F_CLK => FF_TX_F_CLK,
+  FF_TX_H_CLK => FF_TX_H_CLK,
+  FF_TX_Q_CLK => FF_TX_Q_CLK,
+  FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+  FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+  FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+  FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+  FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+  FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+  FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+  FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+  FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+  FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+  FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+  FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+  FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+  FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+  FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+  FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+  FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+  FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+  FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+  FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+  FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+  FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+  FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+  FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+  FFS_PLOL => FFS_PLOL,
+  FFS_RLOL_0 => FFS_RLOL_0,
+  FFS_RLOL_1 => FFS_RLOL_1,
+  FFS_RLOL_2 => FFS_RLOL_2,
+  FFS_RLOL_3 => FFS_RLOL_3,
+  FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+  FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+  FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+  FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+  FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+  FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+  FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+  FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+  OOB_OUT_0 => OOB_OUT_0,
+  OOB_OUT_1 => OOB_OUT_1,
+  OOB_OUT_2 => OOB_OUT_2,
+  OOB_OUT_3 => OOB_OUT_3,
+  REFCK2CORE => REFCK2CORE,
+  SCIINT => SCIINT,
+  SCIRDATA0 => SCIRDATA0,
+  SCIRDATA1 => SCIRDATA1,
+  SCIRDATA2 => SCIRDATA2,
+  SCIRDATA3 => SCIRDATA3,
+  SCIRDATA4 => SCIRDATA4,
+  SCIRDATA5 => SCIRDATA5,
+  SCIRDATA6 => SCIRDATA6,
+  SCIRDATA7 => SCIRDATA7
+   );
+
+end PCSC_arch;
+
+--synopsys translate_on
+
+--synopsys translate_off
+library ECP2;
+use ECP2.components.all;
+--synopsys translate_on
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity serdes_sfp_0_extclock is
+   GENERIC (USER_CONFIG_FILE    :  String := "serdes_sfp_0_extclock.txt");
+ port (
+   refclkp, refclkn : in std_logic;
+   hdinp0, hdinn0 : in std_logic;
+   hdoutp0, hdoutn0 : out std_logic;
+   ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;
+   ff_txdata_ch0 : in std_logic_vector (15 downto 0);
+   ff_rxdata_ch0 : out std_logic_vector (15 downto 0);
+   ff_tx_k_cntrl_ch0 : in std_logic_vector (1 downto 0);
+   ff_rx_k_cntrl_ch0 : out std_logic_vector (1 downto 0);
+   ff_rxfullclk_ch0 : out std_logic;
+   ff_rxhalfclk_ch0 : out std_logic;
+   ff_force_disp_ch0 : in std_logic_vector (1 downto 0);
+   ff_disp_sel_ch0 : in std_logic_vector (1 downto 0);
+   ff_disp_err_ch0, ff_cv_ch0 : out std_logic_vector (1 downto 0);
+   ffc_rrst_ch0 : in std_logic;
+   ffc_lane_tx_rst_ch0 : in std_logic;
+   ffc_lane_rx_rst_ch0 : in std_logic;
+   ffc_txpwdnb_ch0 : in std_logic;
+   ffc_rxpwdnb_ch0 : in std_logic;
+   ffs_rlos_lo_ch0 : out std_logic;
+   ffs_ls_sync_status_ch0 : out std_logic;
+   ffs_cc_underrun_ch0 : out std_logic;
+   ffs_cc_overrun_ch0 : out std_logic;
+   ffs_txfbfifo_error_ch0 : out std_logic;
+   ffs_rxfbfifo_error_ch0 : out std_logic;
+   ffs_rlol_ch0 : out std_logic;
+   oob_out_ch0 : out std_logic;
+   ffc_macro_rst : in std_logic;
+   ffc_quad_rst : in std_logic;
+   ffc_trst : in std_logic;
+   ff_txfullclk : out std_logic;
+   ff_txhalfclk : out std_logic;
+   refck2core : out std_logic;
+   ffs_plol : out std_logic);
+
+end serdes_sfp_0_extclock;
+
+architecture serdes_sfp_0_extclock_arch of serdes_sfp_0_extclock is
+
+component VLO
+port (
+   Z : out std_logic);
+end component;
+
+component VHI
+port (
+   Z : out std_logic);
+end component;
+component PCSC
+--synopsys translate_off
+GENERIC(
+  CONFIG_FILE : String
+  );
+--synopsys translate_on
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX             : in std_logic;
+  FFC_CK_CORE_TX             : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD             : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN             : in std_logic;
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_RX_Q_CLK_0             : out std_logic;
+  FF_RX_Q_CLK_1             : out std_logic;
+  FF_RX_Q_CLK_2             : out std_logic;
+  FF_RX_Q_CLK_3             : out std_logic;
+  FF_TX_F_CLK             : out std_logic;
+  FF_TX_H_CLK             : out std_logic;
+  FF_TX_Q_CLK             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  OOB_OUT_0             : out std_logic;
+  OOB_OUT_1             : out std_logic;
+  OOB_OUT_2             : out std_logic;
+  OOB_OUT_3             : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT             : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic
+);
+end component;
+   attribute IS_ASB: string;
+   attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";
+   attribute CONFIG_FILE: string;
+   attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;
+   attribute black_box_pad_pin: string;
+   attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal fpsc_vlo : std_logic := '0';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+
+-- pcs_quad instance
+PCSC_INST : PCSC
+--synopsys translate_off
+  generic map (CONFIG_FILE => USER_CONFIG_FILE)
+--synopsys translate_on
+port map  (
+  FFC_CK_CORE_TX => fpsc_vlo,
+  FFC_CK_CORE_RX => fpsc_vlo,
+  REFCLKP => refclkp,
+  REFCLKN => refclkn,
+  HDINP0 => hdinp0,
+  HDINN0 => hdinn0,
+  HDOUTP0 => hdoutp0,
+  HDOUTN0 => hdoutn0,
+  SCISELCH0 => fpsc_vlo,
+  SCIENCH0 => fpsc_vlo,
+  FF_RXI_CLK_0 => ff_rxiclk_ch0,
+  FF_TXI_CLK_0 => ff_txiclk_ch0,
+  FF_EBRD_CLK_0 => ff_ebrd_clk_0,
+  FF_RX_F_CLK_0 => ff_rxfullclk_ch0,
+  FF_RX_H_CLK_0 => ff_rxhalfclk_ch0,
+  FF_RX_Q_CLK_0 => open,
+  FF_TX_D_0_0 => ff_txdata_ch0(0),
+  FF_TX_D_0_1 => ff_txdata_ch0(1),
+  FF_TX_D_0_2 => ff_txdata_ch0(2),
+  FF_TX_D_0_3 => ff_txdata_ch0(3),
+  FF_TX_D_0_4 => ff_txdata_ch0(4),
+  FF_TX_D_0_5 => ff_txdata_ch0(5),
+  FF_TX_D_0_6 => ff_txdata_ch0(6),
+  FF_TX_D_0_7 => ff_txdata_ch0(7),
+  FF_TX_D_0_8 => ff_tx_k_cntrl_ch0(0),
+  FF_TX_D_0_9 => ff_force_disp_ch0(0),
+  FF_TX_D_0_10 => ff_disp_sel_ch0(0),
+  FF_TX_D_0_11 => fpsc_vlo,
+  FF_TX_D_0_12 => ff_txdata_ch0(8),
+  FF_TX_D_0_13 => ff_txdata_ch0(9),
+  FF_TX_D_0_14 => ff_txdata_ch0(10),
+  FF_TX_D_0_15 => ff_txdata_ch0(11),
+  FF_TX_D_0_16 => ff_txdata_ch0(12),
+  FF_TX_D_0_17 => ff_txdata_ch0(13),
+  FF_TX_D_0_18 => ff_txdata_ch0(14),
+  FF_TX_D_0_19 => ff_txdata_ch0(15),
+  FF_TX_D_0_20 => ff_tx_k_cntrl_ch0(1),
+  FF_TX_D_0_21 => ff_force_disp_ch0(1),
+  FF_TX_D_0_22 => ff_disp_sel_ch0(1),
+  FF_TX_D_0_23 => fpsc_vlo,
+  FF_RX_D_0_0 => ff_rxdata_ch0(0),
+  FF_RX_D_0_1 => ff_rxdata_ch0(1),
+  FF_RX_D_0_2 => ff_rxdata_ch0(2),
+  FF_RX_D_0_3 => ff_rxdata_ch0(3),
+  FF_RX_D_0_4 => ff_rxdata_ch0(4),
+  FF_RX_D_0_5 => ff_rxdata_ch0(5),
+  FF_RX_D_0_6 => ff_rxdata_ch0(6),
+  FF_RX_D_0_7 => ff_rxdata_ch0(7),
+  FF_RX_D_0_8 => ff_rx_k_cntrl_ch0(0),
+  FF_RX_D_0_9 => ff_disp_err_ch0(0),
+  FF_RX_D_0_10 => ff_cv_ch0(0),
+  FF_RX_D_0_11 => open,
+  FF_RX_D_0_12 => ff_rxdata_ch0(8),
+  FF_RX_D_0_13 => ff_rxdata_ch0(9),
+  FF_RX_D_0_14 => ff_rxdata_ch0(10),
+  FF_RX_D_0_15 => ff_rxdata_ch0(11),
+  FF_RX_D_0_16 => ff_rxdata_ch0(12),
+  FF_RX_D_0_17 => ff_rxdata_ch0(13),
+  FF_RX_D_0_18 => ff_rxdata_ch0(14),
+  FF_RX_D_0_19 => ff_rxdata_ch0(15),
+  FF_RX_D_0_20 => ff_rx_k_cntrl_ch0(1),
+  FF_RX_D_0_21 => ff_disp_err_ch0(1),
+  FF_RX_D_0_22 => ff_cv_ch0(1),
+  FF_RX_D_0_23 => open,
+  FFC_RRST_0 => ffc_rrst_ch0,
+  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+  FFC_PFIFO_CLR_0 => fpsc_vlo,
+  FFC_FB_LOOPBACK_0 => fpsc_vlo,
+  FFC_SB_INV_RX_0 => fpsc_vlo,
+  FFC_PCIE_CT_0 => fpsc_vlo,
+  FFC_PCI_DET_EN_0 => fpsc_vlo,
+  FFS_PCIE_DONE_0 => open,
+  FFS_PCIE_CON_0 => open,
+  FFC_EI_EN_0 => fpsc_vlo,
+  FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0,
+  FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0,
+  FFC_TXPWDNB_0 => ffc_txpwdnb_ch0,
+  FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0,
+  FFS_RLOS_LO_0 => ffs_rlos_lo_ch0,
+  FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0,
+  FFS_CC_UNDERRUN_0 => ffs_cc_underrun_ch0,
+  FFS_CC_OVERRUN_0 => ffs_cc_overrun_ch0,
+  FFS_RXFBFIFO_ERROR_0 => ffs_rxfbfifo_error_ch0,
+  FFS_TXFBFIFO_ERROR_0 => ffs_txfbfifo_error_ch0,
+  FFS_RLOL_0 => ffs_rlol_ch0,
+  OOB_OUT_0 => oob_out_ch0,
+  HDINP1 => fpsc_vlo,
+  HDINN1 => fpsc_vlo,
+  HDOUTP1 => open,
+  HDOUTN1 => open,
+  SCISELCH1 => fpsc_vlo,
+  SCIENCH1 => fpsc_vlo,
+  FF_RXI_CLK_1 => fpsc_vlo,
+  FF_TXI_CLK_1 => fpsc_vlo,
+  FF_EBRD_CLK_1 => fpsc_vlo,
+  FF_RX_F_CLK_1 => open,
+  FF_RX_H_CLK_1 => open,
+  FF_RX_Q_CLK_1 => open,
+  FF_TX_D_1_0 => fpsc_vlo,
+  FF_TX_D_1_1 => fpsc_vlo,
+  FF_TX_D_1_2 => fpsc_vlo,
+  FF_TX_D_1_3 => fpsc_vlo,
+  FF_TX_D_1_4 => fpsc_vlo,
+  FF_TX_D_1_5 => fpsc_vlo,
+  FF_TX_D_1_6 => fpsc_vlo,
+  FF_TX_D_1_7 => fpsc_vlo,
+  FF_TX_D_1_8 => fpsc_vlo,
+  FF_TX_D_1_9 => fpsc_vlo,
+  FF_TX_D_1_10 => fpsc_vlo,
+  FF_TX_D_1_11 => fpsc_vlo,
+  FF_TX_D_1_12 => fpsc_vlo,
+  FF_TX_D_1_13 => fpsc_vlo,
+  FF_TX_D_1_14 => fpsc_vlo,
+  FF_TX_D_1_15 => fpsc_vlo,
+  FF_TX_D_1_16 => fpsc_vlo,
+  FF_TX_D_1_17 => fpsc_vlo,
+  FF_TX_D_1_18 => fpsc_vlo,
+  FF_TX_D_1_19 => fpsc_vlo,
+  FF_TX_D_1_20 => fpsc_vlo,
+  FF_TX_D_1_21 => fpsc_vlo,
+  FF_TX_D_1_22 => fpsc_vlo,
+  FF_TX_D_1_23 => fpsc_vlo,
+  FF_RX_D_1_0 => open,
+  FF_RX_D_1_1 => open,
+  FF_RX_D_1_2 => open,
+  FF_RX_D_1_3 => open,
+  FF_RX_D_1_4 => open,
+  FF_RX_D_1_5 => open,
+  FF_RX_D_1_6 => open,
+  FF_RX_D_1_7 => open,
+  FF_RX_D_1_8 => open,
+  FF_RX_D_1_9 => open,
+  FF_RX_D_1_10 => open,
+  FF_RX_D_1_11 => open,
+  FF_RX_D_1_12 => open,
+  FF_RX_D_1_13 => open,
+  FF_RX_D_1_14 => open,
+  FF_RX_D_1_15 => open,
+  FF_RX_D_1_16 => open,
+  FF_RX_D_1_17 => open,
+  FF_RX_D_1_18 => open,
+  FF_RX_D_1_19 => open,
+  FF_RX_D_1_20 => open,
+  FF_RX_D_1_21 => open,
+  FF_RX_D_1_22 => open,
+  FF_RX_D_1_23 => open,
+  FFC_RRST_1 => fpsc_vlo,
+  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_1 => fpsc_vlo,
+  FFC_SB_INV_RX_1 => fpsc_vlo,
+  FFC_PFIFO_CLR_1 => fpsc_vlo,
+  FFC_PCIE_CT_1 => fpsc_vlo,
+  FFC_PCI_DET_EN_1 => fpsc_vlo,
+  FFC_FB_LOOPBACK_1 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+  FFC_EI_EN_1 => fpsc_vlo,
+  FFC_LANE_TX_RST_1 => fpsc_vlo,
+  FFC_LANE_RX_RST_1 => fpsc_vlo,
+  FFC_TXPWDNB_1 => fpsc_vlo,
+  FFC_RXPWDNB_1 => fpsc_vlo,
+  FFS_RLOS_LO_1 => open,
+  FFS_PCIE_DONE_1 => open,
+  FFS_PCIE_CON_1 => open,
+  FFS_LS_SYNC_STATUS_1 => open,
+  FFS_CC_UNDERRUN_1 => open,
+  FFS_CC_OVERRUN_1 => open,
+  FFS_RLOL_1 => open,
+  FFS_RXFBFIFO_ERROR_1 => open,
+  FFS_TXFBFIFO_ERROR_1 => open,
+  OOB_OUT_1 => open,
+  HDINP2 => fpsc_vlo,
+  HDINN2 => fpsc_vlo,
+  HDOUTP2 => open,
+  HDOUTN2 => open,
+  SCISELCH2 => fpsc_vlo,
+  SCIENCH2 => fpsc_vlo,
+  FF_RXI_CLK_2 => fpsc_vlo,
+  FF_TXI_CLK_2 => fpsc_vlo,
+  FF_EBRD_CLK_2 => fpsc_vlo,
+  FF_RX_F_CLK_2 => open,
+  FF_RX_H_CLK_2 => open,
+  FF_RX_Q_CLK_2 => open,
+  FF_TX_D_2_0 => fpsc_vlo,
+  FF_TX_D_2_1 => fpsc_vlo,
+  FF_TX_D_2_2 => fpsc_vlo,
+  FF_TX_D_2_3 => fpsc_vlo,
+  FF_TX_D_2_4 => fpsc_vlo,
+  FF_TX_D_2_5 => fpsc_vlo,
+  FF_TX_D_2_6 => fpsc_vlo,
+  FF_TX_D_2_7 => fpsc_vlo,
+  FF_TX_D_2_8 => fpsc_vlo,
+  FF_TX_D_2_9 => fpsc_vlo,
+  FF_TX_D_2_10 => fpsc_vlo,
+  FF_TX_D_2_11 => fpsc_vlo,
+  FF_TX_D_2_12 => fpsc_vlo,
+  FF_TX_D_2_13 => fpsc_vlo,
+  FF_TX_D_2_14 => fpsc_vlo,
+  FF_TX_D_2_15 => fpsc_vlo,
+  FF_TX_D_2_16 => fpsc_vlo,
+  FF_TX_D_2_17 => fpsc_vlo,
+  FF_TX_D_2_18 => fpsc_vlo,
+  FF_TX_D_2_19 => fpsc_vlo,
+  FF_TX_D_2_20 => fpsc_vlo,
+  FF_TX_D_2_21 => fpsc_vlo,
+  FF_TX_D_2_22 => fpsc_vlo,
+  FF_TX_D_2_23 => fpsc_vlo,
+  FF_RX_D_2_0 => open,
+  FF_RX_D_2_1 => open,
+  FF_RX_D_2_2 => open,
+  FF_RX_D_2_3 => open,
+  FF_RX_D_2_4 => open,
+  FF_RX_D_2_5 => open,
+  FF_RX_D_2_6 => open,
+  FF_RX_D_2_7 => open,
+  FF_RX_D_2_8 => open,
+  FF_RX_D_2_9 => open,
+  FF_RX_D_2_10 => open,
+  FF_RX_D_2_11 => open,
+  FF_RX_D_2_12 => open,
+  FF_RX_D_2_13 => open,
+  FF_RX_D_2_14 => open,
+  FF_RX_D_2_15 => open,
+  FF_RX_D_2_16 => open,
+  FF_RX_D_2_17 => open,
+  FF_RX_D_2_18 => open,
+  FF_RX_D_2_19 => open,
+  FF_RX_D_2_20 => open,
+  FF_RX_D_2_21 => open,
+  FF_RX_D_2_22 => open,
+  FF_RX_D_2_23 => open,
+  FFC_RRST_2 => fpsc_vlo,
+  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+  FFC_SB_INV_RX_2 => fpsc_vlo,
+  FFC_PFIFO_CLR_2 => fpsc_vlo,
+  FFC_PCIE_CT_2 => fpsc_vlo,
+  FFC_PCI_DET_EN_2 => fpsc_vlo,
+  FFC_FB_LOOPBACK_2 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+  FFC_EI_EN_2 => fpsc_vlo,
+  FFC_LANE_TX_RST_2 => fpsc_vlo,
+  FFC_LANE_RX_RST_2 => fpsc_vlo,
+  FFC_TXPWDNB_2 => fpsc_vlo,
+  FFC_RXPWDNB_2 => fpsc_vlo,
+  FFS_RLOS_LO_2 => open,
+  FFS_PCIE_DONE_2 => open,
+  FFS_PCIE_CON_2 => open,
+  FFS_LS_SYNC_STATUS_2 => open,
+  FFS_CC_UNDERRUN_2 => open,
+  FFS_CC_OVERRUN_2 => open,
+  FFS_RLOL_2 => open,
+  FFS_RXFBFIFO_ERROR_2 => open,
+  FFS_TXFBFIFO_ERROR_2 => open,
+  OOB_OUT_2 => open,
+  HDINP3 => fpsc_vlo,
+  HDINN3 => fpsc_vlo,
+  HDOUTP3 => open,
+  HDOUTN3 => open,
+  SCISELCH3 => fpsc_vlo,
+  SCIENCH3 => fpsc_vlo,
+  FF_RXI_CLK_3 => fpsc_vlo,
+  FF_TXI_CLK_3 => fpsc_vlo,
+  FF_EBRD_CLK_3 => fpsc_vlo,
+  FF_RX_F_CLK_3 => open,
+  FF_RX_H_CLK_3 => open,
+  FF_RX_Q_CLK_3 => open,
+  FF_TX_D_3_0 => fpsc_vlo,
+  FF_TX_D_3_1 => fpsc_vlo,
+  FF_TX_D_3_2 => fpsc_vlo,
+  FF_TX_D_3_3 => fpsc_vlo,
+  FF_TX_D_3_4 => fpsc_vlo,
+  FF_TX_D_3_5 => fpsc_vlo,
+  FF_TX_D_3_6 => fpsc_vlo,
+  FF_TX_D_3_7 => fpsc_vlo,
+  FF_TX_D_3_8 => fpsc_vlo,
+  FF_TX_D_3_9 => fpsc_vlo,
+  FF_TX_D_3_10 => fpsc_vlo,
+  FF_TX_D_3_11 => fpsc_vlo,
+  FF_TX_D_3_12 => fpsc_vlo,
+  FF_TX_D_3_13 => fpsc_vlo,
+  FF_TX_D_3_14 => fpsc_vlo,
+  FF_TX_D_3_15 => fpsc_vlo,
+  FF_TX_D_3_16 => fpsc_vlo,
+  FF_TX_D_3_17 => fpsc_vlo,
+  FF_TX_D_3_18 => fpsc_vlo,
+  FF_TX_D_3_19 => fpsc_vlo,
+  FF_TX_D_3_20 => fpsc_vlo,
+  FF_TX_D_3_21 => fpsc_vlo,
+  FF_TX_D_3_22 => fpsc_vlo,
+  FF_TX_D_3_23 => fpsc_vlo,
+  FF_RX_D_3_0 => open,
+  FF_RX_D_3_1 => open,
+  FF_RX_D_3_2 => open,
+  FF_RX_D_3_3 => open,
+  FF_RX_D_3_4 => open,
+  FF_RX_D_3_5 => open,
+  FF_RX_D_3_6 => open,
+  FF_RX_D_3_7 => open,
+  FF_RX_D_3_8 => open,
+  FF_RX_D_3_9 => open,
+  FF_RX_D_3_10 => open,
+  FF_RX_D_3_11 => open,
+  FF_RX_D_3_12 => open,
+  FF_RX_D_3_13 => open,
+  FF_RX_D_3_14 => open,
+  FF_RX_D_3_15 => open,
+  FF_RX_D_3_16 => open,
+  FF_RX_D_3_17 => open,
+  FF_RX_D_3_18 => open,
+  FF_RX_D_3_19 => open,
+  FF_RX_D_3_20 => open,
+  FF_RX_D_3_21 => open,
+  FF_RX_D_3_22 => open,
+  FF_RX_D_3_23 => open,
+  FFC_RRST_3 => fpsc_vlo,
+  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+  FFC_SB_INV_RX_3 => fpsc_vlo,
+  FFC_PFIFO_CLR_3 => fpsc_vlo,
+  FFC_PCIE_CT_3 => fpsc_vlo,
+  FFC_PCI_DET_EN_3 => fpsc_vlo,
+  FFC_FB_LOOPBACK_3 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+  FFC_EI_EN_3 => fpsc_vlo,
+  FFC_LANE_TX_RST_3 => fpsc_vlo,
+  FFC_LANE_RX_RST_3 => fpsc_vlo,
+  FFC_TXPWDNB_3 => fpsc_vlo,
+  FFC_RXPWDNB_3 => fpsc_vlo,
+  FFS_RLOS_LO_3 => open,
+  FFS_PCIE_DONE_3 => open,
+  FFS_PCIE_CON_3 => open,
+  FFS_LS_SYNC_STATUS_3 => open,
+  FFS_CC_UNDERRUN_3 => open,
+  FFS_CC_OVERRUN_3 => open,
+  FFS_RLOL_3 => open,
+  FFS_RXFBFIFO_ERROR_3 => open,
+  FFS_TXFBFIFO_ERROR_3 => open,
+  OOB_OUT_3 => open,
+  SCIWDATA0 => fpsc_vlo,
+  SCIWDATA1 => fpsc_vlo,
+  SCIWDATA2 => fpsc_vlo,
+  SCIWDATA3 => fpsc_vlo,
+  SCIWDATA4 => fpsc_vlo,
+  SCIWDATA5 => fpsc_vlo,
+  SCIWDATA6 => fpsc_vlo,
+  SCIWDATA7 => fpsc_vlo,
+  SCIADDR0 => fpsc_vlo,
+  SCIADDR1 => fpsc_vlo,
+  SCIADDR2 => fpsc_vlo,
+  SCIADDR3 => fpsc_vlo,
+  SCIADDR4 => fpsc_vlo,
+  SCIADDR5 => fpsc_vlo,
+  SCIRDATA0 => open,
+  SCIRDATA1 => open,
+  SCIRDATA2 => open,
+  SCIRDATA3 => open,
+  SCIRDATA4 => open,
+  SCIRDATA5 => open,
+  SCIRDATA6 => open,
+  SCIRDATA7 => open,
+  SCIENAUX => fpsc_vlo,
+  SCISELAUX => fpsc_vlo,
+  SCIRD => fpsc_vlo,
+  SCIWSTN => fpsc_vlo,
+  CYAWSTN => fpsc_vlo,
+  SCIINT => open,
+  FFC_MACRO_RST => ffc_macro_rst,
+  FFC_QUAD_RST => ffc_quad_rst,
+  FFC_TRST => ffc_trst,
+  FF_TX_F_CLK => ff_txfullclk,
+  FF_TX_H_CLK => ff_txhalfclk,
+  FF_TX_Q_CLK => open,
+  REFCK2CORE => refck2core,
+  CIN0 => cin(0),
+  CIN1 => cin(1),
+  CIN2 => cin(2),
+  CIN3 => cin(3),
+  CIN4 => cin(4),
+  CIN5 => cin(5),
+  CIN6 => cin(6),
+  CIN7 => cin(7),
+  CIN8 => cin(8),
+  CIN9 => cin(9),
+  CIN10 => cin(10),
+  CIN11 => cin(11),
+  COUT0 => cout(0),
+  COUT1 => cout(1),
+  COUT2 => cout(2),
+  COUT3 => cout(3),
+  COUT4 => cout(4),
+  COUT5 => cout(5),
+  COUT6 => cout(6),
+  COUT7 => cout(7),
+  COUT8 => cout(8),
+  COUT9 => cout(9),
+  COUT10 => cout(10),
+  COUT11 => cout(11),
+  COUT12 => cout(12),
+  COUT13 => cout(13),
+  COUT14 => cout(14),
+  COUT15 => cout(15),
+  COUT16 => cout(16),
+  COUT17 => cout(17),
+  COUT18 => cout(18),
+  COUT19 => cout(19),
+  FFS_PLOL => ffs_plol);
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+   IF (open_status = name_error) THEN
+      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
+      severity ERROR;
+   END IF;
+   wait;
+END PROCESS;
+--synopsys translate_on
+
+end serdes_sfp_0_extclock_arch ;

diff --git a/media_interfaces/trb_net16_med_ecp_sfp.vhd b/media_interfaces/trb_net16_med_ecp_sfp.vhd
index eec57ec60a6de84cd97b5b5203d6cc3b6096554a..96984ba896d243221641bb7c09036f037b1cc253 100644 (file)
--- a/media_interfaces/trb_net16_med_ecp_sfp.vhd
+++ b/media_interfaces/trb_net16_med_ecp_sfp.vhd
@@ -1,6 +1,6 @@
 --Media interface for Lattice ECP2M using PCS at 2GHz
 
---Still missing: link reset features, fifo full error handling, signals on stat_op
+--Still missing: link reset features, fifo full error handling
 
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.ALL;
@@ -9,10 +9,12 @@ USE IEEE.std_logic_UNSIGNED.ALL;
 
 library work;
 use work.trb_net_std.all;
+use work.trb_net_components.all;
 
 entity trb_net16_med_ecp_sfp is
   generic(
-    SERDES_NUM : integer range 0 to 3 := 2
+    SERDES_NUM : integer range 0 to 3 := 2;
+    EXT_CLOCK  : integer range 0 to 1 := c_NO
     );
   port(
     CLK                : in  std_logic; -- SerDes clock
@@ -101,6 +103,51 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
       );
   end component;
 
+  component serdes_sfp_0_extclock
+    port(
+      refclkp : in std_logic;
+      refclkn : in std_logic;
+      hdinp0 : in std_logic;
+      hdinn0 : in std_logic;
+      ff_rxiclk_ch0 : in std_logic;
+      ff_txiclk_ch0 : in std_logic;
+      ff_ebrd_clk_0 : in std_logic;
+      ff_txdata_ch0 : in std_logic_vector(15 downto 0);
+      ff_tx_k_cntrl_ch0 : in std_logic_vector(1 downto 0);
+      ff_force_disp_ch0 : in std_logic_vector(1 downto 0);
+      ff_disp_sel_ch0 : in std_logic_vector(1 downto 0);
+      ff_correct_disp_ch0 : in std_logic_vector(1 downto 0);
+      ffc_rrst_ch0 : in std_logic;
+      ffc_lane_tx_rst_ch0 : in std_logic;
+      ffc_lane_rx_rst_ch0 : in std_logic;
+      ffc_txpwdnb_ch0 : in std_logic;
+      ffc_rxpwdnb_ch0 : in std_logic;
+      ffc_macro_rst : in std_logic;
+      ffc_quad_rst : in std_logic;
+      ffc_trst : in std_logic;
+      hdoutp0 : out std_logic;
+      hdoutn0 : out std_logic;
+      ff_rxdata_ch0 : out std_logic_vector(15 downto 0);
+      ff_rx_k_cntrl_ch0 : out std_logic_vector(1 downto 0);
+      ff_rxfullclk_ch0 : out std_logic;
+      ff_rxhalfclk_ch0 : out std_logic;
+      ff_disp_err_ch0 : out std_logic_vector(1 downto 0);
+      ff_cv_ch0 : out std_logic_vector(1 downto 0);
+      ffs_rlos_lo_ch0 : out std_logic;
+      ffs_ls_sync_status_ch0 : out std_logic;
+      ffs_cc_underrun_ch0 : out std_logic;
+      ffs_cc_overrun_ch0 : out std_logic;
+      ffs_txfbfifo_error_ch0 : out std_logic;
+      ffs_rxfbfifo_error_ch0 : out std_logic;
+      ffs_rlol_ch0 : out std_logic;
+      oob_out_ch0 : out std_logic;
+      ff_txfullclk : out std_logic;
+      ff_txhalfclk : out std_logic;
+      refck2core : out std_logic;
+      ffs_plol : out std_logic
+      );
+  end component;
+
   component serdes_sfp_1
     port(
       core_txrefclk : in std_logic;
@@ -237,78 +284,18 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
       );
   end component;
 
-  component trb_net16_lsm_sfp is
-    port(
-      SYSCLK            : in   std_logic; -- fabric clock
-      RESET             : in   std_logic; -- synchronous reset
-      CLEAR             : in   std_logic; -- asynchronous reset, connect to '0' if not needed / available
-      -- status signals
-      SFP_MISSING_IN    : in   std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place)
-      SFP_LOS_IN        : in   std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-      SD_LINK_OK_IN     : in   std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)
-      SD_LOS_IN         : in   std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)
-      SD_TXCLK_BAD_IN   : in   std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)
-      SD_RXCLK_BAD_IN   : in   std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)
-      SD_RETRY_IN       : in   std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
-      SD_ALIGNMENT_IN   : in   std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct)
-      SD_CV_IN          : in   std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD)
-      -- control signals 
-      FULL_RESET_OUT    : out  std_logic; -- full reset AKA quad_reset
-      LANE_RESET_OUT    : out  std_logic; -- partial reset AKA lane_reset
-      TX_ALLOW_OUT      : out  std_logic; -- allow normal transmit operation
-      RX_ALLOW_OUT      : out  std_logic; -- allow normal receive operation
-      SWAP_BYTES_OUT    : out  std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order)
-      -- debug signals
-      STAT_OP           : out  std_logic_vector(15 downto 0);
-      CTRL_OP           : in   std_logic_vector(15 downto 0);
-      STAT_DEBUG        : out  std_logic_vector(31 downto 0)
-      );
-  end component;
 
-  component trb_net_fifo_16bit_bram_dualport is
-    generic(
-      USE_STATUS_FLAGS : integer  := c_YES
-        );
-    port( read_clock_in  : in   std_logic;
-        write_clock_in   : in   std_logic;
-        read_enable_in   : in   std_logic;
-        write_enable_in  : in   std_logic;
-        fifo_gsr_in      : in   std_logic;
-        write_data_in    : in   std_logic_vector(17 downto 0);
-        read_data_out    : out  std_logic_vector(17 downto 0);
-        full_out         : out  std_logic;
-        empty_out        : out  std_logic;
-        fifostatus_out   : out  std_logic_vector(3 downto 0);
-        valid_read_out   : out  std_logic;
-        almost_empty_out : out  std_logic;
-        almost_full_out  : out  std_logic
-      );
-  end component;
-
-  component signal_sync is
-    generic(
-      WIDTH : integer := 1;     --
-      DEPTH : integer := 3
-      );
-    port(
-      RESET    : in   std_logic; --Reset is neceessary to avoid optimization to shift register
-      CLK0     : in   std_logic;                          --clock for first FF
-      CLK1     : in   std_logic;                          --Clock for other FF
-      D_IN     : in   std_logic_vector(WIDTH-1 downto 0); --Data input
-      D_OUT    : out  std_logic_vector(WIDTH-1 downto 0)  --Data output
-      );
-  end component;
 
   signal refck2core             : std_logic;
 --  signal clock                  : std_logic;
-  --reset signals              
+  --reset signals
   signal ffc_quad_rst           : std_logic;
   signal ffc_lane_tx_rst        : std_logic;
   signal ffc_lane_rx_rst        : std_logic;
-  --serdes connections         
+  --serdes connections
   signal tx_data                : std_logic_vector(15 downto 0);
   signal tx_k                   : std_logic_vector(1 downto 0);
-  signal rx_data                : std_logic_vector(15 downto 0); -- delayed signals 
+  signal rx_data                : std_logic_vector(15 downto 0); -- delayed signals
   signal rx_k                   : std_logic_vector(1 downto 0);  -- delayed signals
   signal comb_rx_data           : std_logic_vector(15 downto 0); -- original signals from SFP
   signal comb_rx_k              : std_logic_vector(1 downto 0);  -- original signals from SFP
@@ -316,7 +303,7 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
   signal link_error             : std_logic_vector(8 downto 0);
   signal ff_rxhalfclk           : std_logic;
   signal ff_txhalfclk           : std_logic;
-  --rx fifo signals            
+  --rx fifo signals
   signal fifo_rx_rd_en          : std_logic;
   signal fifo_rx_wr_en          : std_logic;
   signal fifo_rx_reset          : std_logic;
@@ -324,7 +311,7 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
   signal fifo_rx_dout           : std_logic_vector(17 downto 0);
   signal fifo_rx_full           : std_logic;
   signal fifo_rx_empty          : std_logic;
-  --tx fifo signals            
+  --tx fifo signals
   signal fifo_tx_rd_en          : std_logic;
   signal fifo_tx_wr_en          : std_logic;
   signal fifo_tx_reset          : std_logic;
@@ -367,11 +354,24 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
   signal rx_led                 : std_logic;
   signal tx_led                 : std_logic;
 
-
+  signal reset_i                : std_logic;
+  signal pwr_up                 : std_logic;
 begin
 
 --------------------------------------------------------------------------
--- Synchronizer stages 
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+
+  PROC_RESET : process(SYSCLK)
+    begin
+      if rising_edge(SYSCLK) then
+        reset_i <= RESET or CTRL_OP(14);
+        pwr_up  <= '1'; --not CTRL_OP(i*16+14);
+      end if;
+    end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
 --------------------------------------------------------------------------
 
 -- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
@@ -381,7 +381,7 @@ THE_SFP_STATUS_SYNC: signal_sync
     WIDTH => 2
     )
   port map(
-    RESET    => reset,
+    RESET    => reset_i,
     D_IN(0)  => sd_prsnt_n_in,
     D_IN(1)  => sd_los_in,
     CLK0     => sysclk,
@@ -397,7 +397,7 @@ THE_RX_K_SYNC: signal_sync
     WIDTH => 2
     )
   port map(
-    RESET    => reset,
+    RESET    => reset_i,
     D_IN     => comb_rx_k, -- rx_k
     CLK0     => ff_rxhalfclk,
     CLK1     => sysclk,
@@ -411,7 +411,7 @@ THE_RX_DATA_DELAY: signal_sync
     WIDTH => 16
     )
   port map(
-    RESET    => reset,
+    RESET    => reset_i,
     D_IN     => comb_rx_data,
     CLK0     => ff_rxhalfclk,
     CLK1     => ff_rxhalfclk,
@@ -424,7 +424,7 @@ THE_RX_K_DELAY: signal_sync
     WIDTH => 2
     )
   port map(
-    RESET    => reset,
+    RESET    => reset_i,
     D_IN     => comb_rx_k,
     CLK0     => ff_rxhalfclk,
     CLK1     => ff_rxhalfclk,
@@ -439,7 +439,7 @@ THE_RX_ALLOW_SYNC: signal_sync -- really needed?!?
     WIDTH => 2
     )
   port map(
-    RESET    => RESET,
+    RESET    => reset_i,
     D_IN(0)  => rx_allow,
     D_IN(1)  => tx_allow,
     CLK0     => sysclk,
@@ -455,7 +455,7 @@ THE_RX_ALLOW_SYNC: signal_sync -- really needed?!?
 THE_SFP_LSM: trb_net16_lsm_sfp
     port map(
       SYSCLK            => sysclk,
-      RESET             => reset,
+      RESET             => reset_i,
       CLEAR             => clear,
       SFP_MISSING_IN    => sfp_prsnt_n,
       SFP_LOS_IN        => sfp_los,
@@ -475,7 +475,7 @@ THE_SFP_LSM: trb_net16_lsm_sfp
       CTRL_OP           => ctrl_op,
       STAT_DEBUG        => buf_stat_debug
       );
-      
+
 sd_txdis_out <= quad_rst;
 
 --------------------------------------------------------------------------
@@ -489,7 +489,7 @@ ffc_lane_rx_rst      <= lane_rst;
 refclk2core_out <= refck2core;
 
 -- Instantiation of serdes module
-  gen_serdes_0 : if SERDES_NUM = 0 generate
+  gen_serdes_0 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO generate
     THE_SERDES: serdes_sfp_0
       port map(
              core_txrefclk          => clk,
@@ -534,6 +534,52 @@ refclk2core_out <= refck2core;
               ffs_plol               => link_error(5)
             );
   end generate;
+  gen_serdes_0_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES generate
+    THE_SERDES: serdes_sfp_0_extclock
+      port map(
+              refclkp          => SD_REFCLK_P_IN,
+              refclkn          => SD_REFCLK_N_IN,
+              hdinp0                 => sd_rxd_p_in,
+              hdinn0                 => sd_rxd_n_in,
+              ff_rxiclk_ch0          => ff_rxhalfclk,
+              ff_txiclk_ch0          => ff_txhalfclk,
+              ff_ebrd_clk_0          => ff_rxhalfclk, -- not used, just for completeness
+              ff_txdata_ch0          => tx_data,
+              ff_tx_k_cntrl_ch0      => tx_k,
+              ff_force_disp_ch0      => "00",
+              ff_disp_sel_ch0        => "00",
+              ff_correct_disp_ch0    => "00",
+              ffc_rrst_ch0           => '0',
+              ffc_lane_tx_rst_ch0    => ffc_lane_tx_rst,
+              ffc_lane_rx_rst_ch0    => ffc_lane_rx_rst,
+              ffc_txpwdnb_ch0        => '1',
+              ffc_rxpwdnb_ch0        => '1',
+              ffc_macro_rst          => '0',
+              ffc_quad_rst           => ffc_quad_rst,
+              ffc_trst               => '0',
+              hdoutp0                => sd_txd_p_out,
+              hdoutn0                => sd_txd_n_out,
+              ff_rxdata_ch0          => comb_rx_data, --rx_data,
+              ff_rx_k_cntrl_ch0      => comb_rx_k, --rx_k,
+              ff_rxfullclk_ch0       => open,
+              ff_rxhalfclk_ch0       => ff_rxhalfclk,
+              ff_disp_err_ch0        => open,
+              ff_cv_ch0              => link_error(7 downto 6),
+              ffs_rlos_lo_ch0        => link_error(8),
+              ffs_ls_sync_status_ch0 => link_ok(0),
+              ffs_cc_underrun_ch0    => link_error(0),
+              ffs_cc_overrun_ch0     => link_error(1),
+              ffs_txfbfifo_error_ch0 => link_error(2),
+              ffs_rxfbfifo_error_ch0 => link_error(3),
+              ffs_rlol_ch0           => link_error(4),
+              oob_out_ch0            => open,
+              ff_txfullclk           => open,
+              ff_txhalfclk           => ff_txhalfclk,
+              refck2core             => refck2core,
+              ffs_plol               => link_error(5)
+            );
+  end generate;
+
   gen_serdes_1 : if SERDES_NUM = 1 generate
     THE_SERDES: serdes_sfp_1
       port map(
@@ -689,7 +735,7 @@ port map( read_clock_in  => sysclk,
       empty_out          => fifo_rx_empty
     );
 
-fifo_rx_reset <= reset or not rx_allow_q;
+fifo_rx_reset <= reset_i or not rx_allow_q;
 fifo_rx_rd_en <= '1';
 
 -- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
@@ -715,7 +761,7 @@ med_read_out              <= tx_allow_q;
 THE_SYNC_PROC: process( sysclk )
 begin
   if( rising_edge(sysclk) ) then
-    if RESET = '1' then
+    if reset_i = '1' then
       med_dataready_out <= '0';
     else
       med_dataready_out     <= buf_med_dataready_out;
@@ -731,7 +777,7 @@ THE_RX_PACKETS_PROC: process( sysclk )
 begin
   if( rising_edge(sysclk) ) then
     last_fifo_rx_empty <= fifo_rx_empty;
-    if RESET = '1' or rx_allow_q = '0' then
+    if reset_i = '1' or rx_allow_q = '0' then
       rx_counter <= c_H0;
     else
       if( buf_med_dataready_out = '1' ) then
@@ -762,7 +808,7 @@ port map( read_clock_in => ff_txhalfclk,
       empty_out         => fifo_tx_empty
     );
 
-fifo_tx_reset <= reset or not tx_allow_q;
+fifo_tx_reset <= reset_i or not tx_allow_q;
 fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
 fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
 fifo_tx_rd_en <= tx_allow;