*** empty log message ***

diff --git a/README b/README
index d70bf32ba4bf9f10fadaeae607d3cb3e8d915394..3c8bc0c698e5c408a2281c6e216779ea6e59c5f1 100644 (file)
--- a/README
+++ b/README
@@ -21,7 +21,9 @@ fpgatest                    Designs used during hardware testing
 
 === Files to copy & change for new projects (COPY, CHANGE & USE)
 
+base/trb3_central.p2t               Config file for PAR
 base/trb3_central.vhd               Basic design for central FPGA
+base/trb3_periph.p2t                Config file for PAR
 base/trb3_periph.vhd                Basic design for central FPGA
 base/constraints_trb3_central.lpf   Constraints for each specific design of trb3_central
 base/constraints_trb3_periph.lpf    Constraints for each specific design of trb3_peripheral

diff --git a/base/compile_central_frankfurt.pl b/base/compile_central_frankfurt.pl
new file mode 100755 (executable)
index 0000000..7e2ddd7
--- /dev/null
+++ b/base/compile_central_frankfurt.pl
@@ -0,0 +1,151 @@
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+
+
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME                      = "trb3_central";  #Name of top-level entity
+my $lattice_path                 = '/d/sugar/lattice/diamond/1.3';
+my $synplify_path                = '/d/sugar/lattice/synplify/D-2010.03/';
+my $lm_license_file_for_synplify = "27000\@localhost";
+my $lm_license_file_for_par      = "1710\@cronos.e12.physik.tu-muenchen.de";
+###################################################################################
+
+
+
+
+
+
+
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA1156";
+my $SPEEDGRADE="7";
+
+
+#create full lpf file
+system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+    constant VERSION_NUMBER_TIME  : integer   := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+
+
+foreach (@a)
+{
+    if(/\@E:/)
+    {
+       print "\n";
+       $c="cat $TOPNAME.srr | grep \"\@E\"";
+       system($c);
+        print "\n\n";
+       exit 129;
+    }
+}
+
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd  -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate   -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+
+system("rm $TOPNAME.ncd");
+
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen  -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+exit;
+
+sub execute {
+    my ($c, $op) = @_;
+    #print "option: $op \n";
+    $op = "" if(!$op);
+    print "\n\ncommand to execute: $c \n";
+    $r=system($c);
+    if($r) {
+       print "$!";
+       if($op ne "do_not_exit") {
+           exit;
+       }
+    }
+
+    return $r;
+
+}

diff --git a/base/compile_periph_frankfurt.pl b/base/compile_periph_frankfurt.pl
new file mode 100755 (executable)
index 0000000..b7a6271
--- /dev/null
+++ b/base/compile_periph_frankfurt.pl
@@ -0,0 +1,152 @@
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+
+
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME                      = "trb3_periph";  #Name of top-level entity
+my $BasePath                     = "../base/";     #path to "base" directory
+my $lattice_path                 = '/d/sugar/lattice/diamond/1.3';
+my $synplify_path                = '/d/sugar/lattice/synplify/D-2010.03/';
+my $lm_license_file_for_synplify = "27000\@localhost";
+my $lm_license_file_for_par      = "1710\@cronos.e12.physik.tu-muenchen.de";
+###################################################################################
+
+
+
+
+
+
+
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA1156";
+my $SPEEDGRADE="7";
+
+
+#create full lpf file
+system("cp $BasePath/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+    constant VERSION_NUMBER_TIME  : integer   := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+
+
+foreach (@a)
+{
+    if(/\@E:/)
+    {
+  print "\n";
+  $c="cat $TOPNAME.srr | grep \"\@E\"";
+  system($c);
+        print "\n\n";
+  exit 129;
+    }
+}
+
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd  -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate   -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+
+system("rm $TOPNAME.ncd");
+
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen  -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+exit;
+
+sub execute {
+    my ($c, $op) = @_;
+    #print "option: $op \n";
+    $op = "" if(!$op);
+    print "\n\ncommand to execute: $c \n";
+    $r=system($c);
+    if($r) {
+  print "$!";
+  if($op ne "do_not_exit") {
+      exit;
+  }
+    }
+
+    return $r;
+
+}

diff --git a/base/trb3_central.lpf b/base/trb3_central.lpf
index 20e83349e1d0a4529122594b3563802fd39de20a..95ea4a3602f639c5ee49516456c106d29882b656 100644 (file)
--- a/base/trb3_central.lpf
+++ b/base/trb3_central.lpf
@@ -29,13 +29,13 @@ IOBUF PORT   "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4;
 
 #Trigger from fan-out
 LOCATE COMP  "TRIGGER_RIGHT" SITE "W30";
-IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25  
+IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; 
 LOCATE COMP  "TRIGGER_LEFT"  SITE "Y2";
-IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25  
+IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25 ;
 
 #To fan-out to all FPGA
 LOCATE COMP  "TRIGGER_OUT"   SITE "V7";
-IOBUF  PORT  "TRIGGER_OUT"   IO_TYPE=LVDS25  
+IOBUF  PORT  "TRIGGER_OUT"   IO_TYPE=LVDS25 ; 
 
 #Additional lines on Trigger-RJ-45
 LOCATE COMP  "TRIGGER_EXT_2"   SITE "W2";
@@ -50,7 +50,7 @@ IOBUF GROUP  "TRIGGER_EXT_group" IO_TYPE=LVDS25;
 #################################################################
 #Trigger select for fan-out. 0: external trigger. 1: TRIGGER_OUT
 LOCATE COMP  "TRIGGER_SELECT" SITE "AA31";
-IOBUF  PORT  "TRIGGER_SELECT" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4  ;
+IOBUF  PORT  "TRIGGER_SELECT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4  ;
 
 LOCATE COMP  "CLK_MNGR1_USER_0"   SITE "AA28";
 LOCATE COMP  "CLK_MNGR1_USER_1"   SITE "AA27";
@@ -64,22 +64,28 @@ DEFINE PORT GROUP "CLK_MNGR_group" "CLK_MNGR*" ;
 IOBUF GROUP "CLK_MNGR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
 
 LOCATE COMP  "CLOCK_SELECT"   SITE "AA30";
-IOBUF  PORT  "CLOCK_SELECT" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4  ;
+IOBUF  PORT  "CLOCK_SELECT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4  ;
 
 #################################################################
 # LED
 #################################################################
-LOCATE COMP  "LED_CLOCK_GREEN"    SITE "AL4";
-LOCATE COMP  "LED_CLOCK_RED"      SITE "AM4";
 LOCATE COMP  "LED_GREEN"          SITE "A17";
 LOCATE COMP  "LED_ORANGE"         SITE "B17";
 LOCATE COMP  "LED_RED"            SITE "E19";
-LOCATE COMP  "LED_TRIGGER_GREEN"  SITE "AP5";
-LOCATE COMP  "LED_TRIGGER_RED"    SITE "AP6";
 LOCATE COMP  "LED_YELLOW"         SITE "E20";
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8;
+IOBUF PORT "LED_GREEN"  IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8;
+IOBUF PORT "LED_ORANGE" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8;
+IOBUF PORT "LED_RED"    IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8;
+IOBUF PORT "LED_YELLOW" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8;
 
+LOCATE COMP  "LED_TRIGGER_GREEN"  SITE "AP5";
+LOCATE COMP  "LED_TRIGGER_RED"    SITE "AP6";
+LOCATE COMP  "LED_CLOCK_GREEN"    SITE "AL4";
+LOCATE COMP  "LED_CLOCK_RED"      SITE "AM4";
+IOBUF PORT "LED_TRIGGER_GREEN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8;
+IOBUF PORT "LED_TRIGGER_RED"   IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8;
+IOBUF PORT "LED_CLOCK_GREEN"   IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8;
+IOBUF PORT "LED_CLOCK_RED"     IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8;
 
 #################################################################
 # Inter-FPGA Connection
@@ -192,7 +198,7 @@ LOCATE COMP  "FPGA4_TTL_1"    SITE "H23";
 LOCATE COMP  "FPGA4_TTL_2"    SITE "D24";
 LOCATE COMP  "FPGA4_TTL_3"    SITE "E24";
 DEFINE PORT GROUP "FPGATTL_group" "*TTL*" ;
-IOBUF GROUP "TTL_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=8;
+IOBUF GROUP "FPGATTL_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=8;
 
 #################################################################
 # SFP Control / Status
@@ -268,7 +274,10 @@ LOCATE COMP  "ADDON_TO_TRB_CLK"   SITE "J17";
 IOBUF  PORT "ADDON_TO_TRB_CLK" IO_TYPE=LVDS25  ;
 
 LOCATE COMP  "TRB_TO_ADDON_CLK"   SITE "K16";
-IOBUF  PORT "TRB_TO_ADDON_CLK" IO_TYPE=LVDS25  ;
+IOBUF  PORT "TRB_TO_ADDON_CLK" IO_TYPE=LVCMOS25  ;
+LOCATE COMP  "TRB_TO_ADDON_CLKb"   SITE "L16";
+IOBUF  PORT "TRB_TO_ADDON_CLKb" IO_TYPE=LVCMOS25  ;
+
 
 LOCATE COMP  "ADO_LV_0"   SITE "D5";
 LOCATE COMP  "ADO_LV_1"   SITE "C6";
@@ -475,74 +484,7 @@ IOBUF  PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8  ;
 #################################################################
 # Other Pins / Unused
 #################################################################
-# LOCATE COMP  "SDF4_RIGHT_INP_0"   SITE "AP10";
-# LOCATE COMP  "SDF4_RIGHT_INN_0"   SITE "AN10";
-# LOCATE COMP  "SDF3_RIGHT_OUTP_0"    SITE "AL11";
-# LOCATE COMP  "SDF4_RIGHT_OUTP_0"    SITE "AL10";
-# LOCATE COMP  "SDF4_RIGHT_OUTN_0"    SITE "AK10";
-# LOCATE COMP  "SDF2_RIGHT_OUTN_0"    SITE "AK12";
-# LOCATE COMP  "SDF1_RIGHT_INP_0"   SITE "AP13";
-# LOCATE COMP  "SDF2_RIGHT_INP_0"   SITE "AP12";
-# LOCATE COMP  "SDF1_RIGHT_INN_0"   SITE "AN13";
-# LOCATE COMP  "SDF3_RIGHT_INN_0"   SITE "AN11";
-# LOCATE COMP  "SDF2_RIGHT_INN_0"   SITE "AN12";
-# LOCATE COMP  "SDF1_RIGHT_OUTP_0"    SITE "AL13";
-# LOCATE COMP  "SDF3_RIGHT_OUTN_0"    SITE "AK11";
-# LOCATE COMP  "SDF2_RIGHT_OUTP_0"    SITE "AL12";
-# LOCATE COMP  "SDF3_RIGHT_INP_0"   SITE "AP11";
-# LOCATE COMP  "SDF1_RIGHT_OUTN_0"    SITE "AK13";
-# LOCATE COMP  "SDF4_RIGHT_OUTP_1"    SITE "AL22";
-# LOCATE COMP  "SDF3_RIGHT_INN_1"   SITE "AN23";
-# LOCATE COMP  "SDF3_RIGHT_OUTN_1"    SITE "AK23";
-# LOCATE COMP  "SDF2_RIGHT_OUTN_1"    SITE "AK24";
-# LOCATE COMP  "SDF2_RIGHT_INN_1"   SITE "AN24";
-# LOCATE COMP  "SDF3_RIGHT_OUTP_1"    SITE "AL23";
-# LOCATE COMP  "SDF4_RIGHT_INN_1"   SITE "AN22";
-# LOCATE COMP  "SDF1_RIGHT_OUTN_1"    SITE "AK25";
-# LOCATE COMP  "SDF2_RIGHT_OUTP_1"    SITE "AL24";
-# LOCATE COMP  "SDF1_RIGHT_OUTP_1"    SITE "AL25";
-# LOCATE COMP  "SDF1_RIGHT_INP_1"   SITE "AP25";
-# LOCATE COMP  "SDF3_RIGHT_INP_1"   SITE "AP23";
-# LOCATE COMP  "SDF1_RIGHT_INN_1"   SITE "AN25";
-# LOCATE COMP  "SDF2_RIGHT_INP_1"   SITE "AP24";
-# LOCATE COMP  "SDF4_RIGHT_OUTN_1"    SITE "AK22";
-# LOCATE COMP  "SDF4_RIGHT_INP_1"   SITE "AP22";
-# LOCATE COMP  "SFP5_RXN"   SITE "AK17";
-# LOCATE COMP  "SFP5_TXP"   SITE "AP17";
-# LOCATE COMP  "SFP8_RXP"   SITE "AL14";
-# LOCATE COMP  "SFP8_TXP"   SITE "AP14";
-# LOCATE COMP  "SFP1_TXN"   SITE "AN21";
-# LOCATE COMP  "SFP4_RXN"   SITE "AK18";
-# LOCATE COMP  "SFP6_TXP"   SITE "AP16";
-# LOCATE COMP  "SFP1_RXP"   SITE "AL21";
-# LOCATE COMP  "SFP5_RXP"   SITE "AL17";
-# LOCATE COMP  "SFP7_TXN"   SITE "AN15";
-# LOCATE COMP  "SFP6_RXN"   SITE "AK16";
-# LOCATE COMP  "SFP3_RXP"   SITE "AL19";
-# LOCATE COMP  "SFP2_RXP"   SITE "AL20";
-# LOCATE COMP  "SFP7_RXP"   SITE "AL15";
-# LOCATE COMP  "SFP2_TXN"   SITE "AN20";
-# LOCATE COMP  "SFP4_RXP"   SITE "AL18";
-# LOCATE COMP  "SFP3_TXP"   SITE "AP19";
-# LOCATE COMP  "SFP7_TXP"   SITE "AP15";
-# LOCATE COMP  "SFP8_RXN"   SITE "AK14";
-# LOCATE COMP  "SFP2_TXP"   SITE "AP20";
-# LOCATE COMP  "SFP1_RXN"   SITE "AK21";
-# LOCATE COMP  "SFP1_TXP"   SITE "AP21";
-# LOCATE COMP  "SFP3_RXN"   SITE "AK19";
-# LOCATE COMP  "SFP8_TXN"   SITE "AN14";
-# LOCATE COMP  "SFP4_TXP"   SITE "AP18";
-# LOCATE COMP  "SFP7_RXN"   SITE "AK15";
-# LOCATE COMP  "SFP5_TXN"   SITE "AN17";
-# LOCATE COMP  "SFP2_RXN"   SITE "AK20";
-# LOCATE COMP  "SFP4_TXN"   SITE "AN18";
-# LOCATE COMP  "SFP6_TXN"   SITE "AN16";
-# LOCATE COMP  "SFP6_RXP"   SITE "AL16";
-# LOCATE COMP  "SFP3_TXN"   SITE "AN19";
-# LOCATE COMP  "JTAG_F5TDO"   SITE "C1";
-# LOCATE COMP  "JTAG_TCK"   SITE "D1";
-# LOCATE COMP  "JTAG_TDO"   SITE "E1";
-# LOCATE COMP  "JTAG_TMS"   SITE "D2";
+
 
 
 

diff --git a/base/trb3_central.p2t b/base/trb3_central.p2t
new file mode 100644 (file)
index 0000000..c037b03
--- /dev/null
+++ b/base/trb3_central.p2t
@@ -0,0 +1,20 @@
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 12
+-c 1
+-e 2
+-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:

diff --git a/base/trb3_central.prj b/base/trb3_central.prj
new file mode 100644 (file)
index 0000000..7ba2894
--- /dev/null
+++ b/base/trb3_central.prj
@@ -0,0 +1,63 @@
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN1156C
+set_option -speed_grade -7
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3_central"
+set_option -resource_sharing true
+
+# map options
+set_option -frequency 200
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+#set_option -force_gsr 
+set_option -force_gsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3_central.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#add_file options
+
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+
+add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib "work" "./trb3_central.vhd"
+add_file -vhdl -lib "work" "../base/trb3_components.vhd"
+
+
+

diff --git a/base/trb3_central.vhd b/base/trb3_central.vhd
index 4e4474683550822241b47b14ad5d2d30bf36bc06..6967cbfcb306de617bdf77374995aa2af96ede46 100644 (file)
--- a/base/trb3_central.vhd
+++ b/base/trb3_central.vhd
@@ -99,7 +99,6 @@ entity trb3_central is
     attribute syn_useioff : boolean;
     --no IO-FF for LEDs relaxes timing constraints
     attribute syn_useioff of LED_CLOCK_GREEN    : signal is false;
-    attribute syn_useioff of LED_CLOCK_GREEN    : signal is false;
     attribute syn_useioff of LED_CLOCK_RED      : signal is false;
     attribute syn_useioff of LED_GREEN          : signal is false;
     attribute syn_useioff of LED_ORANGE         : signal is false;
@@ -132,6 +131,9 @@ architecture trb3_central_arch of trb3_central is
   signal clk_200_i   : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
   signal pll_lock    : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
 
+  
+  --FPGA Test
+  signal time_counter : unsigned(31 downto 0);
 begin
 
 ---------------------------------------------------------------------------
@@ -151,24 +153,24 @@ begin
 ---------------------------------------------------------------------------
   TRIGGER_SELECT <= '0'; --always external trigger source
   CLOCK_SELECT   <= '0'; --use on-board oscillator
-  CLK_MNGR1_USER <= (others => 'Z');
-  CLK_MNGR2_USER <= (others => 'Z'); 
+  CLK_MNGR1_USER <= (others => '0');
+  CLK_MNGR2_USER <= (others => '0'); 
 
   TRIGGER_OUT    <= '0';
 
-
+  SFP_TXDIS <= (others => '0');
 ---------------------------------------------------------------------------
 -- FPGA communication
 ---------------------------------------------------------------------------
-  FPGA1_COMM <= (others => 'Z');
-  FPGA2_COMM <= (others => 'Z');
-  FPGA3_COMM <= (others => 'Z');
-  FPGA4_COMM <= (others => 'Z');
+  FPGA1_COMM <= (others => '0');
+  FPGA2_COMM <= (others => '0');
+  FPGA3_COMM <= (others => '0');
+  FPGA4_COMM <= (others => '0');
 
-  FPGA1_TTL <= (others => 'Z');
-  FPGA2_TTL <= (others => 'Z');
-  FPGA3_TTL <= (others => 'Z');
-  FPGA4_TTL <= (others => 'Z');
+  FPGA1_TTL <= (others => '0');
+  FPGA2_TTL <= (others => '0');
+  FPGA3_TTL <= (others => '0');
+  FPGA4_TTL <= (others => '0');
 
   FPGA1_CONNECTOR <= (others => '0');
   FPGA2_CONNECTOR <= (others => '0');
@@ -198,14 +200,13 @@ begin
 -- LED
 ---------------------------------------------------------------------------
   LED_CLOCK_GREEN                <= '0';
-  LED_CLOCK_GREEN                <= '1';
   LED_CLOCK_RED                  <= '1';
-  LED_GREEN                      <= '1';
-  LED_ORANGE                     <= '1'; 
-  LED_RED                        <= '1';
+  LED_GREEN                      <= not time_counter(24);
+  LED_ORANGE                     <= not time_counter(25); 
+  LED_RED                        <= not time_counter(26);
   LED_TRIGGER_GREEN              <= '0';
   LED_TRIGGER_RED                <= '1';
-  LED_YELLOW                     <= '1';
+  LED_YELLOW                     <= not time_counter(27);
 
 
 ---------------------------------------------------------------------------
@@ -214,4 +215,13 @@ begin
   TEST_LINE                     <= (others => '0');
 
 
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+  process
+    begin
+      wait until rising_edge(clk_100_i);
+      time_counter <= time_counter + 1;
+    end process;
+
 end architecture;
\ No newline at end of file

diff --git a/fpgatest/projects/trb3_central.ldf b/fpgatest/projects/trb3_central.ldf
new file mode 100644 (file)
index 0000000..d2e31d1
--- /dev/null
+++ b/fpgatest/projects/trb3_central.ldf
@@ -0,0 +1,32 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="1.3" title="trb3_central" device="LFE3-150EA-7FN672C" default_implementation="trb3_central">
+    <Options/>
+    <Implementation title="trb3_central" dir="trb3_central" description="trb3_central" default_strategy="Strategy1">
+        <Options/>
+        <Source name="../../base/trb3_central.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../base/cores/pll_in200_out100.lpc" type="LPC_Module" type_short="LPC">
+            <Options/>
+        </Source>
+        <Source name="../../base/cores/pll_in200_out100.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../base/trb3_central.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="Strategy1.sty"/>
+</BaliProject>