signal link_rx_ready_i : std_logic_vector(3 downto 0);
signal link_rx_null_i : std_logic_vector(3 downto 0);
signal link_tx_null_i : std_logic_vector(3 downto 0);
- signal link_active_i : std_logic_vector(3 downto 0);
signal word_sync_i : std_logic_vector(3 downto 0);
signal rx_rst_word_i : std_logic_vector(4*8-1 downto 0);
WORD_SYNC_OUT => word_sync_i(i),
LINK_TX_READY_IN => LINK_TX_READY_IN,
LINK_RX_READY_OUT => link_rx_ready_i(i),
- LINK_ACTIVE_OUT => link_active_i(i),
LINK_RX_NULL_OUT => link_rx_null_i(i),
LINK_TX_NULL_IN => link_tx_null_i(i),
-- komma operation
WORD_SYNC_OUT : out std_logic;
LINK_TX_READY_IN : in std_logic; --
LINK_RX_READY_OUT : out std_logic; --
- LINK_ACTIVE_OUT : out std_logic; --
LINK_RX_NULL_OUT : out std_logic;
LINK_TX_NULL_IN : in std_logic;
-- komma handling
signal link_status : std_logic_vector(3 downto 0);
signal link_status_qsys : std_logic_vector(3 downto 0);
signal link_active_i : std_logic;
- signal link_active_qref : std_logic;
signal link_active_qsys : std_logic;
signal link_rx_null_i : std_logic;
signal link_rx_null_qref : std_logic;
RX_RST_OUT => RX_RST_OUT,
RX_RST_WORD_OUT => RX_RST_WORD_OUT,
--
- LINK_RX_READY_IN => link_rx_ready_i, -- internally synced
+ LINK_RX_READY_IN => link_rx_ready_i, -- internally synced to CLK_RXI
LINK_HALF_DONE_OUT => link_half_done_i, -- CLK_RXI based
LINK_FULL_DONE_OUT => link_full_done_i, -- CLK_RXI based
LINK_RX_NULL_OUT => link_rx_null_i, -- CLK_RXI based
SEND_RST_IN => TX_RST_IN,
SEND_RST_WORD_IN => TX_RST_WORD_IN,
-- link status signals, internally synced
- LINK_TX_READY_IN => link_tx_ready_i, -- internally synced
- LINK_RX_READY_IN => link_rx_ready_i, -- internally synced
- LINK_HALF_DONE_IN => link_half_done_i, -- internally synced
- LINK_FULL_DONE_IN => link_full_done_i, -- internally synced
+ LINK_TX_READY_IN => link_tx_ready_i, -- internally synced to CLK_TXI
+ LINK_RX_READY_IN => link_rx_ready_i, -- internally synced to CLK_TXI
+ LINK_HALF_DONE_IN => link_half_done_i, -- internally synced to CLK_TXI
+ LINK_FULL_DONE_IN => link_full_done_i, -- internally synced to CLK_TXI
LINK_TX_NULL_IN => LINK_TX_NULL_IN,
-- debug
DEBUG_OUT => debug_tx_control_i,
SYNC_LA_SIGS : entity work.signal_sync
generic map(
- WIDTH => 2,
+ WIDTH => 1,
DEPTH => 3
)
port map(
RESET => '0',
CLK0 => CLK_REF,
CLK1 => CLK_REF,
- D_IN(0) => link_active_i,
- D_IN(1) => link_rx_null_i,
- D_OUT(0) => link_active_qref,
- D_OUT(1) => link_rx_null_qref
+ D_IN(0) => link_rx_null_i,
+ D_OUT(0) => link_rx_null_qref
);
- LINK_ACTIVE_OUT <= link_active_qref;
LINK_RX_NULL_OUT <= link_rx_null_qref;
-- TEST_LINE signals