--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n adc_1ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 2 -freq_in 200 -gear 2 -aligned -del 11 -dynamic_delay -data_lane -fdc /local/trb/git/trb5sc/adc/cores/adc_1ch/adc_1ch.fdc
+
+-- Tue Jun 25 16:53:16 2024
+
+
+
+--
+-- Verific VHDL Description of OPERATOR equal_32
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity equal_32 is
+ port (a: in std_logic_vector(31 downto 0);
+ b: in std_logic_vector(31 downto 0);
+ o: out std_logic
+ );
+
+end entity equal_32;
+
+architecture INTERFACE of equal_32 is
+ signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,
+ n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,
+ n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,
+ n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,
+ n58,n59,n60,n61,n62,n63 : std_logic;
+begin
+ n1 <= a(0) xor b(0);
+ n2 <= a(1) xor b(1);
+ n3 <= a(2) xor b(2);
+ n4 <= a(3) xor b(3);
+ n5 <= a(4) xor b(4);
+ n6 <= a(5) xor b(5);
+ n7 <= a(6) xor b(6);
+ n8 <= a(7) xor b(7);
+ n9 <= a(8) xor b(8);
+ n10 <= a(9) xor b(9);
+ n11 <= a(10) xor b(10);
+ n12 <= a(11) xor b(11);
+ n13 <= a(12) xor b(12);
+ n14 <= a(13) xor b(13);
+ n15 <= a(14) xor b(14);
+ n16 <= a(15) xor b(15);
+ n17 <= a(16) xor b(16);
+ n18 <= a(17) xor b(17);
+ n19 <= a(18) xor b(18);
+ n20 <= a(19) xor b(19);
+ n21 <= a(20) xor b(20);
+ n22 <= a(21) xor b(21);
+ n23 <= a(22) xor b(22);
+ n24 <= a(23) xor b(23);
+ n25 <= a(24) xor b(24);
+ n26 <= a(25) xor b(25);
+ n27 <= a(26) xor b(26);
+ n28 <= a(27) xor b(27);
+ n29 <= a(28) xor b(28);
+ n30 <= a(29) xor b(29);
+ n31 <= a(30) xor b(30);
+ n32 <= a(31) xor b(31);
+ n33 <= n1 or n2;
+ n34 <= n3 or n4;
+ n35 <= n33 or n34;
+ n36 <= n5 or n6;
+ n37 <= n7 or n8;
+ n38 <= n36 or n37;
+ n39 <= n35 or n38;
+ n40 <= n9 or n10;
+ n41 <= n11 or n12;
+ n42 <= n40 or n41;
+ n43 <= n13 or n14;
+ n44 <= n15 or n16;
+ n45 <= n43 or n44;
+ n46 <= n42 or n45;
+ n47 <= n39 or n46;
+ n48 <= n17 or n18;
+ n49 <= n19 or n20;
+ n50 <= n48 or n49;
+ n51 <= n21 or n22;
+ n52 <= n23 or n24;
+ n53 <= n51 or n52;
+ n54 <= n50 or n53;
+ n55 <= n25 or n26;
+ n56 <= n27 or n28;
+ n57 <= n55 or n56;
+ n58 <= n29 or n30;
+ n59 <= n31 or n32;
+ n60 <= n58 or n59;
+ n61 <= n57 or n60;
+ n62 <= n54 or n61;
+ n63 <= n47 or n62;
+ o <= not n63;
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR mux_5
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity mux_5 is
+ port (d0: in std_logic_vector(4 downto 0);
+ d1: in std_logic_vector(4 downto 0);
+ cond: in std_logic;
+ o: out std_logic_vector(4 downto 0)
+ );
+
+end entity mux_5;
+
+architecture INTERFACE of mux_5 is
+
+begin
+ o(0) <= d1(0) when cond='1' else d0(0);
+ o(1) <= d1(1) when cond='1' else d0(1);
+ o(2) <= d1(2) when cond='1' else d0(2);
+ o(3) <= d1(3) when cond='1' else d0(3);
+ o(4) <= d1(4) when cond='1' else d0(4);
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR equal_5
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity equal_5 is
+ port (a: in std_logic_vector(4 downto 0);
+ b: in std_logic_vector(4 downto 0);
+ o: out std_logic
+ );
+
+end entity equal_5;
+
+architecture INTERFACE of equal_5 is
+ signal n1,n2,n3,n4,n5,n6,n7,n8,n9 : std_logic;
+begin
+ n1 <= a(0) xor b(0);
+ n2 <= a(1) xor b(1);
+ n3 <= a(2) xor b(2);
+ n4 <= a(3) xor b(3);
+ n5 <= a(4) xor b(4);
+ n6 <= n1 or n2;
+ n7 <= n4 or n5;
+ n8 <= n3 or n7;
+ n9 <= n6 or n8;
+ o <= not n9;
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR reduce_nor_6
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity reduce_nor_6 is
+ port (a: in std_logic_vector(5 downto 0);
+ o: out std_logic
+ );
+
+end entity reduce_nor_6;
+
+architecture INTERFACE of reduce_nor_6 is
+ signal n1,n2,n3,n4,n5 : std_logic;
+begin
+ n1 <= a(1) or a(2);
+ n2 <= a(0) or n1;
+ n3 <= a(4) or a(5);
+ n4 <= a(3) or n3;
+ n5 <= n2 or n4;
+ o <= not n5;
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR Select_7
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity Select_7 is
+ port (sel: in std_logic_vector(6 downto 0);
+ data: in std_logic_vector(6 downto 0);
+ o: out std_logic
+ );
+
+end entity Select_7;
+
+architecture INTERFACE of Select_7 is
+ signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12 : std_logic;
+begin
+ n1 <= data(0) and sel(0);
+ n2 <= data(1) and sel(1);
+ n3 <= data(2) and sel(2);
+ n4 <= data(3) and sel(3);
+ n5 <= data(4) and sel(4);
+ n6 <= data(5) and sel(5);
+ n7 <= data(6) and sel(6);
+ n8 <= n2 or n3;
+ n9 <= n1 or n8;
+ n10 <= n4 or n5;
+ n11 <= n6 or n7;
+ n12 <= n10 or n11;
+ o <= n9 or n12;
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR wide_select_7_35
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity wide_select_7_35 is
+ port (sel: in std_logic_vector(6 downto 0);
+ data: in std_logic_vector(34 downto 0);
+ o: out std_logic_vector(4 downto 0)
+ );
+
+end entity wide_select_7_35;
+
+architecture INTERFACE of wide_select_7_35 is
+
+begin
+ Select_0: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5),
+ sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1),
+ sel(0)=>sel(0),data(6)=>data(30),data(5)=>data(25),data(4)=>data(20),
+ data(3)=>data(15),data(2)=>data(10),data(1)=>data(5),data(0)=>data(0),
+ o=>o(0));
+ Select_1: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5),
+ sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1),
+ sel(0)=>sel(0),data(6)=>data(31),data(5)=>data(26),data(4)=>data(21),
+ data(3)=>data(16),data(2)=>data(11),data(1)=>data(6),data(0)=>data(1),
+ o=>o(1));
+ Select_2: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5),
+ sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1),
+ sel(0)=>sel(0),data(6)=>data(32),data(5)=>data(27),data(4)=>data(22),
+ data(3)=>data(17),data(2)=>data(12),data(1)=>data(7),data(0)=>data(2),
+ o=>o(2));
+ Select_3: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5),
+ sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1),
+ sel(0)=>sel(0),data(6)=>data(33),data(5)=>data(28),data(4)=>data(23),
+ data(3)=>data(18),data(2)=>data(13),data(1)=>data(8),data(0)=>data(3),
+ o=>o(3));
+ Select_4: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5),
+ sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1),
+ sel(0)=>sel(0),data(6)=>data(34),data(5)=>data(29),data(4)=>data(24),
+ data(3)=>data(19),data(2)=>data(14),data(1)=>data(9),data(0)=>data(4),
+ o=>o(4));
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR LessThan_3u_3u
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity LessThan_3u_3u is
+ port (cin: in std_logic;
+ a: in std_logic_vector(2 downto 0);
+ b: in std_logic_vector(2 downto 0);
+ o: out std_logic
+ );
+
+end entity LessThan_3u_3u;
+
+architecture INTERFACE of LessThan_3u_3u is
+ signal n1,n2,n3,n4,n5 : std_logic;
+begin
+ n1 <= a(0) xor b(0);
+ n2 <= b(0) when n1='1' else cin;
+ n3 <= a(1) xor b(1);
+ n4 <= b(1) when n3='1' else n2;
+ n5 <= a(2) xor b(2);
+ o <= b(2) when n5='1' else n4;
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR add_32u_32u
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity add_32u_32u is
+ port (cin: in std_logic;
+ a: in std_logic_vector(31 downto 0);
+ b: in std_logic_vector(31 downto 0);
+ o: out std_logic_vector(31 downto 0);
+ cout: out std_logic
+ );
+
+end entity add_32u_32u;
+
+architecture INTERFACE of add_32u_32u is
+ signal n2,n4,n6,n8,n10,n12,n14,n16,n18,n20,n22,n24,n26,n28,
+ n30,n32,n34,n36,n38,n40,n42,n44,n46,n48,n50,n52,n54,n56,
+ n58,n60,n62 : std_logic;
+begin
+ n2 <= a(0) or b(0) when cin='1' else a(0) and b(0);
+ o(0) <= a(0) xor b(0) xor cin;
+ n4 <= a(1) or b(1) when n2='1' else a(1) and b(1);
+ o(1) <= a(1) xor b(1) xor n2;
+ n6 <= a(2) or b(2) when n4='1' else a(2) and b(2);
+ o(2) <= a(2) xor b(2) xor n4;
+ n8 <= a(3) or b(3) when n6='1' else a(3) and b(3);
+ o(3) <= a(3) xor b(3) xor n6;
+ n10 <= a(4) or b(4) when n8='1' else a(4) and b(4);
+ o(4) <= a(4) xor b(4) xor n8;
+ n12 <= a(5) or b(5) when n10='1' else a(5) and b(5);
+ o(5) <= a(5) xor b(5) xor n10;
+ n14 <= a(6) or b(6) when n12='1' else a(6) and b(6);
+ o(6) <= a(6) xor b(6) xor n12;
+ n16 <= a(7) or b(7) when n14='1' else a(7) and b(7);
+ o(7) <= a(7) xor b(7) xor n14;
+ n18 <= a(8) or b(8) when n16='1' else a(8) and b(8);
+ o(8) <= a(8) xor b(8) xor n16;
+ n20 <= a(9) or b(9) when n18='1' else a(9) and b(9);
+ o(9) <= a(9) xor b(9) xor n18;
+ n22 <= a(10) or b(10) when n20='1' else a(10) and b(10);
+ o(10) <= a(10) xor b(10) xor n20;
+ n24 <= a(11) or b(11) when n22='1' else a(11) and b(11);
+ o(11) <= a(11) xor b(11) xor n22;
+ n26 <= a(12) or b(12) when n24='1' else a(12) and b(12);
+ o(12) <= a(12) xor b(12) xor n24;
+ n28 <= a(13) or b(13) when n26='1' else a(13) and b(13);
+ o(13) <= a(13) xor b(13) xor n26;
+ n30 <= a(14) or b(14) when n28='1' else a(14) and b(14);
+ o(14) <= a(14) xor b(14) xor n28;
+ n32 <= a(15) or b(15) when n30='1' else a(15) and b(15);
+ o(15) <= a(15) xor b(15) xor n30;
+ n34 <= a(16) or b(16) when n32='1' else a(16) and b(16);
+ o(16) <= a(16) xor b(16) xor n32;
+ n36 <= a(17) or b(17) when n34='1' else a(17) and b(17);
+ o(17) <= a(17) xor b(17) xor n34;
+ n38 <= a(18) or b(18) when n36='1' else a(18) and b(18);
+ o(18) <= a(18) xor b(18) xor n36;
+ n40 <= a(19) or b(19) when n38='1' else a(19) and b(19);
+ o(19) <= a(19) xor b(19) xor n38;
+ n42 <= a(20) or b(20) when n40='1' else a(20) and b(20);
+ o(20) <= a(20) xor b(20) xor n40;
+ n44 <= a(21) or b(21) when n42='1' else a(21) and b(21);
+ o(21) <= a(21) xor b(21) xor n42;
+ n46 <= a(22) or b(22) when n44='1' else a(22) and b(22);
+ o(22) <= a(22) xor b(22) xor n44;
+ n48 <= a(23) or b(23) when n46='1' else a(23) and b(23);
+ o(23) <= a(23) xor b(23) xor n46;
+ n50 <= a(24) or b(24) when n48='1' else a(24) and b(24);
+ o(24) <= a(24) xor b(24) xor n48;
+ n52 <= a(25) or b(25) when n50='1' else a(25) and b(25);
+ o(25) <= a(25) xor b(25) xor n50;
+ n54 <= a(26) or b(26) when n52='1' else a(26) and b(26);
+ o(26) <= a(26) xor b(26) xor n52;
+ n56 <= a(27) or b(27) when n54='1' else a(27) and b(27);
+ o(27) <= a(27) xor b(27) xor n54;
+ n58 <= a(28) or b(28) when n56='1' else a(28) and b(28);
+ o(28) <= a(28) xor b(28) xor n56;
+ n60 <= a(29) or b(29) when n58='1' else a(29) and b(29);
+ o(29) <= a(29) xor b(29) xor n58;
+ n62 <= a(30) or b(30) when n60='1' else a(30) and b(30);
+ o(30) <= a(30) xor b(30) xor n60;
+ cout <= a(31) or b(31) when n62='1' else a(31) and b(31);
+ o(31) <= a(31) xor b(31) xor n62;
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR mux_3
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity mux_3 is
+ port (d0: in std_logic_vector(2 downto 0);
+ d1: in std_logic_vector(2 downto 0);
+ cond: in std_logic;
+ o: out std_logic_vector(2 downto 0)
+ );
+
+end entity mux_3;
+
+architecture INTERFACE of mux_3 is
+
+begin
+ o(0) <= d1(0) when cond='1' else d0(0);
+ o(1) <= d1(1) when cond='1' else d0(1);
+ o(2) <= d1(2) when cond='1' else d0(2);
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR not_equal_32
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity not_equal_32 is
+ port (a: in std_logic_vector(31 downto 0);
+ b: in std_logic_vector(31 downto 0);
+ o: out std_logic
+ );
+
+end entity not_equal_32;
+
+architecture INTERFACE of not_equal_32 is
+ signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,
+ n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,
+ n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,
+ n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,
+ n58,n59,n60,n61,n62,n63,n64 : std_logic;
+begin
+ n1 <= a(0) xor b(0);
+ n2 <= a(1) xor b(1);
+ n3 <= a(2) xor b(2);
+ n4 <= a(3) xor b(3);
+ n5 <= a(4) xor b(4);
+ n6 <= a(5) xor b(5);
+ n7 <= a(6) xor b(6);
+ n8 <= a(7) xor b(7);
+ n9 <= a(8) xor b(8);
+ n10 <= a(9) xor b(9);
+ n11 <= a(10) xor b(10);
+ n12 <= a(11) xor b(11);
+ n13 <= a(12) xor b(12);
+ n14 <= a(13) xor b(13);
+ n15 <= a(14) xor b(14);
+ n16 <= a(15) xor b(15);
+ n17 <= a(16) xor b(16);
+ n18 <= a(17) xor b(17);
+ n19 <= a(18) xor b(18);
+ n20 <= a(19) xor b(19);
+ n21 <= a(20) xor b(20);
+ n22 <= a(21) xor b(21);
+ n23 <= a(22) xor b(22);
+ n24 <= a(23) xor b(23);
+ n25 <= a(24) xor b(24);
+ n26 <= a(25) xor b(25);
+ n27 <= a(26) xor b(26);
+ n28 <= a(27) xor b(27);
+ n29 <= a(28) xor b(28);
+ n30 <= a(29) xor b(29);
+ n31 <= a(30) xor b(30);
+ n32 <= a(31) xor b(31);
+ n33 <= n1 or n2;
+ n34 <= n3 or n4;
+ n35 <= n33 or n34;
+ n36 <= n5 or n6;
+ n37 <= n7 or n8;
+ n38 <= n36 or n37;
+ n39 <= n35 or n38;
+ n40 <= n9 or n10;
+ n41 <= n11 or n12;
+ n42 <= n40 or n41;
+ n43 <= n13 or n14;
+ n44 <= n15 or n16;
+ n45 <= n43 or n44;
+ n46 <= n42 or n45;
+ n47 <= n39 or n46;
+ n48 <= n17 or n18;
+ n49 <= n19 or n20;
+ n50 <= n48 or n49;
+ n51 <= n21 or n22;
+ n52 <= n23 or n24;
+ n53 <= n51 or n52;
+ n54 <= n50 or n53;
+ n55 <= n25 or n26;
+ n56 <= n27 or n28;
+ n57 <= n55 or n56;
+ n58 <= n29 or n30;
+ n59 <= n31 or n32;
+ n60 <= n58 or n59;
+ n61 <= n57 or n60;
+ n62 <= n54 or n61;
+ n63 <= n47 or n62;
+ n64 <= not n63;
+ o <= not n64;
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR not_equal_5
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity not_equal_5 is
+ port (a: in std_logic_vector(4 downto 0);
+ b: in std_logic_vector(4 downto 0);
+ o: out std_logic
+ );
+
+end entity not_equal_5;
+
+architecture INTERFACE of not_equal_5 is
+ signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10 : std_logic;
+begin
+ n1 <= a(0) xor b(0);
+ n2 <= a(1) xor b(1);
+ n3 <= a(2) xor b(2);
+ n4 <= a(3) xor b(3);
+ n5 <= a(4) xor b(4);
+ n6 <= n1 or n2;
+ n7 <= n4 or n5;
+ n8 <= n3 or n7;
+ n9 <= n6 or n8;
+ n10 <= not n9;
+ o <= not n10;
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR wide_dffrs_3
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity wide_dffrs_3 is
+ port (d: in std_logic_vector(2 downto 0);
+ set: in std_logic_vector(2 downto 0);
+ reset: in std_logic_vector(2 downto 0);
+ clock: in std_logic;
+ q: out std_logic_vector(2 downto 0)
+ );
+
+end entity wide_dffrs_3;
+
+architecture INTERFACE of wide_dffrs_3 is
+ procedure VERIFIC_DFFRS (d: in std_logic;
+ signal clk: in std_logic;
+ s: in std_logic;
+ r: in std_logic;
+ signal q: inout std_logic
+ ) is begin
+ if (s='1') then
+ q <= '1' ;
+ elsif (r='1') then
+ q <= '0' ;
+ elsif (clk'event and clk='1') then
+ q <= d ;
+ end if ;
+ end procedure VERIFIC_DFFRS;
+ signal \q[0]_c\,\q[1]_c\,\q[2]_c\ : std_logic;
+begin
+ q(2) <= \q[2]_c\;
+ q(1) <= \q[1]_c\;
+ q(0) <= \q[0]_c\;
+ i1: VERIFIC_DFFRS (d=>d(0),clk=>clock,s=>set(0),r=>reset(0),q=>\q[0]_c\);
+ i2: VERIFIC_DFFRS (d=>d(1),clk=>clock,s=>set(1),r=>reset(1),q=>\q[1]_c\);
+ i3: VERIFIC_DFFRS (d=>d(2),clk=>clock,s=>set(2),r=>reset(2),q=>\q[2]_c\);
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of OPERATOR wide_dffrs_5
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity wide_dffrs_5 is
+ port (d: in std_logic_vector(4 downto 0);
+ set: in std_logic_vector(4 downto 0);
+ reset: in std_logic_vector(4 downto 0);
+ clock: in std_logic;
+ q: out std_logic_vector(4 downto 0)
+ );
+
+end entity wide_dffrs_5;
+
+architecture INTERFACE of wide_dffrs_5 is
+ procedure VERIFIC_DFFRS (d: in std_logic;
+ signal clk: in std_logic;
+ s: in std_logic;
+ r: in std_logic;
+ signal q: inout std_logic
+ ) is begin
+ if (s='1') then
+ q <= '1' ;
+ elsif (r='1') then
+ q <= '0' ;
+ elsif (clk'event and clk='1') then
+ q <= d ;
+ end if ;
+ end procedure VERIFIC_DFFRS;
+ signal \q[0]_c\,\q[1]_c\,\q[2]_c\,\q[3]_c\,\q[4]_c\ : std_logic;
+begin
+ q(4) <= \q[4]_c\;
+ q(3) <= \q[3]_c\;
+ q(2) <= \q[2]_c\;
+ q(1) <= \q[1]_c\;
+ q(0) <= \q[0]_c\;
+ i1: VERIFIC_DFFRS (d=>d(0),clk=>clock,s=>set(0),r=>reset(0),q=>\q[0]_c\);
+ i2: VERIFIC_DFFRS (d=>d(1),clk=>clock,s=>set(1),r=>reset(1),q=>\q[1]_c\);
+ i3: VERIFIC_DFFRS (d=>d(2),clk=>clock,s=>set(2),r=>reset(2),q=>\q[2]_c\);
+ i4: VERIFIC_DFFRS (d=>d(3),clk=>clock,s=>set(3),r=>reset(3),q=>\q[3]_c\);
+ i5: VERIFIC_DFFRS (d=>d(4),clk=>clock,s=>set(4),r=>reset(4),q=>\q[4]_c\);
+
+end architecture INTERFACE;
+
+
+--
+-- Verific VHDL Description of module adc_1chrxdll_sync
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+library ecp5um ;
+use ecp5um.components.all ;
+
+entity adc_1chrxdll_sync is
+ port (rst: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(47)
+ sync_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(48)
+ update: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(49)
+ dll_lock: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(50)
+ dll_reset: out std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58)
+ uddcntln: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53)
+ freeze: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54)
+ stop: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55)
+ ddr_reset: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(56)
+ ready: out std_logic -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57)
+ );
+
+end entity adc_1chrxdll_sync; -- syn_module_defined=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(25)
+
+architecture adc_1chrxdll_sync of adc_1chrxdll_sync is
+ procedure VERIFIC_DFFRS (d: in std_logic;
+ signal clk: in std_logic;
+ s: in std_logic;
+ r: in std_logic;
+ signal q: inout std_logic
+ ) is begin
+ if (s='1') then
+ q <= '1' ;
+ elsif (r='1') then
+ q <= '0' ;
+ elsif (clk'event and clk='1') then
+ q <= d ;
+ end if ;
+ end procedure VERIFIC_DFFRS;
+ signal uddcntln_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53)
+ signal freeze_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54)
+ signal stop_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55)
+ signal ready_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57)
+ signal dll_reset_c : std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58)
+ signal ddr_reset_d : std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(75)
+ signal ctrl_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(77)
+ signal dll_lock_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(78)
+ signal ready_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(79)
+ signal cs_rx_sync : std_logic_vector(4 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(81)
+ signal ns_rx_sync : std_logic_vector(4 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(82)
+ signal dll_lock_q1 : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(84)
+ signal dll_lock_q2 : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(85)
+ signal not_uddcntln : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(87)
+ signal assert_stop : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(88)
+ signal not_reset : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(89)
+ signal not_stop : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(90)
+ signal not_freeze : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(91)
+ signal get_ready : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(92)
+ signal n303,pwr,n3,n4,n5,n6,n8 : std_logic;
+ signal n9 : std_logic_vector(4 downto 0);
+ signal n15 : std_logic_vector(4 downto 0);
+ signal n21 : std_logic;
+ signal n24 : std_logic_vector(4 downto 0);
+ signal n30 : std_logic_vector(4 downto 0);
+ signal n36 : std_logic_vector(4 downto 0);
+ signal n42,n44 : std_logic;
+ signal n45 : std_logic_vector(4 downto 0);
+ signal n51 : std_logic;
+ signal n53 : std_logic_vector(4 downto 0);
+ signal n59 : std_logic_vector(4 downto 0);
+ signal n65,n67 : std_logic;
+ signal n68 : std_logic_vector(4 downto 0);
+ signal n74,n75 : std_logic;
+ signal n76 : std_logic_vector(4 downto 0);
+ signal n82,n83,n84,n85,n86,n87,n88,n97,n98,n99 : std_logic;
+ signal n101 : std_logic_vector(31 downto 0);
+ signal n134 : std_logic_vector(2 downto 0);
+ signal n138,n139,n140,n141,n142 : std_logic;
+ signal n144 : std_logic_vector(31 downto 0);
+ signal n177 : std_logic_vector(2 downto 0);
+ signal n181 : std_logic_vector(2 downto 0);
+ signal n185 : std_logic_vector(2 downto 0);
+ signal n189,n190 : std_logic;
+ signal n192 : std_logic_vector(31 downto 0);
+ signal n225 : std_logic_vector(2 downto 0);
+ signal n229,n230,n231,n232,n233,n234,n235,n236,n237,n238,n239,
+ n240,n241,n242,n243,n244,n245,n246,n247,n248,n249,n250,n251,
+ n252,n253,n254,n255,n256,n257,n258,n259,n260,n261,n262 : std_logic;
+ signal n263 : std_logic_vector(2 downto 0);
+ signal n267 : std_logic_vector(2 downto 0);
+ signal n271 : std_logic_vector(2 downto 0);
+ signal gnd : std_logic; signal OPEN_net : std_logic_vector(0 to 87);
+
+begin
+ dll_reset <= dll_reset_c; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58)
+ uddcntln <= uddcntln_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53)
+ freeze <= freeze_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54)
+ stop <= stop_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55)
+ ready <= ready_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57)
+ n303 <= '0' ;
+ pwr <= '1' ;
+ ddr_reset <= cs_rx_sync(2) or ddr_reset_d; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(114)
+ equal_4: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303,
+ a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303,
+ a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303,
+ a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303,
+ a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303,
+ a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303,
+ a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1),a(0)=>dll_lock_cnt(0),
+ b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303,
+ b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303,
+ b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303,
+ b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303,
+ b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303,
+ b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>n303,b(0)=>pwr,
+ o=>n3); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124)
+ n4 <= not not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124)
+ n5 <= n3 and n4; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124)
+ equal_7: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303,
+ a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303,
+ a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303,
+ a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303,
+ a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303,
+ a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303,
+ a(3)=>n303,a(2)=>ready_cnt(2),a(1)=>ready_cnt(1),a(0)=>ready_cnt(0),
+ b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303,
+ b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303,
+ b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303,
+ b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303,
+ b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303,
+ b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>pwr,b(0)=>pwr,
+ o=>n6); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(128)
+ n8 <= n6 and get_ready; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(128)
+ mux_10: entity work.mux_5(INTERFACE) port map (d0(4)=>n303,d0(3)=>n303,
+ d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n303,d1(3)=>n303,
+ d1(2)=>n303,d1(1)=>pwr,d1(0)=>pwr,cond=>n8,o(4)=>n9(4),o(3)=>n9(3),
+ o(2)=>n9(2),o(1)=>n9(1),o(0)=>n9(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(135)
+ mux_11: entity work.mux_5(INTERFACE) port map (d0(4)=>n9(4),d0(3)=>n9(3),
+ d0(2)=>n9(2),d0(1)=>n9(1),d0(0)=>n9(0),d1(4)=>pwr,d1(3)=>n303,
+ d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>n5,o(4)=>n15(4),o(3)=>n15(3),
+ o(2)=>n15(2),o(1)=>n15(1),o(0)=>n15(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(135)
+ equal_12: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303,
+ a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303,
+ a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303,
+ a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303,
+ a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303,
+ a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303,
+ a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0),
+ b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303,
+ b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303,
+ b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303,
+ b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303,
+ b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303,
+ b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,
+ o=>n21); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(140)
+ mux_15: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303,
+ d0(2)=>n303,d0(1)=>n303,d0(0)=>n303,d1(4)=>n303,d1(3)=>n303,
+ d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>not_freeze,o(4)=>n24(4),
+ o(3)=>n24(3),o(2)=>n24(2),o(1)=>n24(1),o(0)=>n24(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(153)
+ mux_16: entity work.mux_5(INTERFACE) port map (d0(4)=>n24(4),d0(3)=>n24(3),
+ d0(2)=>n24(2),d0(1)=>n24(1),d0(0)=>n24(0),d1(4)=>pwr,d1(3)=>pwr,
+ d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>assert_stop,o(4)=>n30(4),
+ o(3)=>n30(3),o(2)=>n30(2),o(1)=>n30(1),o(0)=>n30(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(153)
+ mux_17: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303,
+ d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n30(4),d1(3)=>n30(3),
+ d1(2)=>n30(2),d1(1)=>n30(1),d1(0)=>n30(0),cond=>n21,o(4)=>n36(4),
+ o(3)=>n36(3),o(2)=>n36(2),o(1)=>n36(1),o(0)=>n36(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(158)
+ equal_18: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303,
+ a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303,
+ a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303,
+ a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303,
+ a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303,
+ a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303,
+ a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0),
+ b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303,
+ b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303,
+ b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303,
+ b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303,
+ b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303,
+ b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,
+ o=>n42); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(163)
+ n44 <= n42 and not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(163)
+ mux_21: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303,
+ d0(2)=>n303,d0(1)=>n303,d0(0)=>n303,d1(4)=>pwr,d1(3)=>n303,
+ d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>n44,o(4)=>n45(4),o(3)=>n45(3),
+ o(2)=>n45(2),o(1)=>n45(1),o(0)=>n45(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(170)
+ equal_22: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303,
+ a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303,
+ a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303,
+ a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303,
+ a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303,
+ a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303,
+ a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0),
+ b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303,
+ b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303,
+ b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303,
+ b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303,
+ b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303,
+ b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,
+ o=>n51); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(175)
+ mux_24: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr,
+ d0(2)=>pwr,d0(1)=>pwr,d0(0)=>n303,d1(4)=>pwr,d1(3)=>n303,d1(2)=>n303,
+ d1(1)=>pwr,d1(0)=>n303,cond=>not_stop,o(4)=>n53(4),o(3)=>n53(3),
+ o(2)=>n53(2),o(1)=>n53(1),o(0)=>n53(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(184)
+ mux_25: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr,
+ d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n53(4),d1(3)=>n53(3),
+ d1(2)=>n53(2),d1(1)=>n53(1),d1(0)=>n53(0),cond=>n51,o(4)=>n59(4),
+ o(3)=>n59(3),o(2)=>n59(2),o(1)=>n59(1),o(0)=>n59(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(189)
+ equal_26: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303,
+ a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303,
+ a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303,
+ a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303,
+ a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303,
+ a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303,
+ a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0),
+ b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303,
+ b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303,
+ b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303,
+ b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303,
+ b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303,
+ b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,
+ o=>n65); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(194)
+ n67 <= n65 and not_reset; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(194)
+ mux_29: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr,
+ d0(2)=>pwr,d0(1)=>pwr,d0(0)=>n303,d1(4)=>pwr,d1(3)=>pwr,d1(2)=>n303,
+ d1(1)=>pwr,d1(0)=>n303,cond=>n67,o(4)=>n68(4),o(3)=>n68(3),
+ o(2)=>n68(2),o(1)=>n68(1),o(0)=>n68(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(201)
+ n74 <= not dll_lock_q2; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(206)
+ n75 <= n74 or update; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(206)
+ mux_32: entity work.mux_5(INTERFACE) port map (d0(4)=>n303,d0(3)=>n303,
+ d0(2)=>n303,d0(1)=>pwr,d0(0)=>pwr,d1(4)=>n303,d1(3)=>n303,d1(2)=>n303,
+ d1(1)=>pwr,d1(0)=>n303,cond=>n75,o(4)=>n76(4),o(3)=>n76(3),
+ o(2)=>n76(2),o(1)=>n76(1),o(0)=>n76(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(213)
+ equal_33: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303,
+ b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n82); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(122)
+ equal_34: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr,
+ b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n83); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(138)
+ equal_35: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr,
+ b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n84); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(161)
+ equal_36: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr,
+ b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n85); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(173)
+ equal_37: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr,
+ b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n86); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(192)
+ equal_38: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303,
+ b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n87); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(204)
+ reduce_nor_39: entity work.reduce_nor_6(INTERFACE) port map (a(5)=>n82,
+ a(4)=>n83,a(3)=>n84,a(2)=>n85,a(1)=>n86,a(0)=>n87,o=>n88); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(221)
+ select_40: entity work.wide_select_7_35(INTERFACE) port map (sel(6)=>n82,
+ sel(5)=>n83,sel(4)=>n84,sel(3)=>n85,sel(2)=>n86,sel(1)=>n87,
+ sel(0)=>n88,data(34)=>n15(4),data(33)=>n15(3),data(32)=>n15(2),
+ data(31)=>n15(1),data(30)=>n15(0),data(29)=>n36(4),data(28)=>n36(3),
+ data(27)=>n36(2),data(26)=>n36(1),data(25)=>n36(0),data(24)=>n45(4),
+ data(23)=>n45(3),data(22)=>n45(2),data(21)=>n45(1),data(20)=>n45(0),
+ data(19)=>n59(4),data(18)=>n59(3),data(17)=>n59(2),data(16)=>n59(1),
+ data(15)=>n59(0),data(14)=>n68(4),data(13)=>n68(3),data(12)=>n68(2),
+ data(11)=>n68(1),data(10)=>n68(0),data(9)=>n76(4),data(8)=>n76(3),
+ data(7)=>n76(2),data(6)=>n76(1),data(5)=>n76(0),data(4)=>freeze_c,
+ data(3)=>stop_c,data(2)=>cs_rx_sync(2),data(1)=>uddcntln_c,data(0)=>ready_c,
+ o(4)=>ns_rx_sync(4),o(3)=>ns_rx_sync(3),o(2)=>ns_rx_sync(2),o(1)=>ns_rx_sync(1),
+ o(0)=>ns_rx_sync(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(221)
+ dll_lock_q2_112: VERIFIC_DFFRS (d=>dll_lock_q1,clk=>sync_clk,s=>n303,
+ r=>rst,q=>dll_lock_q2); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(238)
+ gnd <= '0' ;
+ n97 <= dll_lock_q2 and dll_lock; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264)
+ LessThan_44: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303,
+ a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1),a(0)=>dll_lock_cnt(0),
+ b(2)=>pwr,b(1)=>n303,b(0)=>pwr,o=>n98); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264)
+ n99 <= n97 and n98; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264)
+ add_46: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303,
+ a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,
+ a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,
+ a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,
+ a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,
+ a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,
+ a(4)=>n303,a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1),
+ a(0)=>dll_lock_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,
+ b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,
+ b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,
+ b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,
+ b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,
+ b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303,
+ b(0)=>pwr,o(31)=>OPEN_net(87),o(30)=>OPEN_net(86),o(29)=>OPEN_net(85),
+ o(28)=>OPEN_net(84),o(27)=>OPEN_net(83),o(26)=>OPEN_net(82),o(25)=>OPEN_net(81),
+ o(24)=>OPEN_net(80),o(23)=>OPEN_net(79),o(22)=>OPEN_net(78),o(21)=>OPEN_net(77),
+ o(20)=>OPEN_net(76),o(19)=>OPEN_net(75),o(18)=>OPEN_net(74),o(17)=>OPEN_net(73),
+ o(16)=>OPEN_net(72),o(15)=>OPEN_net(71),o(14)=>OPEN_net(70),o(13)=>OPEN_net(69),
+ o(12)=>OPEN_net(68),o(11)=>OPEN_net(67),o(10)=>OPEN_net(66),o(9)=>OPEN_net(65),
+ o(8)=>OPEN_net(64),o(7)=>OPEN_net(63),o(6)=>OPEN_net(62),o(5)=>OPEN_net(61),
+ o(4)=>OPEN_net(60),o(3)=>OPEN_net(59),o(2)=>n101(2),o(1)=>n101(1),
+ o(0)=>n101(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(266)
+ mux_47: entity work.mux_3(INTERFACE) port map (d0(2)=>dll_lock_cnt(2),
+ d0(1)=>dll_lock_cnt(1),d0(0)=>dll_lock_cnt(0),d1(2)=>n101(2),
+ d1(1)=>n101(1),d1(0)=>n101(0),cond=>n99,o(2)=>n134(2),o(1)=>n134(1),
+ o(0)=>n134(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(267)
+ not_equal_48: entity work.not_equal_32(INTERFACE) port map (a(31)=>n303,
+ a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,
+ a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,
+ a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,
+ a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,
+ a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,
+ a(4)=>n303,a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1),
+ a(0)=>dll_lock_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,
+ b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,
+ b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,
+ b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,
+ b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,
+ b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>n303,
+ b(0)=>pwr,o=>n138); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(271)
+ equal_49: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303,
+ a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303,
+ a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303,
+ a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303,
+ a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303,
+ a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303,
+ a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0),
+ b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303,
+ b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303,
+ b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303,
+ b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303,
+ b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303,
+ b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,
+ o=>n139); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275)
+ not_equal_50: entity work.not_equal_5(INTERFACE) port map (a(4)=>freeze_c,
+ a(3)=>stop_c,a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,
+ b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n140); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275)
+ n141 <= n139 and n140; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275)
+ LessThan_52: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303,
+ a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0),b(2)=>pwr,
+ b(1)=>n303,b(0)=>n303,o=>n142); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(280)
+ add_53: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303,
+ a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,
+ a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,
+ a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,
+ a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,
+ a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,
+ a(4)=>n303,a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0),
+ b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303,
+ b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303,
+ b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303,
+ b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303,
+ b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303,
+ b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>pwr,
+ o(31)=>OPEN_net(58),o(30)=>OPEN_net(57),o(29)=>OPEN_net(56),o(28)=>OPEN_net(55),
+ o(27)=>OPEN_net(54),o(26)=>OPEN_net(53),o(25)=>OPEN_net(52),o(24)=>OPEN_net(51),
+ o(23)=>OPEN_net(50),o(22)=>OPEN_net(49),o(21)=>OPEN_net(48),o(20)=>OPEN_net(47),
+ o(19)=>OPEN_net(46),o(18)=>OPEN_net(45),o(17)=>OPEN_net(44),o(16)=>OPEN_net(43),
+ o(15)=>OPEN_net(42),o(14)=>OPEN_net(41),o(13)=>OPEN_net(40),o(12)=>OPEN_net(39),
+ o(11)=>OPEN_net(38),o(10)=>OPEN_net(37),o(9)=>OPEN_net(36),o(8)=>OPEN_net(35),
+ o(7)=>OPEN_net(34),o(6)=>OPEN_net(33),o(5)=>OPEN_net(32),o(4)=>OPEN_net(31),
+ o(3)=>OPEN_net(30),o(2)=>n144(2),o(1)=>n144(1),o(0)=>n144(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(282)
+ mux_54: entity work.mux_3(INTERFACE) port map (d0(2)=>ctrl_cnt(2),d0(1)=>ctrl_cnt(1),
+ d0(0)=>ctrl_cnt(0),d1(2)=>n144(2),d1(1)=>n144(1),d1(0)=>n144(0),
+ cond=>n142,o(2)=>n177(2),o(1)=>n177(1),o(0)=>n177(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283)
+ mux_55: entity work.mux_3(INTERFACE) port map (d0(2)=>n177(2),d0(1)=>n177(1),
+ d0(0)=>n177(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n141,
+ o(2)=>n181(2),o(1)=>n181(1),o(0)=>n181(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283)
+ mux_56: entity work.mux_3(INTERFACE) port map (d0(2)=>n181(2),d0(1)=>n181(1),
+ d0(0)=>n181(0),d1(2)=>n303,d1(1)=>pwr,d1(0)=>pwr,cond=>n138,
+ o(2)=>n185(2),o(1)=>n185(1),o(0)=>n185(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283)
+ LessThan_57: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303,
+ a(2)=>ready_cnt(2),a(1)=>ready_cnt(1),a(0)=>ready_cnt(0),b(2)=>pwr,
+ b(1)=>pwr,b(0)=>pwr,o=>n189); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(287)
+ n190 <= get_ready and n189; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(287)
+ add_59: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303,
+ a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,
+ a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,
+ a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,
+ a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,
+ a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,
+ a(4)=>n303,a(3)=>n303,a(2)=>ready_cnt(2),a(1)=>ready_cnt(1),
+ a(0)=>ready_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,
+ b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,
+ b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,
+ b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,
+ b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,
+ b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303,
+ b(0)=>pwr,o(31)=>OPEN_net(29),o(30)=>OPEN_net(28),o(29)=>OPEN_net(27),
+ o(28)=>OPEN_net(26),o(27)=>OPEN_net(25),o(26)=>OPEN_net(24),o(25)=>OPEN_net(23),
+ o(24)=>OPEN_net(22),o(23)=>OPEN_net(21),o(22)=>OPEN_net(20),o(21)=>OPEN_net(19),
+ o(20)=>OPEN_net(18),o(19)=>OPEN_net(17),o(18)=>OPEN_net(16),o(17)=>OPEN_net(15),
+ o(16)=>OPEN_net(14),o(15)=>OPEN_net(13),o(14)=>OPEN_net(12),o(13)=>OPEN_net(11),
+ o(12)=>OPEN_net(10),o(11)=>OPEN_net(9),o(10)=>OPEN_net(8),o(9)=>OPEN_net(7),
+ o(8)=>OPEN_net(6),o(7)=>OPEN_net(5),o(6)=>OPEN_net(4),o(5)=>OPEN_net(3),
+ o(4)=>OPEN_net(2),o(3)=>OPEN_net(1),o(2)=>n192(2),o(1)=>n192(1),
+ o(0)=>n192(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(290)
+ mux_60: entity work.mux_3(INTERFACE) port map (d0(2)=>ready_cnt(2),d0(1)=>ready_cnt(1),
+ d0(0)=>ready_cnt(0),d1(2)=>n192(2),d1(1)=>n192(1),d1(0)=>n192(0),
+ cond=>n190,o(2)=>n225(2),o(1)=>n225(1),o(0)=>n225(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(291)
+ equal_61: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr,
+ b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n229); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294)
+ equal_62: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4),
+ a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0),
+ b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n230); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294)
+ n231 <= n229 and n230; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294)
+ n232 <= pwr when n231='1' else not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(297)
+ equal_65: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr,
+ b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n233); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300)
+ equal_66: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4),
+ a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0),
+ b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n234); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300)
+ n235 <= n233 and n234; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300)
+ n236 <= pwr when n235='1' else assert_stop; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(303)
+ equal_69: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr,
+ b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n237); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306)
+ equal_70: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4),
+ a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0),
+ b(4)=>pwr,b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n238); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306)
+ n239 <= n237 and n238; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306)
+ n240 <= pwr when n239='1' else not_reset; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(309)
+ equal_73: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr,
+ b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n241); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312)
+ equal_74: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4),
+ a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0),
+ b(4)=>pwr,b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n242); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312)
+ n243 <= n241 and n242; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312)
+ n244 <= pwr when n243='1' else not_stop; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(315)
+ equal_77: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr,
+ b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n245); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318)
+ equal_78: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4),
+ a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0),
+ b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n246); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318)
+ n247 <= n245 and n246; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318)
+ n248 <= pwr when n247='1' else not_freeze; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(322)
+ n249 <= n303 when n247='1' else n236; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(322)
+ equal_82: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr,
+ b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n250); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325)
+ equal_83: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4),
+ a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0),
+ b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n251); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325)
+ n252 <= n250 and n251; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325)
+ n253 <= pwr when n252='1' else get_ready; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(328)
+ equal_86: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c,
+ a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303,
+ b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n254); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332)
+ equal_87: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4),
+ a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0),
+ b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n255); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332)
+ n256 <= n254 and n255; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332)
+ n257 <= n303 when n256='1' else n248; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344)
+ n258 <= n303 when n256='1' else n249; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344)
+ n259 <= n303 when n256='1' else n244; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344)
+ n260 <= n303 when n256='1' else n240; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344)
+ n261 <= n303 when n256='1' else n232; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344)
+ n262 <= n303 when n256='1' else n253; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344)
+ mux_95: entity work.mux_3(INTERFACE) port map (d0(2)=>n225(2),d0(1)=>n225(1),
+ d0(0)=>n225(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256,
+ o(2)=>n263(2),o(1)=>n263(1),o(0)=>n263(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344)
+ mux_96: entity work.mux_3(INTERFACE) port map (d0(2)=>n134(2),d0(1)=>n134(1),
+ d0(0)=>n134(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256,
+ o(2)=>n267(2),o(1)=>n267(1),o(0)=>n267(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344)
+ mux_97: entity work.mux_3(INTERFACE) port map (d0(2)=>n185(2),d0(1)=>n185(1),
+ d0(0)=>n185(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256,
+ o(2)=>n271(2),o(1)=>n271(1),o(0)=>n271(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344)
+ ctrl_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n271(2),
+ d(1)=>n271(1),d(0)=>n271(0),set(2)=>n303,set(1)=>n303,set(0)=>n303,
+ reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>ctrl_cnt(2),
+ q(1)=>ctrl_cnt(1),q(0)=>ctrl_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+ dll_lock_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n267(2),
+ d(1)=>n267(1),d(0)=>n267(0),set(2)=>n303,set(1)=>n303,set(0)=>n303,
+ reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>dll_lock_cnt(2),
+ q(1)=>dll_lock_cnt(1),q(0)=>dll_lock_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+ ready_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n263(2),
+ d(1)=>n263(1),d(0)=>n263(0),set(2)=>n303,set(1)=>n303,set(0)=>n303,
+ reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>ready_cnt(2),
+ q(1)=>ready_cnt(1),q(0)=>ready_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+ ddr_reset_d_118: VERIFIC_DFFRS (d=>n303,clk=>sync_clk,s=>rst,r=>gnd,
+ q=>ddr_reset_d); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+ dll_reset_119: VERIFIC_DFFRS (d=>n256,clk=>sync_clk,s=>rst,r=>gnd,q=>dll_reset_c); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+ not_uddcntln_120: VERIFIC_DFFRS (d=>n261,clk=>sync_clk,s=>n303,r=>rst,
+ q=>not_uddcntln); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+ assert_stop_121: VERIFIC_DFFRS (d=>n258,clk=>sync_clk,s=>n303,r=>rst,
+ q=>assert_stop); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+ not_reset_122: VERIFIC_DFFRS (d=>n260,clk=>sync_clk,s=>n303,r=>rst,q=>not_reset); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+ not_stop_123: VERIFIC_DFFRS (d=>n259,clk=>sync_clk,s=>n303,r=>rst,q=>not_stop); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+ not_freeze_124: VERIFIC_DFFRS (d=>n257,clk=>sync_clk,s=>n303,r=>rst,
+ q=>not_freeze); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+ get_ready_125: VERIFIC_DFFRS (d=>n262,clk=>sync_clk,s=>n303,r=>rst,q=>get_ready); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+ dll_lock_q1_111: VERIFIC_DFFRS (d=>dll_lock,clk=>sync_clk,s=>n303,r=>rst,
+ q=>dll_lock_q1); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(238)
+ cs_rx_sync_c: entity work.wide_dffrs_5(INTERFACE) port map (d(4)=>ns_rx_sync(4),
+ d(3)=>ns_rx_sync(3),d(2)=>ns_rx_sync(2),d(1)=>ns_rx_sync(1),d(0)=>ns_rx_sync(0),
+ set(4)=>n303,set(3)=>n303,set(2)=>n303,set(1)=>rst,set(0)=>n303,
+ reset(4)=>rst,reset(3)=>rst,reset(2)=>rst,reset(1)=>gnd,reset(0)=>rst,
+ clock=>sync_clk,q(4)=>freeze_c,q(3)=>stop_c,q(2)=>cs_rx_sync(2),
+ q(1)=>uddcntln_c,q(0)=>ready_c); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346)
+
+end architecture adc_1chrxdll_sync; -- syn_module_defined=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(25)
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity adc_1ch is
+ port (
+ clkin: in std_logic;
+ dcntl: out std_logic_vector(7 downto 0);
+ ready: out std_logic;
+ sclk: out std_logic;
+ sync_clk: in std_logic;
+ sync_reset: in std_logic;
+ update: in std_logic;
+ data_cflag: out std_logic_vector(1 downto 0);
+ data_direction: in std_logic_vector(1 downto 0);
+ data_loadn: in std_logic_vector(1 downto 0);
+ data_move: in std_logic_vector(1 downto 0);
+ datain: in std_logic_vector(1 downto 0);
+ q: out std_logic_vector(3 downto 0));
+end adc_1ch;
+
+architecture Structure of adc_1ch is
+
+ -- internal signal declarations
+ signal stop: std_logic;
+ signal scuba_vlo: std_logic;
+ signal dll_lock: std_logic;
+ signal freeze: std_logic;
+ signal uddcntln: std_logic;
+ signal dll_reset: std_logic;
+ signal clock_cflag: std_logic;
+ signal clock_direction: std_logic;
+ signal clock_move: std_logic;
+ signal clock_loadn: std_logic;
+ signal ddrdel: std_logic;
+ signal buf_clkin: std_logic;
+ signal qb1: std_logic;
+ signal qa1: std_logic;
+ signal qb0: std_logic;
+ signal qa0: std_logic;
+ signal reset: std_logic;
+ signal sclk_t: std_logic;
+ signal dataini_t1: std_logic;
+ signal dataini_t0: std_logic;
+ signal buf_dataini1: std_logic;
+ signal buf_dataini0: std_logic;
+
+ component adc_1chrxdll_sync
+ port (rst: in std_logic; sync_clk: in std_logic;
+ update: in std_logic; dll_lock: in std_logic;
+ dll_reset: out std_logic; uddcntln: out std_logic;
+ freeze: out std_logic; stop: out std_logic;
+ ddr_reset: out std_logic; ready: out std_logic);
+ end component;
+ attribute IO_TYPE : string;
+ attribute IO_TYPE of Inst5_IB : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB1 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB0 : label is "LVDS";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ Inst5_IB: IB
+ port map (I=>clkin, O=>buf_clkin);
+
+ Inst_rxdll_sync: adc_1chrxdll_sync
+ port map (rst => sync_reset, sync_clk => sync_clk, update => update,
+ dll_lock => dll_lock, dll_reset => dll_reset, uddcntln => uddcntln,
+ freeze => freeze, stop => stop, ddr_reset => reset,
+ ready => ready);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ Inst4_DDRDLLA: DDRDLLA
+ generic map (FORCE_MAX_DELAY=> "NO")
+ port map (CLK=>sclk_t, RST=>dll_reset, UDDCNTLN=>uddcntln,
+ FREEZE=>freeze, DDRDEL=>ddrdel, LOCK=>dll_lock,
+ DCNTL7=>dcntl(7), DCNTL6=>dcntl(6), DCNTL5=>dcntl(5),
+ DCNTL4=>dcntl(4), DCNTL3=>dcntl(3), DCNTL2=>dcntl(2),
+ DCNTL1=>dcntl(1), DCNTL0=>dcntl(0));
+
+ Inst3_DLLDELD: DLLDELD
+ port map (A=>buf_clkin, DDRDEL=>ddrdel, LOADN=>clock_loadn,
+ MOVE=>clock_move, DIRECTION=>clock_direction, Z=>sclk_t,
+ CFLAG=>clock_cflag);
+
+ Inst2_IDDRX1F1: IDDRX1F
+ port map (D=>dataini_t1, SCLK=>sclk_t, RST=>reset, Q0=>qa1,
+ Q1=>qb1);
+
+ Inst2_IDDRX1F0: IDDRX1F
+ port map (D=>dataini_t0, SCLK=>sclk_t, RST=>reset, Q0=>qa0,
+ Q1=>qb0);
+
+ udel_dataini1: DELAYF
+ generic map (DEL_VALUE=> 11, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini1, LOADN=>data_loadn(1),
+ MOVE=>data_move(1), DIRECTION=>data_direction(1),
+ Z=>dataini_t1, CFLAG=>data_cflag(1));
+
+ udel_dataini0: DELAYF
+ generic map (DEL_VALUE=> 11, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini0, LOADN=>data_loadn(0),
+ MOVE=>data_move(0), DIRECTION=>data_direction(0),
+ Z=>dataini_t0, CFLAG=>data_cflag(0));
+
+ Inst1_IB1: IB
+ port map (I=>datain(1), O=>buf_dataini1);
+
+ Inst1_IB0: IB
+ port map (I=>datain(0), O=>buf_dataini0);
+
+ sclk <= sclk_t;
+ q(3) <= qb1;
+ q(2) <= qa1;
+ q(1) <= qb0;
+ q(0) <= qa0;
+ clock_direction <= scuba_vlo;
+ clock_move <= scuba_vlo;
+ clock_loadn <= uddcntln;
+end Structure;
jspc29 / trb5sc.git / commitdiff