Init config prevents sim messages

diff --git a/ADC/sim/tb_adcprocessor_cfd.vhd b/ADC/sim/tb_adcprocessor_cfd.vhd
index 65ae5ee6dc3532b029d08096b257b8966338722e..fb51cffa03fa4dd1eff4a80547ab574081b0c89a 100644 (file)
--- a/ADC/sim/tb_adcprocessor_cfd.vhd
+++ b/ADC/sim/tb_adcprocessor_cfd.vhd
@@ -17,7 +17,7 @@ architecture tb_arch of tb is
   signal adc_data    : std_logic_vector(39 downto 0) := (others => '0');
   signal stop_in     : std_logic                     := '0';
   signal trigger_out : std_logic                     := '0';
-  signal config      : cfg_cfd_t;
+  signal config      : cfg_cfd_t := cfg_cfd_t_INIT;
   signal readout_rx  : READOUT_RX;
   signal readout_tx  : READOUT_TX;
   signal control     : std_logic_vector(63 downto 0);

diff --git a/ADC/source/adc_package.vhd b/ADC/source/adc_package.vhd
index 4c95ec26db6389ad444855959362ac70dbd5f793..5bb492f0ce238ea546abbeb7ae2c298456b1eac7 100644 (file)
--- a/ADC/source/adc_package.vhd
+++ b/ADC/source/adc_package.vhd
@@ -59,6 +59,23 @@ package adc_package is
     ChannelDisable   : std_logic_vector(47 downto 0);
   end record;
 
+  constant cfg_cfd_t_INIT : cfg_cfd_t := (
+    InputThreshold   => (others => '0'),
+    PolarityInvert   => '0',
+    BaselineAverage  => (others => '0'),
+    BaselineAlwaysOn => '0',
+    CFDDelay         => (others => '0'),
+    CFDMult          => (others => '0'),
+    CFDMultDly       => (others => '0'),
+    IntegrateWindow  => (others => '0'),
+    TriggerDelay     => (others => '0'),
+    CheckWord1       => (others => '0'),
+    CheckWord2       => (others => '0'),
+    CheckWordEnable  => '0',
+    TriggerEnable    => (others => '0'),
+    ChannelDisable   => (others => '0')
+  );
+
   type debug_cfd_t is record
     InvalidWordCount : unsigned(31 downto 0);
     Baseline         : unsigned(RESOLUTION - 1 downto 0);