--- /dev/null
+-- this is a dummy apl, just sending data into an active api
+
+--THIS IS NOT WORKING !!!!
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+
+entity trb_net16_dummy_passive_apl is
+ generic (
+ TARGET_ADDRESS : std_logic_vector (15 downto 0) := x"ffff";
+ PREFILL_LENGTH : integer := 3;
+ TRANSFER_LENGTH : integer := 3 -- length of dummy data
+ -- might not work with transfer_length > api_fifo
+ -- because of incorrect handling of fifo_full_in!
+ -- shorttransfer is not working too
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- APL Transmitter port
+ APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ APL_WRITE_OUT: out std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_IN: in std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_OUT: out std_logic; --
+ APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_OUT: out std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+ -- Receiver port
+ APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_IN:in std_logic_vector (1 downto 0);
+ APL_TYP_IN: in std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_IN: in std_logic; -- Data word is valid and might be read out
+ APL_READ_OUT: out std_logic; -- Read data word
+ -- APL Control port
+ APL_RUN_IN: in std_logic; -- Data transfer is running
+-- APL_MY_ADDRESS_OUT: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_IN: in std_logic_vector (7 downto 0)
+ );
+end entity;
+
+architecture trb_net16_dummy_passive_apl_arch of trb_net16_dummy_passive_apl is
+
+ type SENDER_STATE is (IDLE, WRITING, RUNNING, WAITING, MY_ERROR);
+ signal current_state, next_state : SENDER_STATE;
+ signal next_counter, reg_counter : std_logic_vector(15 downto 0);
+ signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(15 downto 0);
+ signal buf_APL_PACKET_NUM_OUT, next_APL_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
+ signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic;
+ signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic;
+ signal next_packet_counter, packet_counter : std_logic_vector(1 downto 0);
+
+begin
+ APL_READ_OUT <= '1'; --just read, do not check
+ APL_DTYPE_OUT <= x"1";
+ APL_ERROR_PATTERN_OUT <= x"12345678";
+ APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS;
+ --APL_DATA_OUT <= reg_counter;
+
+ CHECK_1:if TRANSFER_LENGTH >0 generate
+ APL_SHORT_TRANSFER_OUT <= '0';
+ end generate;
+ CHECK_2:if TRANSFER_LENGTH =0 generate
+ APL_SHORT_TRANSFER_OUT <= '1';
+ end generate;
+
+
+ SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN, RESET, packet_counter, buf_APL_SEND_OUT)
+ begin -- process
+ next_APL_SEND_OUT <= buf_APL_SEND_OUT;
+ next_state <= MY_ERROR;
+ next_counter <= reg_counter;
+ next_APL_PACKET_NUM_OUT <= packet_counter;
+ next_APL_WRITE_OUT <= '0';
+ next_APL_DATA_OUT <= (others => '0');
+ next_packet_counter <= packet_counter;
+-------------------------------------------------------------------------
+-- IDLE
+-------------------------------------------------------------------------
+ if current_state = IDLE then
+ if APL_FIFO_FULL_IN = '1' or reg_counter = PREFILL_LENGTH then
+ next_state <= RUNNING;
+ next_APL_SEND_OUT <= '0';
+ else
+ if buf_APL_SEND_OUT = '1' or APL_RUN_IN = '0' then
+ next_APL_SEND_OUT <= '1';
+ end if;
+ next_state <= WRITING;
+ next_APL_DATA_OUT <= (1 => '1', others => '0');
+ next_APL_WRITE_OUT <= '1';
+ next_packet_counter <= "01";
+ end if;
+-------------------------------------------------------------------------
+-- WRITING
+-------------------------------------------------------------------------
+ elsif current_state = WRITING then
+ next_state <= WRITING;
+ if packet_counter = "01" then
+ next_APL_WRITE_OUT <= '1';
+ next_APL_DATA_OUT <= (0 => '1', others => '0');
+ next_packet_counter <= "10";
+ elsif packet_counter = "10" then
+ next_APL_WRITE_OUT <= '1';
+ next_APL_DATA_OUT <= reg_counter;
+ next_packet_counter <= "11";
+ elsif packet_counter <= "11" then
+ next_state <= IDLE;
+ next_packet_counter <= "01";
+ next_counter <= reg_counter +1;
+ end if;
+-----------------------------------------------------------------------
+-- RUNNING
+-----------------------------------------------------------------------
+ elsif current_state = RUNNING then
+ next_APL_SEND_OUT <= '0';
+ if reg_counter = TRANSFER_LENGTH then
+ next_state <= WAITING;
+ else
+ next_state <= RUNNING;
+ if APL_FIFO_FULL_IN = '0' then
+ next_counter <= reg_counter +1;
+ end if;
+ end if;
+-----------------------------------------------------------------------
+-- WAITING
+-----------------------------------------------------------------------
+ elsif current_state = WAITING then
+ if not (APL_TYP_IN = TYPE_TRM and APL_DATAREADY_IN = '1') then
+ next_state <= WAITING;
+ else
+ next_state <= IDLE;
+ next_counter <= (others => '0');
+ end if;
+ end if; -- end state switch
+ if RESET = '1' then
+ next_APL_WRITE_OUT <= '0';
+ end if;
+ end process;
+
+APL_DATA_OUT(15 downto 0) <= buf_APL_DATA_OUT;
+APL_PACKET_NUM_OUT <= packet_counter;
+APL_WRITE_OUT <= buf_APL_WRITE_OUT;
+APL_SEND_OUT <= buf_APL_SEND_OUT;
+
+ CLK_REG: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= WAITING;
+ reg_counter <= (others => '0');
+ packet_counter <= "01";
+ buf_APL_DATA_OUT <= (others => '0');
+ buf_APL_PACKET_NUM_OUT <= "00";
+ buf_APL_WRITE_OUT <= '0';
+ buf_APL_SEND_OUT <= '0';
+ elsif CLK_EN = '1' then
+ reg_counter <= next_counter;
+ current_state <= next_state;
+ packet_counter <= next_packet_counter;
+ buf_APL_DATA_OUT <= next_APL_DATA_OUT;
+ buf_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT;
+ buf_APL_WRITE_OUT <= next_APL_WRITE_OUT;
+ buf_APL_SEND_OUT <= next_APL_SEND_OUT;
+ end if;
+ end if;
+ end process;
+
+end architecture;
--- /dev/null
+-- an passive api together with an iobuf
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+--Entity decalaration for clock generator
+entity trb_net16_passive_apimbuf is
+
+ generic (INIT_DEPTH : integer := 1; -- Depth of the FIFO, 2^(n+1), if
+ -- the initibuf
+ REPLY_DEPTH : integer := 1; -- or the replyibuf
+ FIFO_TO_INT_DEPTH : integer := 1; -- Depth of the FIFO, 2^(n+1),
+ -- for the direction to
+ -- internal world
+ FIFO_TO_APL_DEPTH : integer := 1; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_READ_IN: in std_logic; -- Media is reading
+
+ MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+
+ -- APL Transmitter port
+ APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN: in std_logic; --
+ APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN: in std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN: in std_logic; -- Read data word
+
+ -- APL Control port
+ APL_RUN_OUT: out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
+
+ -- Status and control port => just coming from the iobuf for debugging
+ STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ STAT_api_control_signals: out std_logic_vector(31 downto 0);
+ STAT_MPLEX: out std_logic_vector(31 downto 0);
+ CTRL_GEN: in std_logic_vector (31 downto 0);
+ CTRL_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
+ MPLEX_CTRL: in std_logic_vector (31 downto 0);
+ API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
+ API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_passive_apimbuf_arch of trb_net16_passive_apimbuf is
+
+component trb_net16_iobuf is
+
+ generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
+ -- the initibuf
+ REPLY_DEPTH : integer := 3); -- or the replyibuf
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic; -- Media is reading
+
+ MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic; -- Media is reading
+
+ MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT: out std_logic;
+ INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_INIT_READ_IN: in std_logic;
+
+ INT_INIT_DATAREADY_IN: in std_logic;
+ INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_INIT_READ_OUT: out std_logic;
+
+ INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_REPLY_DATAREADY_OUT: out std_logic;
+ INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_REPLY_READ_IN: in std_logic;
+
+ INT_REPLY_DATAREADY_IN: in std_logic;
+ INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_REPLY_READ_OUT: out std_logic;
+
+ -- Status and control port
+ STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ CTRL_GEN: in std_logic_vector (31 downto 0);
+ CTRL_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
+ );
+end component;
+
+component trb_net16_passive_api is
+
+ generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
+ -- for the direction to
+ -- internal world
+ FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- APL Transmitter port
+ APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN: in std_logic; --
+ APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN: in std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN: in std_logic; -- Read data word
+
+ -- APL Control port
+ APL_RUN_OUT: out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
+
+ -- Internal direction port
+ -- This is just a clone from trb_net_iobuf
+
+ INT_INIT_DATAREADY_OUT: out std_logic;
+ INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_INIT_READ_IN: in std_logic;
+
+ INT_INIT_DATAREADY_IN: in std_logic;
+ INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_INIT_READ_OUT: out std_logic;
+
+
+ INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_REPLY_DATAREADY_OUT: out std_logic;
+ INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_REPLY_READ_IN: in std_logic;
+
+ INT_REPLY_DATAREADY_IN: in std_logic;
+ INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_REPLY_READ_OUT: out std_logic;
+
+ -- Status and control port
+ STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
+ );
+end component;
+
+
+
+component trb_net16_io_multiplexer is
+
+ generic (BUS_WIDTH : integer := 16;
+ MULT_WIDTH : integer := 1);
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in std_logic;
+ MED_DATA_IN: in std_logic_vector (BUS_WIDTH-1 downto 0);
+ -- highest bits are mult.
+ MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_READ_OUT: out std_logic;
+
+ MED_DATAREADY_OUT: out std_logic;
+ MED_DATA_OUT: out std_logic_vector (BUS_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_READ_IN: in std_logic;
+
+ -- Internal direction port
+ INT_DATAREADY_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
+ INT_DATA_OUT: out std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
+ INT_READ_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
+
+ INT_DATAREADY_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
+ INT_DATA_IN: in std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
+ INT_READ_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
+
+ -- Status and control port
+ CTRL: in std_logic_vector (31 downto 0);
+ STAT: out std_logic_vector (31 downto 0)
+ );
+end component;
+
+signal apl_to_buf_INIT_DATAREADY: std_logic;
+signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0);
+signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0);
+signal apl_to_buf_INIT_READ : std_logic;
+
+signal buf_to_apl_INIT_DATAREADY: std_logic;
+signal buf_to_apl_INIT_DATA : std_logic_vector (15 downto 0);
+signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (1 downto 0);
+signal buf_to_apl_INIT_READ : std_logic;
+
+signal apl_to_buf_REPLY_DATAREADY: std_logic;
+signal apl_to_buf_REPLY_DATA : std_logic_vector (15 downto 0);
+signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (1 downto 0);
+signal apl_to_buf_REPLY_READ : std_logic;
+
+signal buf_to_apl_REPLY_DATAREADY: std_logic;
+signal buf_to_apl_REPLY_DATA : std_logic_vector (15 downto 0);
+signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (1 downto 0);
+signal buf_to_apl_REPLY_READ : std_logic;
+
+-- for the connection to the multiplexer
+signal MED_INIT_DATAREADY_OUT : std_logic;
+signal MED_INIT_DATA_OUT : std_logic_vector (15 downto 0);
+signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (1 downto 0);
+signal MED_INIT_READ_IN : std_logic;
+
+signal MED_INIT_DATAREADY_IN : std_logic;
+signal MED_INIT_DATA_IN : std_logic_vector (15 downto 0);
+signal MED_INIT_PACKET_NUM_IN : std_logic_vector (1 downto 0);
+signal MED_INIT_READ_OUT : std_logic;
+
+signal MED_REPLY_DATAREADY_OUT : std_logic;
+signal MED_REPLY_DATA_OUT : std_logic_vector (15 downto 0);
+signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0);
+signal MED_REPLY_READ_IN : std_logic;
+
+signal MED_REPLY_DATAREADY_IN : std_logic;
+signal MED_REPLY_DATA_IN : std_logic_vector (15 downto 0);
+signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0);
+signal MED_REPLY_READ_OUT : std_logic;
+
+signal m_DATAREADY_OUT : std_logic_vector (1 downto 0);
+signal m_DATA_OUT : std_logic_vector (31 downto 0);
+signal m_PACKET_NUM_OUT: std_logic_vector (3 downto 0);
+signal m_READ_IN : std_logic_vector (1 downto 0);
+
+signal m_DATAREADY_IN : std_logic_vector (1 downto 0);
+signal m_DATA_IN : std_logic_vector (31 downto 0);
+signal m_PACKET_NUM_IN : std_logic_vector (3 downto 0);
+signal m_READ_OUT : std_logic_vector (1 downto 0);
+
+begin
+
+ m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT;
+ m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT;
+ m_DATA_OUT(15 downto 0) <= MED_INIT_DATA_OUT;
+ m_DATA_OUT(31 downto 16) <= MED_REPLY_DATA_OUT;
+ m_PACKET_NUM_OUT(1 downto 0) <= MED_INIT_PACKET_NUM_OUT;
+ m_PACKET_NUM_OUT(3 downto 2) <= MED_REPLY_PACKET_NUM_OUT;
+ MED_INIT_READ_IN <= m_READ_IN(0);
+ MED_REPLY_READ_IN <= m_READ_IN(1);
+
+ MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0);
+ MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1);
+ MED_INIT_DATA_IN <= m_DATA_IN(15 downto 0);
+ MED_REPLY_DATA_IN <= m_DATA_IN(31 downto 16);
+ MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(1 downto 0);
+ MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(3 downto 2);
+ m_READ_OUT(0) <= MED_INIT_READ_OUT;
+ m_READ_OUT(1) <= MED_REPLY_READ_OUT;
+
+
+ ACTIVE_API: trb_net16_passive_api
+
+ generic map (FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH)
+
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_WRITE_IN => APL_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
+
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+
+ -- Internal direction port
+ -- connect via private signals
+
+ INT_INIT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY,
+ INT_INIT_DATA_OUT => apl_to_buf_INIT_DATA,
+ INT_INIT_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM,
+ INT_INIT_READ_IN => apl_to_buf_INIT_READ,
+
+ INT_INIT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
+ INT_INIT_DATA_IN => buf_to_apl_INIT_DATA,
+ INT_INIT_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM,
+ INT_INIT_READ_OUT => buf_to_apl_INIT_READ,
+
+ INT_REPLY_HEADER_IN => '0',
+ INT_REPLY_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY,
+ INT_REPLY_DATA_OUT => apl_to_buf_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM,
+ INT_REPLY_READ_IN => apl_to_buf_REPLY_READ,
+
+ INT_REPLY_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
+ INT_REPLY_DATA_IN => buf_to_apl_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM,
+ INT_REPLY_READ_OUT => buf_to_apl_REPLY_READ,
+
+ -- Status and control port
+ STAT_FIFO_TO_INT => api_stat_fifo_to_int,
+ STAT_FIFO_TO_APL => api_stat_fifo_to_apl
+ );
+
+STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
+STAT_api_control_signals(3) <= APL_WRITE_IN;
+STAT_api_control_signals(4) <= APL_SEND_IN;
+STAT_api_control_signals(7 downto 5) <= (others => '0');
+STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0);
+STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY;
+STAT_api_control_signals(12) <= apl_to_buf_INIT_READ;
+STAT_api_control_signals(31 downto 13) <= (others => '0');
+
+
+
+IOBUF: trb_net16_iobuf
+
+ generic map (INIT_DEPTH => INIT_DEPTH,
+ REPLY_DEPTH => REPLY_DEPTH)
+
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
+ MED_INIT_DATA_OUT => MED_INIT_DATA_OUT,
+ MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT,
+ MED_INIT_READ_IN => MED_INIT_READ_IN,
+
+ MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN,
+ MED_INIT_DATA_IN => MED_INIT_DATA_IN,
+ MED_INIT_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN,
+ MED_INIT_READ_OUT => MED_INIT_READ_OUT,
+ MED_INIT_ERROR_IN => (others => '0'),
+
+ MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
+ MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT,
+ MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT,
+ MED_REPLY_READ_IN => MED_REPLY_READ_IN,
+
+ MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
+ MED_REPLY_DATA_IN => MED_REPLY_DATA_IN,
+ MED_REPLY_PACKET_NUM_IN => MED_REPLY_PACKET_NUM_IN,
+ MED_REPLY_READ_OUT => MED_REPLY_READ_OUT,
+ MED_REPLY_ERROR_IN => (others => '0'),
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY,
+ INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA,
+ INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM,
+ INT_INIT_READ_IN => buf_to_apl_INIT_READ,
+
+ INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY,
+ INT_INIT_DATA_IN => apl_to_buf_INIT_DATA,
+ INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM,
+ INT_INIT_READ_OUT => apl_to_buf_INIT_READ,
+
+ INT_REPLY_HEADER_IN => '0',
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY,
+ INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM,
+ INT_REPLY_READ_IN => buf_to_apl_REPLY_READ,
+
+ INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY,
+ INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM,
+ INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ,
+
+ -- Status and control port
+ STAT_GEN => STAT_GEN,
+ STAT_LOCKED => STAT_LOCKED,
+ STAT_INIT_BUFFER => STAT_INIT_BUFFER,
+ STAT_REPLY_BUFFER => STAT_REPLY_BUFFER,
+ CTRL_GEN => CTRL_GEN,
+ CTRL_LOCKED => CTRL_LOCKED,
+ STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER,
+ STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER
+ );
+
+ MPLEX: trb_net16_io_multiplexer
+ generic map (BUS_WIDTH => 16,
+ MULT_WIDTH => 1)
+ port map (
+ CLK => CLK,
+ RESET => RESET ,
+ CLK_EN => CLK_EN,
+
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+
+ INT_DATAREADY_OUT => m_DATAREADY_IN,
+ INT_DATA_OUT =>m_DATA_IN,
+ INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
+ INT_READ_IN =>m_READ_OUT,
+
+ INT_DATAREADY_IN =>m_DATAREADY_OUT,
+ INT_DATA_IN =>m_DATA_OUT,
+ INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
+ INT_READ_OUT =>m_READ_IN,
+
+ CTRL => MPLEX_CTRL
+
+ );
+
+end architecture;
+
--- this is just a terminator, which auto-answers requests
+-- this is just a terminator, which auto-answers requests. Answer is a TRM only.
-- for a description see HADES wiki
-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetTerm
entity trb_net16_term is
generic (
- FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of
+ FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
-- the master path, if set to 0
-- no buffer is used at all
- SEND_DATA_BACK : integer := 0 --answer with data or only a short transfer?
);
port(
-- Misc
architecture trb_net16_term_arch of trb_net16_term is
- component trb_net16_fifo is
- generic (
- DATA_WIDTH : integer := 16; -- FIFO word width
- NUM_WIDTH : integer := 2;
- DEPTH : integer := 4 -- Depth of the FIFO, 2^(n+1)
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data
- PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data
- PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic; -- Full Flag
- EMPTY_OUT : out std_logic;
- DEPTH_OUT : out std_logic_vector(7 downto 0)
- );
- end component;
-
- component trb_net16_dummy_fifo is
- generic (
- DATA_WIDTH : integer := 16; -- FIFO word width
- NUM_WIDTH : integer := 2
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data
- PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data
- PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic; -- Full Flag
- EMPTY_OUT : out std_logic;
- DEPTH_OUT : out std_logic_vector(7 downto 0)
- );
- end component;
-
signal next_APL_DTYPE_OUT, reg_APL_DTYPE_OUT: std_logic_vector(3 downto 0);
signal next_APL_ERROR_PATTERN_OUT, reg_APL_ERROR_PATTERN_OUT: std_logic_vector(31 downto 0);
signal next_APL_SEQNR_OUT, reg_APL_SEQNR_OUT: std_logic_vector(7 downto 0);
begin
-
--- GEN_ONLYTRM: if SEND_DATA_BACK = 0 generate
APL_DTYPE_OUT <= reg_APL_DTYPE_OUT;
APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT;
APL_SEQNR_OUT <= reg_APL_SEQNR_OUT;
process(RESET, reg_APL_ERROR_PATTERN_OUT, reg_APL_DTYPE_OUT, reg_APL_SEQNR_OUT, reg_APL_GOT_TRM, current_packet_type,
INT_PACKET_NUM_IN, INT_DATA_IN, APL_HOLD_TRM, send_trm, reg_APL_ERROR_PATTERN_OUT, reg_APL_DTYPE_IN,
- transfer_counter)
+ transfer_counter, INT_READ_IN)
begin
next_APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT;
next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT;
INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
INT_PACKET_NUM_OUT <= transfer_counter;
--- end generate;
-
-
-
--- GEN_ALSODATA: if SEND_DATA_BACK = 1 generate
--- FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_DATA_IN,
--- INT_DATAREADY_IN,
--- fifo_term_buffer_empty, fifo_term_buffer_data_out,
--- INT_READ_IN, tb_registered_target,
--- reg_APL_DTYPE_OUT, reg_APL_ERROR_PATTERN_OUT,
--- reg_APL_SEQNR_OUT, reg_APL_GOT_TRM,APL_MY_ADDRESS_IN,
--- APL_HOLD_TRM, APL_DTYPE_IN, APL_ERROR_PATTERN_IN, reg_F1,
--- reg_F2, reg_F3, current_packet_type, fifo_term_buffer_full,
--- INT_PACKET_NUM_IN, transfer_counter,
--- reg_APL_ERROR_PATTERN_IN, reg_APL_DTYPE_IN,
--- fifo_term_buffer_packet_num_out)
--- begin -- process
--- INT_READ_OUT <= '1';
--- fifo_term_buffer_write <= '0';
--- tb_next_state <= MY_ERROR;
--- tb_next_registered_target <= tb_registered_target;
--- fifo_term_buffer_read <= '0';
--- INT_DATAREADY_OUT <= '0';
--- next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT;
--- next_APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT;
--- next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT;
--- next_APL_GOT_TRM <= reg_APL_GOT_TRM;
--- next_F1 <= reg_F1;
--- next_F2 <= reg_F2;
--- next_F3 <= reg_F3;
--- fifo_term_buffer_data_in <= (others => '0');
--- -----------------------------------------------------------------------
--- -- IDLE
--- -----------------------------------------------------------------------
--- if tb_current_state = IDLE then
--- INT_READ_OUT <= '1';
--- tb_next_state <= IDLE;
--- if INT_DATAREADY_IN = '1' then
--- if current_packet_type = TYPE_HDR then
--- --header is sent back with exchanged target and source address
--- tb_next_state <= SENDING_HEADER;
--- elsif current_packet_type = TYPE_DAT then
--- --data can be directly sent back
--- fifo_term_buffer_data_in <= INT_DATA_IN;
--- if fifo_term_buffer_full = '0' and (tb_registered_target = APL_MY_ADDRESS_IN
--- or tb_registered_target = BROADCAST_ADRESS) then
--- fifo_term_buffer_write <= '1';
--- else
--- fifo_term_buffer_write <= '0';
--- end if;
---
--- elsif current_packet_type = TYPE_TRM then
--- --TRM is given to APL
--- if INT_PACKET_NUM_IN = "01" then
--- next_APL_ERROR_PATTERN_OUT(31 downto 16) <= INT_DATA_IN;
--- elsif INT_PACKET_NUM_IN = "10" then
--- next_APL_ERROR_PATTERN_OUT(15 downto 0) <= INT_DATA_IN;
--- elsif INT_PACKET_NUM_IN = "11" then
--- next_APL_DTYPE_OUT <= INT_DATA_IN(DTYPE_POSITION);
--- next_APL_SEQNR_OUT <= INT_DATA_IN(SEQNR_POSITION);
--- next_APL_GOT_TRM <= '1';
--- tb_next_state <= RUNNING;
--- end if;
---
--- end if;
--- end if;
--- -----------------------------------------------------------------------
--- -- SENDING & RECEIVING HEADER
--- -----------------------------------------------------------------------
--- --this state is needed to exchange source and target address
--- elsif tb_current_state = SENDING_HEADER then
--- INT_READ_OUT <= '1';
--- if INT_DATAREADY_IN = '1' then
--- fifo_term_buffer_write <= '1';
--- if INT_PACKET_NUM_IN = "01" then
--- next_F2 <= INT_DATA_IN;
--- fifo_term_buffer_data_in <= (others => '0');
--- fifo_term_buffer_data_in(2 downto 0) <= TYPE_HDR;
--- elsif INT_PACKET_NUM_IN = "10" then
--- next_F1 <= INT_DATA_IN;
--- tb_next_registered_target <= INT_DATA_IN;
--- fifo_term_buffer_data_in <= INT_DATA_IN;
--- elsif INT_PACKET_NUM_IN = "11" then
--- next_F3 <= INT_DATA_IN;
--- fifo_term_buffer_data_in <= reg_F2;
--- end if;
--- end if;
--- if transfer_counter = "11" then
--- INT_READ_OUT <= '0';
--- fifo_term_buffer_data_in <= reg_F3;
--- fifo_term_buffer_write <= '1';
--- tb_next_state <= IDLE;
--- end if;
--- -----------------------------------------------------------------------
--- -- RUNNING
--- -----------------------------------------------------------------------
--- elsif tb_current_state = RUNNING then
--- INT_READ_OUT <= '0';
--- if APL_HOLD_TRM = '1' then
--- tb_next_state <= RUNNING;
--- else
--- tb_next_state <= SEND_TRAILER;
--- end if;
--- -----------------------------------------------------------------------
--- -- TRAILER
--- -----------------------------------------------------------------------
--- elsif tb_current_state = SEND_TRAILER then
--- INT_READ_OUT <= '0';
--- tb_next_state <= SEND_TRAILER ;
--- fifo_term_buffer_write <= '1';
--- if transfer_counter = "00" then
--- fifo_term_buffer_data_in <= (others => '0');
--- fifo_term_buffer_data_in(2 downto 0) <= TYPE_TRM;
--- elsif transfer_counter = "01" then
--- fifo_term_buffer_data_in <= reg_APL_ERROR_PATTERN_IN(31 downto 16);
--- elsif transfer_counter = "10" then
--- fifo_term_buffer_data_in <= reg_APL_ERROR_PATTERN_IN(15 downto 0);
--- else
--- fifo_term_buffer_data_in(15 downto 12)<= (others => '0');
--- fifo_term_buffer_data_in(11 downto 4) <= reg_APL_SEQNR_OUT;
--- fifo_term_buffer_data_in(3 downto 0) <= reg_APL_DTYPE_IN;
--- end if;
--- if transfer_counter = "11" then
--- tb_next_state <= IDLE;
--- tb_next_registered_target <= ILLEGAL_ADRESS;
--- next_APL_GOT_TRM <= '0';
--- end if;
--- end if;
--- -----------------------------------------------------------------------
--- -- WRITE FIFO TO INT
--- -----------------------------------------------------------------------
--- INT_DATA_OUT <= fifo_term_buffer_data_out;
--- INT_PACKET_NUM_OUT <= fifo_term_buffer_packet_num_out;
--- if fifo_term_buffer_empty = '0' then
--- INT_DATAREADY_OUT <= '1';
--- if (INT_READ_IN = '1') then
--- fifo_term_buffer_read <= '1';
--- end if;
--- end if;
--- end process;
---
--- fifo_term_buffer_packet_num_in <= transfer_counter;
---
-
--- end generate;
-
-
-
--- CHECK_BUFFER1: if FIFO_TERM_BUFFER_DEPTH >0 generate
--- FIFO_TERM_BUFFER1: trb_net16_fifo
--- generic map (
--- DATA_WIDTH => 16,
--- NUM_WIDTH => 2,
--- DEPTH => FIFO_TERM_BUFFER_DEPTH)
--- port map (
--- CLK => CLK,
--- RESET => RESET,
--- CLK_EN => CLK_EN,
--- DATA_IN => fifo_term_buffer_data_in,
--- PACKET_NUM_IN => fifo_term_buffer_packet_num_in,
--- WRITE_ENABLE_IN => fifo_term_buffer_write,
--- DATA_OUT => fifo_term_buffer_data_out,
--- PACKET_NUM_OUT => fifo_term_buffer_packet_num_out,
--- READ_ENABLE_IN => fifo_term_buffer_read,
--- FULL_OUT => fifo_term_buffer_full,
--- EMPTY_OUT => fifo_term_buffer_empty
--- );
--- end generate CHECK_BUFFER1;
---
--- CHECK_BUFFER2: if FIFO_TERM_BUFFER_DEPTH =0 generate
--- FIFO_TERM_BUFFER0: trb_net16_dummy_fifo
--- generic map (
--- DATA_WIDTH => 16,
--- NUM_WIDTH => 2)
--- port map (
--- CLK => CLK,
--- RESET => RESET,
--- CLK_EN => CLK_EN,
--- DATA_IN => fifo_term_buffer_data_in,
--- PACKET_NUM_IN => fifo_term_buffer_packet_num_in,
--- WRITE_ENABLE_IN => fifo_term_buffer_write,
--- DATA_OUT => fifo_term_buffer_data_out,
--- PACKET_NUM_OUT => fifo_term_buffer_packet_num_out,
--- READ_ENABLE_IN => fifo_term_buffer_read,
--- FULL_OUT => fifo_term_buffer_full,
--- EMPTY_OUT => fifo_term_buffer_empty
--- );
---
--- end generate CHECK_BUFFER2;
-
--- APL_DTYPE_OUT <= reg_APL_DTYPE_OUT;
--- APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT;
--- APL_SEQNR_OUT <= reg_APL_SEQNR_OUT;
--- APL_GOT_TRM <= reg_APL_GOT_TRM;
-
--this holds the current packet type
begin
if rising_edge(CLK) then
if RESET = '1' then
- tb_current_state <= IDLE;
- tb_registered_target <= ILLEGAL_ADRESS;
- reg_F1 <= ILLEGAL_ADRESS;
- reg_F2 <= ILLEGAL_ADRESS;
- reg_F3 <= (others => '0');
reg_APL_GOT_TRM <= '0';
reg_APL_DTYPE_OUT <= (others => '0');
reg_APL_ERROR_PATTERN_OUT <= (others => '0');
reg_APL_SEQNR_OUT <= (others => '0');
send_trm <= '0';
else
- tb_current_state <= tb_next_state;
- tb_registered_target <= tb_next_registered_target;
- reg_F1 <= next_F1;
- reg_F2 <= next_F2;
- reg_F3 <= next_F3;
reg_APL_GOT_TRM <= next_APL_GOT_TRM;
reg_APL_DTYPE_OUT <= next_APL_DTYPE_OUT;
reg_APL_ERROR_PATTERN_OUT <= next_APL_ERROR_PATTERN_OUT;
jspc29 / trbnet.git / commitdiff