*** empty log message ***

diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd
index e2e3ec6721ad680208906ecf5bc26d3eaf628212..c0af57b59d011ead0024767951f26a12ca8b0cc0 100644 (file)
--- a/trb_net16_api_base.vhd
+++ b/trb_net16_api_base.vhd
@@ -49,6 +49,7 @@ entity trb_net16_api_base is
     APL_RUN_OUT           : out std_logic;
     APL_MY_ADDRESS_IN     : in  std_logic_vector (15 downto 0);
     APL_SEQNR_OUT         : out std_logic_vector (7 downto 0);
+    APL_LENGTH_IN         : in  std_logic_vector (15 downto 0);
 
     -- Internal direction port
     -- the ports with master or slave in their name are to be mapped by the active api
@@ -247,11 +248,13 @@ signal last_fifo_to_int_read                 : std_logic;
   signal out_select: OUTPUT_SELECT;
   signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0);
   signal combined_header_F0, combined_header_F1, combined_header_F2, combined_header_F3    : std_logic_vector(15 downto 0);
+  signal registered_header_F0, registered_header_F1, registered_header_F2, registered_header_F3    : std_logic_vector(15 downto 0);
   signal combined_trailer_F0, combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0);
   signal registered_trailer_F0,registered_trailer_F1, registered_trailer_F2, registered_trailer_F3 : std_logic_vector(15 downto 0);
   signal current_combined_header, current_registered_trailer, current_data : std_logic_vector(15 downto 0);
 
   signal update_registered_trailer: std_logic;
+  signal update_registered_header : std_logic;
   signal master_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
   signal send_trm_wrong_addr, next_send_trm_wrong_addr : std_logic;
 
@@ -582,19 +585,19 @@ INT_MASTER_DATAREADY_OUT  <= buf_INT_MASTER_DATAREADY_OUT;
     begin
       case master_counter is
         when c_F0 =>
-           current_combined_header <= combined_header_F0;
+           current_combined_header <= registered_header_F0;
            current_registered_trailer <= registered_trailer_F0;
            current_data <= fifo_to_int_data_out;
         when c_F1 =>
-           current_combined_header <= combined_header_F1;
+           current_combined_header <= registered_header_F1;
            current_registered_trailer <= registered_trailer_F1;
            current_data <= fifo_to_int_data_out;
         when c_F2 =>
-           current_combined_header <= combined_header_F2;
+           current_combined_header <= registered_header_F2;
            current_registered_trailer <= registered_trailer_F2;
            current_data <= fifo_to_int_data_out;
         when c_F3 =>
-           current_combined_header <= combined_header_F3;
+           current_combined_header <= registered_header_F3;
            current_registered_trailer <= registered_trailer_F3;
            current_data <= fifo_to_int_data_out;
         when others =>
@@ -772,6 +775,7 @@ INT_MASTER_DATAREADY_OUT  <= buf_INT_MASTER_DATAREADY_OUT;
       begin
         next_state_to_int <= state_to_int;
         update_registered_trailer <= '0';
+        update_registered_header  <= '0';
         out_select <= DAT;
         next_INT_MASTER_DATAREADY_OUT <= '0';
         next_sequence_counter <= sequence_counter;
@@ -800,6 +804,7 @@ INT_MASTER_DATAREADY_OUT  <= buf_INT_MASTER_DATAREADY_OUT;
               if APL_SHORT_TRANSFER_IN = '1' then
                 next_state_to_int <= SEND_SHORT;
               else
+                update_registered_header <= '1';
                 next_state_to_int <= SEND_HEADER;
               end if;
             end if;
@@ -907,7 +912,7 @@ INT_MASTER_DATAREADY_OUT  <= buf_INT_MASTER_DATAREADY_OUT;
   end generate;
   -- combine the next header
   combined_header_F0 <= APL_MY_ADDRESS_IN;
-  combined_header_F2 <= (others => '0');
+  combined_header_F2 <= APL_LENGTH_IN;
   combined_header_F3(15 downto 14) <= (others => '0');  -- LAY
   combined_header_F3(13 downto 12) <= (others => '0');  -- VERS
   combined_header_F3(11 downto 4)  <= sequence_counter;  -- SEQNR
@@ -990,6 +995,18 @@ INT_MASTER_DATAREADY_OUT  <= buf_INT_MASTER_DATAREADY_OUT;
       end if;
     end process;
 
+  PROC_REG_HDR : process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if update_registered_header = '1' then
+          registered_header_F0 <= combined_header_F0;
+          registered_header_F1 <= combined_header_F1;
+          registered_header_F2 <= combined_header_F2;
+          registered_header_F3 <= combined_header_F3;
+        end if;
+      end if;
+    end process;
+    
 --for simulation only
 
 

diff --git a/trb_net16_endpoint_0_trg_1_api.vhd b/trb_net16_endpoint_0_trg_1_api.vhd
index 3711e3b5eb9b220888eb1f7bba0e79fe28a04d4f..a7c21431cb9822b7da8879b38bde169554729e37 100644 (file)
--- a/trb_net16_endpoint_0_trg_1_api.vhd
+++ b/trb_net16_endpoint_0_trg_1_api.vhd
@@ -71,6 +71,7 @@ entity trb_net16_endpoint_0_trg_1_api is
     APL_RUN_OUT:       out std_logic;
     APL_MY_ADDRESS_IN: in  std_logic_vector (15 downto 0);
     APL_SEQNR_OUT:     out std_logic_vector (7 downto 0);
+    APL_LENGTH_IN:     in  std_logic_vector (15 downto 0);
 
     -- Status and control port
     STAT_GEN:          out std_logic_vector (31 downto 0);