pcs_gen : for i in 0 to NUMBER_OF_GBE_LINKS - 1 generate
- SYNC_RX_PROC : process(sd_rx_clk)
- begin
- if rising_edge(sd_rx_clk(i)) then
- sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8) <= sd_rx_data( (i + 1) * 8 - 1 downto i * 8);
- sd_rx_kcntl_q(i) <= sd_rx_kcntl(i);
- sd_rx_disp_error_q(i) <= sd_rx_disp_error(i);
- sd_rx_cv_error_q(i) <= sd_rx_cv_error(i);
- end if;
- end process SYNC_RX_PROC;
-
- SGMII_GBE_PCS : sgmii_gbe_pcs35
- port map(
- rst_n => synced_rst, --rst_n,
- signal_detect => signal_detected(i),
- gbe_mode => '1',
- sgmii_mode => '0',
- operational_rate => operational_rate( (i + 1) * 2 - 1 downto (i * 2)),
- debug_link_timer_short => '0',
-
- force_isolate => '0',
- force_loopback => '0',
- force_unidir => '0',
-
- rx_compensation_err => open,
-
- ctc_drop_flag => open,
- ctc_add_flag => open,
- an_link_ok => open,
-
- -- MAC interface
- tx_clk_125 => CLK_125_IN, --refclkcore, -- original clock from SerDes
- tx_clock_enable_source => tx_clk_en(i),
- tx_clock_enable_sink => tx_clk_en(i),
- tx_d => pcs_txd( (i + 1) * 8 - 1 downto i * 8), -- TX data from MAC
- tx_en => pcs_tx_en(i), -- TX data enable from MAC
- tx_er => pcs_tx_er(i), -- TX error from MAC
- rx_clk_125 => sd_rx_clk(i),
- rx_clock_enable_source => rx_clk_en(i),
- rx_clock_enable_sink => rx_clk_en(i),
- rx_d => pcs_rxd( (i + 1) * 8 - 1 downto i * 8), -- RX data to MAC
- rx_dv => pcs_rx_en(i), -- RX data enable to MAC
- rx_er => pcs_rx_er(i), -- RX error to MAC
- col => pcs_col(i),
- crs => pcs_crs(i),
+ pcs_active_gen : if LINKS_ACTIVE(i) = '1' generate
+
+ SYNC_RX_PROC : process(sd_rx_clk)
+ begin
+ if rising_edge(sd_rx_clk(i)) then
+ sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8) <= sd_rx_data( (i + 1) * 8 - 1 downto i * 8);
+ sd_rx_kcntl_q(i) <= sd_rx_kcntl(i);
+ sd_rx_disp_error_q(i) <= sd_rx_disp_error(i);
+ sd_rx_cv_error_q(i) <= sd_rx_cv_error(i);
+ end if;
+ end process SYNC_RX_PROC;
- -- SerDes interface
- tx_data => sd_tx_data( (i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes
- tx_kcntl => sd_tx_kcntl(i), -- TX komma control to SerDes
- tx_disparity_cntl => sd_tx_correct_disp(i), -- idle parity state control in IPG (to SerDes)
-
- xmit_autoneg => xmit(i),
-
- serdes_recovered_clk => sd_rx_clk(i), -- 125MHz recovered from receive bit stream
- rx_data => sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8), -- RX data from SerDes
- rx_kcntl => sd_rx_kcntl_q(i), -- RX komma control from SerDes
- rx_err_decode_mode => '0', -- receive error control mode fixed to normal
- rx_even => '0', -- unused (receive error control mode = normal, tie to GND)
- rx_disp_err => sd_rx_disp_error_q(i), -- RX disparity error from SerDes
- rx_cv_err => sd_rx_cv_error_q(i), -- RX code violation error from SerDes
- -- Autonegotiation stuff
- mr_an_complete => an_complete(i),
- mr_page_rx => mr_page_rx(i),
- mr_lp_adv_ability => mr_lp_adv_ability( (i + 1) * 16 - 1 downto i * 16),
- mr_main_reset => mr_main_reset(i),
- mr_an_enable => '1',
- mr_restart_an => mr_restart_an(i),
- mr_adv_ability => mr_adv_ability( (i + 1) * 16 - 1 downto i * 16)
- );
-
- MAC_AN_READY_OUT(i) <= an_complete(i);
-
- u0_reset_controller_pcs : reset_controller_pcs port map(
- rst_n => synced_rst, --rst_n,
- clk => CLK_125_IN,
- tx_plol => tx_pll_lol,
- rx_cdr_lol => rx_cdr_lol(i),
- quad_rst_out => open, --quad_rst,
- tx_pcs_rst_out => tx_pcs_rst(i),
- rx_pcs_rst_out => rx_pcs_rst(i)
- );
-
- u0_reset_controller_cdr : reset_controller_cdr port map(
- rst_n => synced_rst, --rst_n,
- clk => CLK_125_IN,
- cdr_lol => rx_cdr_lol(i),
- cdr_rst_out => rx_serdes_rst(i)
- );
-
- u0_rate_resolution : rate_resolution port map(
- gbe_mode => '1',
- sgmii_mode => '0',
- an_enable => '1',
- advertised_rate => mr_adv_ability(i * 16 + 11 downto i * 16 + 10),
- link_partner_rate => mr_lp_adv_ability(i * 16 + 11 downto i * 16 + 10),
- non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled
-
- operational_rate => operational_rate( (i + 1) * 2 - 1 downto i * 2)
- );
-
- u0_ri : register_interface_hb port map(
- -- Control Signals
- rst_n => synced_rst, --rst_n,
- hclk => CLK_125_IN,
- gbe_mode => '1',
- sgmii_mode => '0',
-
- -- Host Bus
- hcs_n => '1',
- hwrite_n => '1',
- haddr => (others => '0'),
- hdatain => (others => '0'),
-
- hdataout => open,
- hready_n => open,
+ SGMII_GBE_PCS : sgmii_gbe_pcs35
+ port map(
+ rst_n => synced_rst, --rst_n,
+ signal_detect => signal_detected(i),
+ gbe_mode => '1',
+ sgmii_mode => '0',
+ operational_rate => operational_rate( (i + 1) * 2 - 1 downto (i * 2)),
+ debug_link_timer_short => '0',
+
+ force_isolate => '0',
+ force_loopback => '0',
+ force_unidir => '0',
+
+ rx_compensation_err => open,
+
+ ctc_drop_flag => open,
+ ctc_add_flag => open,
+ an_link_ok => open,
+
+ -- MAC interface
+ tx_clk_125 => CLK_125_IN, --refclkcore, -- original clock from SerDes
+ tx_clock_enable_source => tx_clk_en(i),
+ tx_clock_enable_sink => tx_clk_en(i),
+ tx_d => pcs_txd( (i + 1) * 8 - 1 downto i * 8), -- TX data from MAC
+ tx_en => pcs_tx_en(i), -- TX data enable from MAC
+ tx_er => pcs_tx_er(i), -- TX error from MAC
+ rx_clk_125 => sd_rx_clk(i),
+ rx_clock_enable_source => rx_clk_en(i),
+ rx_clock_enable_sink => rx_clk_en(i),
+ rx_d => pcs_rxd( (i + 1) * 8 - 1 downto i * 8), -- RX data to MAC
+ rx_dv => pcs_rx_en(i), -- RX data enable to MAC
+ rx_er => pcs_rx_er(i), -- RX error to MAC
+ col => pcs_col(i),
+ crs => pcs_crs(i),
+
+ -- SerDes interface
+ tx_data => sd_tx_data( (i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes
+ tx_kcntl => sd_tx_kcntl(i), -- TX komma control to SerDes
+ tx_disparity_cntl => sd_tx_correct_disp(i), -- idle parity state control in IPG (to SerDes)
+
+ xmit_autoneg => xmit(i),
+
+ serdes_recovered_clk => sd_rx_clk(i), -- 125MHz recovered from receive bit stream
+ rx_data => sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8), -- RX data from SerDes
+ rx_kcntl => sd_rx_kcntl_q(i), -- RX komma control from SerDes
+ rx_err_decode_mode => '0', -- receive error control mode fixed to normal
+ rx_even => '0', -- unused (receive error control mode = normal, tie to GND)
+ rx_disp_err => sd_rx_disp_error_q(i), -- RX disparity error from SerDes
+ rx_cv_err => sd_rx_cv_error_q(i), -- RX code violation error from SerDes
+ -- Autonegotiation stuff
+ mr_an_complete => an_complete(i),
+ mr_page_rx => mr_page_rx(i),
+ mr_lp_adv_ability => mr_lp_adv_ability( (i + 1) * 16 - 1 downto i * 16),
+ mr_main_reset => mr_main_reset(i),
+ mr_an_enable => '1',
+ mr_restart_an => mr_restart_an(i),
+ mr_adv_ability => mr_adv_ability( (i + 1) * 16 - 1 downto i * 16)
+ );
+
+ MAC_AN_READY_OUT(i) <= an_complete(i);
+
+ u0_reset_controller_pcs : reset_controller_pcs port map(
+ rst_n => synced_rst, --rst_n,
+ clk => CLK_125_IN,
+ tx_plol => tx_pll_lol,
+ rx_cdr_lol => rx_cdr_lol(i),
+ quad_rst_out => open, --quad_rst,
+ tx_pcs_rst_out => tx_pcs_rst(i),
+ rx_pcs_rst_out => rx_pcs_rst(i)
+ );
- -- Register Outputs
- mr_an_enable => mr_an_enable(i),
- mr_restart_an => mr_restart_an(i),
- mr_main_reset => mr_main_reset(i),
- mr_adv_ability => mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16),
+ u0_reset_controller_cdr : reset_controller_cdr port map(
+ rst_n => synced_rst, --rst_n,
+ clk => CLK_125_IN,
+ cdr_lol => rx_cdr_lol(i),
+ cdr_rst_out => rx_serdes_rst(i)
+ );
- -- Register Inputs
- mr_an_complete => an_complete(i),
- mr_page_rx => mr_page_rx(i),
- mr_lp_adv_ability => mr_lp_adv_ability( (i + 1 ) * 16 - 1 downto i * 16)
- );
-
- MAC: tsmac35
- port map(
- ----------------- clock and reset port declarations ------------------
- hclk => CLK_SYS_IN,
- txmac_clk => CLK_125_IN,
- rxmac_clk => sd_rx_clk(i),
- reset_n => GSR_N,
- txmac_clk_en => '1',
- rxmac_clk_en => '1',
- ------------------- Input signals to the GMII ----------------
- rxd => pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8),
- rx_dv => pcs_rx_en_qq(i),
- rx_er => pcs_rx_er_qq(i),
- col => pcs_col(i),
- crs => pcs_crs(i),
- -------------------- Input signals to the CPU I/F -------------------
- haddr => tsm_haddr( (i + 1) * 8 - 1 downto i * 8),
- hdatain => tsm_hdata( (i + 1) * 8 - 1 downto i * 8),
- hcs_n => tsm_hcs_n(i),
- hwrite_n => tsm_hwrite_n(i),
- hread_n => tsm_hread_n(i),
- ---------------- Input signals to the Tx MAC FIFO I/F ---------------
- tx_fifodata => MAC_TX_DATA_IN( (i + 1) * 8 - 1 downto i * 8),
- tx_fifoavail => MAC_FIFOAVAIL_IN(i),
- tx_fifoeof => MAC_FIFOEOF_IN(i),
- tx_fifoempty => MAC_FIFOEMPTY_IN(i),
- tx_sndpaustim => x"0000",
- tx_sndpausreq => '0',
- tx_fifoctrl => '0', -- always data frame
- ---------------- Input signals to the Rx MAC FIFO I/F ---------------
- rx_fifo_full => MAC_RX_FIFOFULL_IN(i), --'0',
- ignore_pkt => '0',
- ---------------- Output signals from the GMII -----------------------
- txd => pcs_txd( (i + 1) * 8 - 1 downto i * 8),
- tx_en => pcs_tx_en(i),
- tx_er => pcs_tx_er(i),
- ----------------- Output signals from the CPU I/F -------------------
- hdataout => open,
- hdataout_en_n => tsm_hdataout_en_n(i),
- hready_n => tsm_hready_n(i),
- cpu_if_gbit_en => open,
- ------------- Output signals from the Tx MAC FIFO I/F ---------------
- tx_macread => MAC_TX_READ_OUT(i),
- tx_discfrm => MAC_TX_DISCRFRM_OUT(i),
- tx_staten => MAC_TX_STAT_EN_OUT(i),
- tx_statvec => MAC_TX_STATS_OUT( (i + 1) * 31 - 1 downto i * 31),
- tx_done => MAC_TX_DONE_OUT(i),
- ------------- Output signals from the Rx MAC FIFO I/F ---------------
- rx_fifo_error => MAC_RX_FIFO_ERR_OUT(i),
- rx_stat_vector => MAC_RX_STATS_OUT( (i + 1) * 32 - 1 downto i * 32),
- rx_dbout => MAC_RX_DATA_OUT( (i + 1) * 8 - 1 downto i * 8),
- rx_write => MAC_RX_WRITE_OUT(i),
- rx_stat_en => MAC_RX_STAT_EN_OUT(i),
- rx_eof => MAC_RX_EOF_OUT(i),
- rx_error => MAC_RX_ERROR_OUT(i)
- );
-
- TSMAC_CONTROLLER : trb_net16_gbe_mac_control
- port map(
- CLK => CLK_SYS_IN,
- RESET => RESET,
+ u0_rate_resolution : rate_resolution port map(
+ gbe_mode => '1',
+ sgmii_mode => '0',
+ an_enable => '1',
+ advertised_rate => mr_adv_ability(i * 16 + 11 downto i * 16 + 10),
+ link_partner_rate => mr_lp_adv_ability(i * 16 + 11 downto i * 16 + 10),
+ non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled
+
+ operational_rate => operational_rate( (i + 1) * 2 - 1 downto i * 2)
+ );
- -- signals to/from main controller
- MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT(i),
- MC_RECONF_IN => MAC_RECONF_IN(i),
- MC_GBE_EN_IN => '1',
- MC_RX_DISCARD_FCS => '0',
- MC_PROMISC_IN => '1',
- MC_MAC_ADDR_IN => (others => '0'),
-
- -- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT => tsm_haddr( (i + 1) * 8 - 1 downto i * 8),
- TSM_HDATA_OUT => tsm_hdata( (i + 1) * 8 - 1 downto i * 8),
- TSM_HCS_N_OUT => tsm_hcs_n(i),
- TSM_HWRITE_N_OUT => tsm_hwrite_n(i),
- TSM_HREAD_N_OUT => tsm_hread_n(i),
- TSM_HREADY_N_IN => tsm_hready_n(i),
- TSM_HDATA_EN_N_IN => tsm_hdataout_en_n(i),
-
- DEBUG_OUT => open
- );
-
- SYNC_GMII_RX_PROC : process(sd_rx_clk)
- begin
- if rising_edge(sd_rx_clk(i)) then
- pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd( (i + 1) * 8 - 1 downto i * 8);
- pcs_rx_en_q(i) <= pcs_rx_en(i);
- pcs_rx_er_q(i) <= pcs_rx_er(i);
+ u0_ri : register_interface_hb port map(
+ -- Control Signals
+ rst_n => synced_rst, --rst_n,
+ hclk => CLK_125_IN,
+ gbe_mode => '1',
+ sgmii_mode => '0',
+
+ -- Host Bus
+ hcs_n => '1',
+ hwrite_n => '1',
+ haddr => (others => '0'),
+ hdatain => (others => '0'),
+
+ hdataout => open,
+ hready_n => open,
- pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8);
- pcs_rx_en_qq(i) <= pcs_rx_en_q(i);
- pcs_rx_er_qq(i) <= pcs_rx_er_q(i);
- end if;
- end process SYNC_GMII_RX_PROC;
-
- SYNC_GMII_TX_PROC : process(CLK_125_IN)
- begin
- if rising_edge(CLK_125_IN) then
- pcs_txd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd( (i + 1) * 8 - 1 downto i * 8);
- pcs_tx_en_q <= pcs_tx_en;
- pcs_tx_er_q <= pcs_tx_er;
+ -- Register Outputs
+ mr_an_enable => mr_an_enable(i),
+ mr_restart_an => mr_restart_an(i),
+ mr_main_reset => mr_main_reset(i),
+ mr_adv_ability => mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16),
+
+ -- Register Inputs
+ mr_an_complete => an_complete(i),
+ mr_page_rx => mr_page_rx(i),
+ mr_lp_adv_ability => mr_lp_adv_ability( (i + 1 ) * 16 - 1 downto i * 16)
+ );
+
+ MAC: tsmac35
+ port map(
+ ----------------- clock and reset port declarations ------------------
+ hclk => CLK_SYS_IN,
+ txmac_clk => CLK_125_IN,
+ rxmac_clk => sd_rx_clk(i),
+ reset_n => GSR_N,
+ txmac_clk_en => '1',
+ rxmac_clk_en => '1',
+ ------------------- Input signals to the GMII ----------------
+ rxd => pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8),
+ rx_dv => pcs_rx_en_qq(i),
+ rx_er => pcs_rx_er_qq(i),
+ col => pcs_col(i),
+ crs => pcs_crs(i),
+ -------------------- Input signals to the CPU I/F -------------------
+ haddr => tsm_haddr( (i + 1) * 8 - 1 downto i * 8),
+ hdatain => tsm_hdata( (i + 1) * 8 - 1 downto i * 8),
+ hcs_n => tsm_hcs_n(i),
+ hwrite_n => tsm_hwrite_n(i),
+ hread_n => tsm_hread_n(i),
+ ---------------- Input signals to the Tx MAC FIFO I/F ---------------
+ tx_fifodata => MAC_TX_DATA_IN( (i + 1) * 8 - 1 downto i * 8),
+ tx_fifoavail => MAC_FIFOAVAIL_IN(i),
+ tx_fifoeof => MAC_FIFOEOF_IN(i),
+ tx_fifoempty => MAC_FIFOEMPTY_IN(i),
+ tx_sndpaustim => x"0000",
+ tx_sndpausreq => '0',
+ tx_fifoctrl => '0', -- always data frame
+ ---------------- Input signals to the Rx MAC FIFO I/F ---------------
+ rx_fifo_full => MAC_RX_FIFOFULL_IN(i), --'0',
+ ignore_pkt => '0',
+ ---------------- Output signals from the GMII -----------------------
+ txd => pcs_txd( (i + 1) * 8 - 1 downto i * 8),
+ tx_en => pcs_tx_en(i),
+ tx_er => pcs_tx_er(i),
+ ----------------- Output signals from the CPU I/F -------------------
+ hdataout => open,
+ hdataout_en_n => tsm_hdataout_en_n(i),
+ hready_n => tsm_hready_n(i),
+ cpu_if_gbit_en => open,
+ ------------- Output signals from the Tx MAC FIFO I/F ---------------
+ tx_macread => MAC_TX_READ_OUT(i),
+ tx_discfrm => MAC_TX_DISCRFRM_OUT(i),
+ tx_staten => MAC_TX_STAT_EN_OUT(i),
+ tx_statvec => MAC_TX_STATS_OUT( (i + 1) * 31 - 1 downto i * 31),
+ tx_done => MAC_TX_DONE_OUT(i),
+ ------------- Output signals from the Rx MAC FIFO I/F ---------------
+ rx_fifo_error => MAC_RX_FIFO_ERR_OUT(i),
+ rx_stat_vector => MAC_RX_STATS_OUT( (i + 1) * 32 - 1 downto i * 32),
+ rx_dbout => MAC_RX_DATA_OUT( (i + 1) * 8 - 1 downto i * 8),
+ rx_write => MAC_RX_WRITE_OUT(i),
+ rx_stat_en => MAC_RX_STAT_EN_OUT(i),
+ rx_eof => MAC_RX_EOF_OUT(i),
+ rx_error => MAC_RX_ERROR_OUT(i)
+ );
+
+ TSMAC_CONTROLLER : trb_net16_gbe_mac_control
+ port map(
+ CLK => CLK_SYS_IN,
+ RESET => RESET,
- pcs_txd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd_q( (i + 1) * 8 - 1 downto i * 8);
- pcs_tx_en_qq <= pcs_tx_en_q;
- pcs_tx_er_qq <= pcs_tx_er_q;
- end if;
- end process SYNC_GMII_TX_PROC;
+ -- signals to/from main controller
+ MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT(i),
+ MC_RECONF_IN => MAC_RECONF_IN(i),
+ MC_GBE_EN_IN => '1',
+ MC_RX_DISCARD_FCS => '0',
+ MC_PROMISC_IN => '1',
+ MC_MAC_ADDR_IN => (others => '0'),
+
+ -- signal to/from Host interface of TriSpeed MAC
+ TSM_HADDR_OUT => tsm_haddr( (i + 1) * 8 - 1 downto i * 8),
+ TSM_HDATA_OUT => tsm_hdata( (i + 1) * 8 - 1 downto i * 8),
+ TSM_HCS_N_OUT => tsm_hcs_n(i),
+ TSM_HWRITE_N_OUT => tsm_hwrite_n(i),
+ TSM_HREAD_N_OUT => tsm_hread_n(i),
+ TSM_HREADY_N_IN => tsm_hready_n(i),
+ TSM_HDATA_EN_N_IN => tsm_hdataout_en_n(i),
+
+ DEBUG_OUT => open
+ );
+
+ SYNC_GMII_RX_PROC : process(sd_rx_clk)
+ begin
+ if rising_edge(sd_rx_clk(i)) then
+ pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd( (i + 1) * 8 - 1 downto i * 8);
+ pcs_rx_en_q(i) <= pcs_rx_en(i);
+ pcs_rx_er_q(i) <= pcs_rx_er(i);
+
+ pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8);
+ pcs_rx_en_qq(i) <= pcs_rx_en_q(i);
+ pcs_rx_er_qq(i) <= pcs_rx_er_q(i);
+ end if;
+ end process SYNC_GMII_RX_PROC;
+
+ SYNC_GMII_TX_PROC : process(CLK_125_IN)
+ begin
+ if rising_edge(CLK_125_IN) then
+ pcs_txd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd( (i + 1) * 8 - 1 downto i * 8);
+ pcs_tx_en_q <= pcs_tx_en;
+ pcs_tx_er_q <= pcs_tx_er;
+
+ pcs_txd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd_q( (i + 1) * 8 - 1 downto i * 8);
+ pcs_tx_en_qq <= pcs_tx_en_q;
+ pcs_tx_er_qq <= pcs_tx_er_q;
+ end if;
+ end process SYNC_GMII_TX_PROC;
+
+ end generate pcs_active_gen;
end generate pcs_gen;
jspc29 / trbnet.git / commitdiff