Add Gbe read-out to ADC AddOn

diff --git a/adcaddon/config.vhd b/adcaddon/config.vhd
index 72b5a416ff8842dcceaa0aa5efe5dad33f335cc8..8cd13c38360b2c9edb4d7b9898c25b5d4736d362 100644 (file)
--- a/adcaddon/config.vhd
+++ b/adcaddon/config.vhd
@@ -13,6 +13,7 @@ package config is
   constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 11; -- size of the event buffer, 2**N
   constant EVENT_MAX_SIZE          : integer := 1000;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
 
+    constant FPGA_TYPE              : integer := 3;
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
     constant USE_200MHZOSCILLATOR   : integer := c_YES;
@@ -27,7 +28,7 @@ package config is
     constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"68";
    
 --set to 0 for backplane serdes, set to 3 for front SFP serdes
-    constant SERDES_NUM             : integer := 3;
+    constant SERDES_NUM             : integer := 0;
    
     constant INCLUDE_UART           : integer  := c_NO;
     constant INCLUDE_SPI            : integer  := c_YES;
@@ -47,11 +48,13 @@ package config is
     constant ADC_SAMPLING_RATE      : integer := 40;
     
 --These are currently used for the included features table only
-    constant ADC_PROCESSING_TYPE    : integer := 0;
+    constant ADC_PROCESSING_TYPE    : integer := 1;
     constant ADC_BASELINE_LOGIC     : integer := c_YES;
     constant ADC_TRIGGER_LOGIC      : integer := c_YES;
     constant ADC_CHANNELS           : integer := 48;
     
+    
+    constant USE_GBE                : integer := c_YES;
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -75,7 +78,8 @@ package config is
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
     constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
-    
+    constant BROADCAST_BITMASK      : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');
+
     
 end;
 
@@ -87,7 +91,7 @@ package body config is
   constant CLOCK_FREQUENCY      : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
   constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
 
-  
+--   constant BROADCAST_BITMASK
   
 function generateIncludedFeatures return std_logic_vector is
   variable t : std_logic_vector(63 downto 0);
@@ -102,6 +106,7 @@ begin
   t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
   t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
   t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+  t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1));
   t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
   t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
   t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));

diff --git a/adcaddon/trb3_periph_adc_constraints.lpf b/adcaddon/trb3_periph_adc_constraints.lpf
index d58272753846286541b7f9f9bed15da7677205ee..0f8f77f9c422ee182f17a7d4736a08a4d3d7137e 100644 (file)
--- a/adcaddon/trb3_periph_adc_constraints.lpf
+++ b/adcaddon/trb3_periph_adc_constraints.lpf
@@ -4,6 +4,11 @@ LOCATE COMP          "THE_MEDIA_INTERFACE_OLD/gen_serdes_0_200_ctc.THE_SERDES/PC
 LOCATE UGROUP        "THE_MEDIA_INTERFACE_OLD/media_interface_group" REGION "MEDIA_MIXED" ;
 
 
+FREQUENCY NET "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz;
+FREQUENCY NET "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/clk_125_rx_from_pcs[0]" 125 MHz;
+LOCATE COMP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
+
+
 
 #################################################################
 # ADC Processor
@@ -62,4 +67,4 @@ PROHIBIT SECONDARY NET "P_CLOCK_c";
 PROHIBIT PRIMARY NET gen_reallogic.THE_ADC/THE_ADC_LEFT/clk_adcfast_i ;
 PROHIBIT SECONDARY NET gen_reallogic.THE_ADC/THE_ADC_RIGHT/clk_adcfast_i ;
 USE EDGE NET gen_reallogic.THE_ADC/THE_ADC_RIGHT/clk_adcfast_i ;
-USE EDGE NET gen_reallogic.THE_ADC/THE_ADC_LEFT/clk_adcfast_i;
\ No newline at end of file
+USE EDGE NET gen_reallogic.THE_ADC/THE_ADC_LEFT/clk_adcfast_i;

diff --git a/adcaddon/trb3sc_adc.prj b/adcaddon/trb3sc_adc.prj
index 03694f03c7dcefd4f34e0c0077046983f15e057e..7da9261c12aa010fc9865c6b115807efd32c083c 100644 (file)
--- a/adcaddon/trb3sc_adc.prj
+++ b/adcaddon/trb3sc_adc.prj
@@ -55,6 +55,8 @@ add_file -vhdl -lib work "config.vhd"
 add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
 
 #Basic Infrastructure
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
@@ -134,9 +136,9 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.v
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
 
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd"
 
 #TrbNet Endpoint
 add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
@@ -168,7 +170,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
@@ -180,6 +182,63 @@ add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
 add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
 
+
+#GbE
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
+
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ip_mem.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd"
+
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
+
+
 add_file -vhdl -lib "work" "../../trb3/base/cores/pll_adc10bit.vhd"
 add_file -vhdl -lib "work" "../../trb3/base/cores/dqsinput_7x5.vhd"
 add_file -vhdl -lib "work" "../../trb3/base/cores/dqsinput_5x5.vhd"

diff --git a/adcaddon/trb3sc_adc.vhd b/adcaddon/trb3sc_adc.vhd
index be3527dfe70b7676c1cab6c139388c4a87ba2bad..c725f8eb1efc0c973a99823aba6e23b902a651db 100644 (file)
--- a/adcaddon/trb3sc_adc.vhd
+++ b/adcaddon/trb3sc_adc.vhd
@@ -236,7 +236,7 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
       CTRL_DEBUG     => open
       );
 
-  SFP_TX_DIS(0) <= '1';
+  SFP_TX_DIS(0) <= '0';
   gen_sfp_con : if SERDES_NUM = 3 generate
     sfp_los_i   <= SFP_LOS(1);
     sfp_prsnt_i <= SFP_MOD0(1); 
@@ -254,22 +254,26 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
 THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
   generic map (
     ADDRESS_MASK                 => x"FFFF",
-    BROADCAST_BITMASK            => x"FF",
+    BROADCAST_BITMASK            => BROADCAST_BITMASK,
     REGIO_INIT_ENDPOINT_ID       => x"0001",
     TIMING_TRIGGER_RAW           => c_YES,
     --Configure data handler
-      DATA_INTERFACE_NUMBER     => 12,
-      DATA_BUFFER_DEPTH         => EVENT_BUFFER_SIZE,
-      DATA_BUFFER_WIDTH         => 32,
-      DATA_BUFFER_FULL_THRESH   => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,
-      TRG_RELEASE_AFTER_DATA    => c_YES,
-      HEADER_BUFFER_DEPTH       => 9,
-      HEADER_BUFFER_FULL_THRESH => 2**9-16
-      )
+    DATA_INTERFACE_NUMBER     => 12,
+    DATA_BUFFER_DEPTH         => EVENT_BUFFER_SIZE,
+    DATA_BUFFER_WIDTH         => 32,
+    DATA_BUFFER_FULL_THRESH   => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,
+    TRG_RELEASE_AFTER_DATA    => c_YES,
+    HEADER_BUFFER_DEPTH       => 9,
+    HEADER_BUFFER_FULL_THRESH => 2**9-16,
+    USE_GBE                   => USE_GBE
+    )
   port map(
     CLK                => clk_sys,
     RESET              => reset_i,
     CLK_EN             => '1',
+    CLK_125            => CLK_SUPPL_PCLK,
+    CLEAR_N            => GSR_N,
+    
     --  Media direction port
     MEDIA_MED2INT                => med2int(0),
     MEDIA_INT2MED                => int2med(0),