*** empty log message ***

diff --git a/special/handler_lvl1.vhd b/special/handler_lvl1.vhd
index fa2017306410c34dbd039b78796bd46ac4bf53c1..12ac6102580bdbc12c2c96abc73bff5fe0875394 100644 (file)
--- a/special/handler_lvl1.vhd
+++ b/special/handler_lvl1.vhd
@@ -12,6 +12,7 @@ generic(
 );
 port(
        RESET                        : in  std_logic;
+       RESET_STATS_IN               : in  std_logic;
        CLOCK                        : in  std_logic;
        --Timing Trigger
        LVL1_TIMING_TRG_IN           : in  std_logic;    --raw trigger signal input, min. 80 ns or strobe, see generics
@@ -496,7 +497,7 @@ end process COUNT_EDGES_AND_LENGTH_PROC;
 -- gk 29.09.10
 WRONG_POLAR_PROC : process(CLOCK)
 begin
-       if (RESET = '1') then
+       if (RESET = '1') or (RESET_STATS_IN = '1') then
                wrong_polarity <= '0';
        elsif (trigger_length > 100) then
                wrong_polarity <= '1';
@@ -540,10 +541,11 @@ end process THE_MEASURED_DELAY_PROC;
 -- Status bits
 ---------------------------------------------------------------------------
 
+-- gk 29.09.10
 STAT_PROC : process(CLOCK)
 begin
        if rising_edge(CLOCK) then
-               if (RESET = '1') then
+               if (RESET = '1') or (RESET_STATS_IN = '1') then
                        STATUS_OUT <= (others => '0');
                elsif (val_trg = '1') or (invalid_trg = '1') then
                        STATUS_OUT(63 downto 48)  <= std_logic_vector(trigger_length);
@@ -569,7 +571,7 @@ end process STAT_PROC;
 STAT_CTR_PROC : process(CLOCK)
 begin
        if rising_edge(CLOCK) then
-               if (RESET = '1') then
+               if (RESET = '1') or (RESET_STATS_IN = '1') then
                        multiple_ctr <= (others => '0');
                        missing_ctr  <= (others => '0');
                        spikes_ctr   <= (others => '0');