Changes in the code and constraint to meet the timing

diff --git a/tdc_releases/tdc_v1.6/TDC.vhd b/tdc_releases/tdc_v1.6/TDC.vhd
index 42e66ef3b8fbb26e661e1a25b1c737d9d5fc247b..e1536d997037f5e0d5eda25fca31114cd9d0b75c 100644 (file)
--- a/tdc_releases/tdc_v1.6/TDC.vhd
+++ b/tdc_releases/tdc_v1.6/TDC.vhd
@@ -97,9 +97,9 @@ architecture TDC of TDC is
   signal reset_tdc                    : std_logic;
   signal reset_tdc_i                  : std_logic;
 -- Coarse counters
-  signal coarse_cntr                  : std_logic_vector_array_11(1 to 4);
+  signal coarse_cntr                  : std_logic_vector_array_11(0 to 4);
   signal coarse_cntr_reset            : std_logic;
-  signal coarse_cntr_reset_r          : std_logic_vector(4 downto 1);
+  signal coarse_cntr_reset_r          : std_logic_vector(4 downto 0);
 -- Slow control
   signal logic_anal_control           : std_logic_vector(3 downto 0);
   signal debug_mode_en_i              : std_logic;
@@ -170,11 +170,15 @@ architecture TDC of TDC is
 -- Bus signals
   signal status_registers_bus_i : std_logic_vector_array_32(0 to STATUS_REG_NR-1);
 
-  attribute syn_keep                    : boolean;
-  attribute syn_keep of reset_tdc       : signal is true;
-  attribute syn_keep of coarse_cntr     : signal is true;
-  attribute syn_preserve                : boolean;
-  attribute syn_preserve of coarse_cntr : signal is true;
+  attribute syn_keep                            : boolean;
+  attribute syn_keep of reset_tdc               : signal is true;
+  attribute syn_keep of coarse_cntr             : signal is true;
+  attribute syn_keep of coarse_cntr_reset_r     : signal is true;
+  attribute syn_keep of trig_win_end_tdc_i      : signal is true;
+  attribute syn_preserve                        : boolean;
+  attribute syn_preserve of coarse_cntr         : signal is true;
+  attribute syn_preserve of coarse_cntr_reset_r : signal is true;
+  attribute syn_preserve of trig_win_end_tdc_i  : signal is true;
 
 begin
 
@@ -405,7 +409,7 @@ begin
       TRIGGER_WIN_EN_IN        => trig_win_en_i,
       TRIG_WIN_END_TDC_IN      => trig_win_end_tdc_i(0),
       TRIG_WIN_END_RDO_IN      => trig_win_end_rdo,
-      COARSE_COUNTER_IN        => coarse_cntr(1),
+      COARSE_COUNTER_IN        => coarse_cntr(0),
       EPOCH_COUNTER_IN         => epoch_cntr,
       DEBUG_MODE_EN_IN         => debug_mode_en_i,
       STATUS_REGISTERS_BUS_OUT => status_registers_bus_i,
@@ -419,7 +423,7 @@ begin
   DATA_FINISHED_OUT <= data_finished_i;
 
 -- Coarse counter
-  GenCoarseCounter : for i in 1 to 4 generate
+  GenCoarseCounter : for i in 0 to 4 generate
     TheCoarseCounter : up_counter
       generic map (
         NUMBER_OF_BITS => 11)
@@ -464,7 +468,7 @@ begin
       SIGNAL_IN => reset_coarse_cntr_200,
       PULSE_OUT => reset_coarse_cntr_edge_200);
 
-  GenCoarseCounterReset : for i in 1 to 4 generate
+  GenCoarseCounterReset : for i in 0 to 4 generate
     coarse_cntr_reset_r(i) <= coarse_cntr_reset when rising_edge(CLK_TDC);
   end generate GenCoarseCounterReset;
 
@@ -477,8 +481,8 @@ begin
       RESET     => epoch_cntr_reset_i,
       COUNT_OUT => epoch_cntr,
       UP_IN     => epoch_cntr_up_i);
-  epoch_cntr_up_i    <= and_all(coarse_cntr(1));
-  epoch_cntr_reset_i <= coarse_cntr_reset_r(1);
+  epoch_cntr_up_i    <= and_all(coarse_cntr(0));
+  epoch_cntr_reset_i <= coarse_cntr_reset_r(0);
 
 -- Bus handler entities
   TheHitCounterBus : BusHandler

diff --git a/tdc_releases/tdc_v1.6/tdc_constraints_2.lpf b/tdc_releases/tdc_v1.6/tdc_constraints_2.lpf
index cf3911f2ae67d0c38224ba22845e6345a1b01a61..d36a787693a7f68b81159c2b4b8ce598b59e8432 100644 (file)
--- a/tdc_releases/tdc_v1.6/tdc_constraints_2.lpf
+++ b/tdc_releases/tdc_v1.6/tdc_constraints_2.lpf
@@ -8,7 +8,7 @@
 #REGION "REGION_LR_CC" "R85C106D" 3 3 DEVSIZE;
 #REGION "REGION_UL_CC" "R48C53D" 3 3 DEVSIZE;
 #REGION "REGION_LL_CC" "R89C53D" 3 3 DEVSIZE;
-
+REGION "REGION_READOUT" "R51C53D" 37 57 DEVSIZE;
 
 ##############################################################################
 ##                     REFERENCE CHANNEL PLACEMENT                         ##
@@ -875,9 +875,9 @@ LOCATE UGROUP "UL_Coarse_Counter" SITE R36C50D; #REGION "REGION_UL_CC" ;
 UGROUP "LL_Coarse_Counter"
         BLKNAME THE_TDC/GenCoarseCounter_4_TheCoarseCounter;
 LOCATE UGROUP "LL_Coarse_Counter" SITE R85C50D; #REGION "REGION_LL_CC" ;
-UGROUP "Epoch_Counter"
-       BLKNAME THE_TDC/TheEpochCounter;
-LOCATE UGROUP "Epoch_Counter" SITE R36C138D;
+#UGROUP "Epoch_Counter"
+#      BLKNAME THE_TDC/TheEpochCounter;
+#LOCATE UGROUP "Epoch_Counter" SITE R36C138D;
 
 #############################################################################
 ## Bus Handler Placements
@@ -895,6 +895,14 @@ UGROUP "ResetHandler"
 #LOCATE UGROUP "ResetHandler" REGION BUS;
 
 
+UGROUP "TheTdcReadout"
+       BLKNAME THE_TDC/TheReadout;
+LOCATE UGROUP "TheTdcReadout" REGION REGION_READOUT;
+
+UGROUP "TheCounters"
+       BLKNAME THE_TDC/GenCoarseCounter_0_TheCoarseCounter
+       BLKNAME THE_TDC/TheEpochCounter;
+LOCATE UGROUP "TheCounters" REGION REGION_READOUT;
 
 #############################################################################
 ##                         Unimportant Data Lines                          ##
@@ -920,11 +928,13 @@ MAXDELAY NET "THE_TDC/GEN_Channels_*_Channels/hit_buf" 0.600000 nS DATAPATH_ONLY
 
 
 MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns;
+MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x;
 MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/GEN_Channels_*_Channels/epoch_cntr_reg*" 5.000000 X;
 MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 5.000000 X;
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns;
+
 
+#MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg*" 2.000000 X;
+#MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg_*" 2.000000 X;
 #MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/FIFO_ALMOST_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg_*" 2.000000 X;
-MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg_*" 2.000000 X;
-MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg*" 2.000000 X;
 #MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/FIFO_ALMOST_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg*" 2.000000 X;