Restart FIFO properly, otherwise sim does not work

diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd
index c927e85c870895aa773e3875de12626b0b63f3ab..2f777e63c12c6748273939344f90b5f6e942be47 100644 (file)
--- a/ADC/source/adc_ad9219.vhd
+++ b/ADC/source/adc_ad9219.vhd
@@ -239,7 +239,7 @@ begin
         RdClock            => CLK,
         WrEn               => fifo_write(i),
         RdEn               => '1',
-        Reset              => '0',
+        Reset              => RESTART_IN,
         RPReset            => RESTART_IN,
         Q(49 downto 0)     => fifo_output(i),
         Empty              => fifo_empty(i),