added sed checker to ADC design

diff --git a/ADC/source/adc_slowcontrol_data_buffer.vhd b/ADC/source/adc_slowcontrol_data_buffer.vhd
index f11672b2cf6a6c374bc6181a9f15b61ee8684fc3..e20b9c792f22089de4a8823fe5221adc1ce94e77 100644 (file)
--- a/ADC/source/adc_slowcontrol_data_buffer.vhd
+++ b/ADC/source/adc_slowcontrol_data_buffer.vhd
@@ -49,7 +49,7 @@ signal fifo_wait_0, fifo_wait_1, fifo_wait_2 : std_logic;
 signal adc_data_out  : std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0);
 signal adc_fco_out   : std_logic_vector(DEVICES*RESOLUTION-1 downto 0);
 signal adc_valid_out : std_logic_vector(DEVICES-1 downto 0);
-signal adc_debug     : std_logic_vector(DEVICES*CHANNELS*32-1 downto 0);
+signal adc_debug     : std_logic_vector(DEVICES*32-1 downto 0);
 signal adc_restart   : std_logic;
 begin
 
@@ -87,10 +87,10 @@ THE_ADC_LEFT : entity work.adc_ad9219
     DATA_VALID_OUT(5 downto 0) => adc_valid_out(5 downto 0),
     DATA_VALID_OUT(6)          => adc_valid_out(7),
     
-    DEBUG(32*6*CHANNELS-1 downto 0)
-                               => adc_debug(32*6*CHANNELS-1 downto 0),
-    DEBUG(32*7*CHANNELS -1 downto 32*6*CHANNELS)
-                               => adc_debug(32*8*CHANNELS-1 downto 32*7*CHANNELS)
+    DEBUG(32*6-1 downto 0)
+                               => adc_debug(32*6-1 downto 0),
+    DEBUG(32*7 -1 downto 32*6)
+                               => adc_debug(32*8-1 downto 32*7)
     
     );
 
@@ -124,10 +124,10 @@ THE_ADC_RIGHT : entity work.adc_ad9219
     DATA_VALID_OUT(0)          => adc_valid_out(6),
     DATA_VALID_OUT(4 downto 1) => adc_valid_out(11 downto 8),
     
-    DEBUG(32*1*CHANNELS-1 downto 0)
-                               => adc_debug(32*7*CHANNELS-1 downto 32*6*CHANNELS),
-    DEBUG(32*5*CHANNELS -1 downto 32*1*CHANNELS)
-                               => adc_debug(32*12*CHANNELS-1 downto 32*8*CHANNELS)
+    DEBUG(32*1-1 downto 0)
+                               => adc_debug(32*7-1 downto 32*6),
+    DEBUG(32*5 -1 downto 32*1)
+                               => adc_debug(32*12-1 downto 32*8)
     
     );    
 
@@ -173,9 +173,9 @@ PROC_BUS : process begin
     if BUS_RX.addr(7 downto 0) = x"80" then
       BUS_TX.data  <= ctrl_reg;
       BUS_TX.ack   <= '1';
-    elsif BUS_RX.addr(7 downto 0) >= x"40" and BUS_RX.addr(7 downto 0) < x"80" 
+    elsif BUS_RX.addr(7 downto 0) >= x"40" and BUS_RX.addr(7 downto 0) < x"50" 
            and BUS_RX.addr(5 downto 0) < std_logic_vector(to_unsigned(DEVICES*CHANNELS,6)) then
-      BUS_TX.data  <= adc_debug(to_integer(unsigned(BUS_RX.addr(5 downto 0)))*32+31 downto to_integer(unsigned(BUS_RX.addr(5 downto 0)))*32);
+      BUS_TX.data  <= adc_debug(to_integer(unsigned(BUS_RX.addr(3 downto 0)))*32+31 downto to_integer(unsigned(BUS_RX.addr(3 downto 0)))*32);
       BUS_TX.ack   <= '1';
     elsif BUS_RX.addr(7 downto 0) = x"83" then
       BUS_TX.data  <= (others => '0');

diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj
index edc54268f44f03f0b614b66816f7d081e7a286a9..be2f7bf5b0a80b1168fffa25446b4d463069143d 100644 (file)
--- a/ADC/trb3_periph_adc.prj
+++ b/ADC/trb3_periph_adc.prj
@@ -146,6 +146,7 @@ add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"
 add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200_50.vhd"
+add_file -vhdl -lib "work" "../base/code/sedcheck.vhd"
 
 add_file -vhdl -lib "work" "source/adc_package.vhd"
 add_file -vhdl -lib "work" "source/adc_processor.vhd"

diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd
index 8fc29c32e88160c3feaf1027734f1c2f1354be1a..bef56a96c74ed8af0378d1e49fd960e4daeab31b 100644 (file)
--- a/ADC/trb3_periph_adc.vhd
+++ b/ADC/trb3_periph_adc.vhd
@@ -153,8 +153,8 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is
   signal spi_sdi, spi_sdo, spi_sck : std_logic;
   signal adcspi_ctrl               : std_logic_vector(7 downto 0);
 
-  signal regio_rx, busadc_rx, busspi_rx, busmem_rx : CTRLBUS_RX;
-  signal regio_tx, busadc_tx, busspi_tx, busmem_tx : CTRLBUS_TX;
+  signal regio_rx, busadc_rx, busspi_rx, busmem_rx, bussed_rx : CTRLBUS_RX;
+  signal regio_tx, busadc_tx, busspi_tx, busmem_tx, bussed_tx : CTRLBUS_TX;
   signal readout_rx : READOUT_RX;
   signal readout_tx : readout_tx_array_t(0 to 11);
   
@@ -164,6 +164,7 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is
   signal fee_data_in           : std_logic_vector(32*DEVICES-1 downto 0);
   signal fee_trg_statusbits_in : std_logic_vector(32*DEVICES-1 downto 0);
   
+  signal sed_debug : std_logic_vector(31 downto 0);
   
 begin
 ---------------------------------------------------------------------------
@@ -443,9 +444,9 @@ end generate;
 ---------------------------------------------------------------------------
   THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
     generic map(
-      PORT_NUMBER      => 3,
-      PORT_ADDRESSES   => (0 => x"d000", 1 => x"d400", 2 => x"a000", others => x"0000"),
-      PORT_ADDR_MASK   => (0 => 9,       1 => 5,       2 => 12,      others => 0),
+      PORT_NUMBER      => 4,
+      PORT_ADDRESSES   => (0 => x"d000", 1 => x"d400", 2 => x"a000", 3 => x"d500", others => x"0000"),
+      PORT_ADDR_MASK   => (0 => 9,       1 => 5,       2 => 12,      3 => 2,       others => 0),
       PORT_MASK_ENABLE => 1
       )
     port map(
@@ -458,9 +459,11 @@ end generate;
       BUS_RX(0) => busmem_rx, --Flash
       BUS_RX(1) => busspi_rx, --SPI
       BUS_RX(2) => busadc_rx, --ADC
+      BUS_RX(3) => bussed_rx,
       BUS_TX(0) => busmem_tx,
       BUS_TX(1) => busspi_tx,
       BUS_TX(2) => busadc_tx,
+      BUS_TX(3) => bussed_tx,
       
       STAT_DEBUG => open
       );
@@ -494,6 +497,18 @@ THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
     SPI_SDI_IN           => FLASH_DOUT
     );
 
+---------------------------------------------------------------------------
+-- SED Detection
+---------------------------------------------------------------------------
+  THE_SED : entity work.sedcheck
+    port map(
+      CLK       => clk_100_i,
+      ERROR_OUT => open,
+      BUS_RX    => bussed_rx,
+      BUS_TX    => bussed_tx,
+      DEBUG     => sed_debug
+      );    
+    
 -------------------------------------------------------------------------------
 -- SPI
 -------------------------------------------------------------------------------
@@ -567,6 +582,6 @@ LED_YELLOW <= not med_stat_op(11);
 -- Test Connector - Logic Analyser
 ---------------------------------------------------------------------------
 
-  TEST_LINE <= (others => '0');
+  TEST_LINE <= sed_debug(28 downto 24) & sed_debug(10 downto 0);
 
 end architecture;

diff --git a/base/code/sedcheck.vhd b/base/code/sedcheck.vhd
index 419835e7d4ca515d31fa4bdece470ece7104dbeb..c3754959ab53f3237ae524c50a45b5926888070e 100644 (file)
--- a/base/code/sedcheck.vhd
+++ b/base/code/sedcheck.vhd
@@ -11,7 +11,8 @@ entity sedcheck is
     ERROR_OUT  : out std_logic;
     
     BUS_RX     : in  CTRLBUS_RX;
-    BUS_TX     : out CTRLBUS_TX
+    BUS_TX     : out CTRLBUS_TX;
+    DEBUG      : out std_logic_vector(31 downto 0)
     );
 end entity;
 
@@ -195,7 +196,7 @@ status_i(23 downto 16) <= std_logic_vector(run_counter)(7 downto 0);
 status_i(31 downto 24) <= std_logic_vector(error_counter)(7 downto 0);
               
 ERROR_OUT <= sed_error;              
-
+DEBUG     <= status_i when rising_edge(CLK);
 
 ---------------------------------------------------------------------------
 -- SED