The slow-control interface:
\begin{itemize}
- \item 32 Bit Data Memory: 0xd800 - 0xd80f, Length register 0xd810
- \item Transfer is started when length register (counting 32 Bit words) is written.
- \item While busy, the writing to the length register will be ignored and gives back a no-more-data flag.
- \item Doing a memory write with 17 words will do the job, should be faster than two individual accesses
- \item All data is sent MSB first (Bit 31), Bits 7-0 are the don't-care-Bits of the DAC.
- \item Interface speed: e.g. 12.5 MHz -> max. 40us for 16 chips
+ \item 32 Bit Data Memory: 0xd400 - 0xd40f, Length register 0xd410
+ \item Transfer is started when the length register (counting 32 Bit words) is written.
+ \item While busy, the writing to the length register will be ignored and gives back a no-more-data flag.
+ \item Doing a memory write with 17 words will do the job, should be faster than two individual accesses for data and length.
+ \item All data is sent MSB first (Bit 31), Bits 31-24 are the don't-care-Bits of the DAC.
+ \item Interface speed: e.g. 6.25 MHz -> max. 80us for 16 chips
\end{itemize}
-The software takes a text file as input (format to be defined) and generates the correct SPI sequence to load and activate the DAC.
+The software takes a text file as input and generates the correct SPI sequence to load and activate the DAC.
+The ASCII format is shown below, the commands can be found in table~\ref{ltc2600cmd}.
+\begin{verbatim}
+# DAC Channel Command Value
+ 0 0 3 0x3450
+ 0 1 3 0x1230
+ 1 0 3 0x6780
+ 2 0 F 0
+\end{verbatim}
+
+\begin{table}
+\centering
+\begin{tabular}{c|l}
+ 0 & Write Register N\\
+ 1 & Switch Output N on \\
+ 2 & Write Register N, switch on all \\
+ 3 & Write Register N, switch output N on \\
+ 4 & Switch Output N off \\
+ F & No Operation \\
+\end{tabular}
+\caption{LTC2600 Commands}
+\label{ltc2600cmd}
+\end{table}
\ No newline at end of file
-\begin{itemize}
+\begin{itemize*}
\item Schematics \href{http://hades-wiki.gsi.de/pub/DaqSlowControl/TDCReadoutBoardV3/MultiTestAddon1_alles.pdf}{MultiTestAddon1\_alles.pdf}
\item Pin-out file for the FPGA \href{cvs://:ext:hadaq@lxi001.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3/base/trb3_periph_multitest.lpf}{cvsroot/trb3/base/trb3\_periph\_multitest.lpf}
-\end{itemize}
\ No newline at end of file
+\end{itemize*}
+
+
+\subsubsection{Known bugs}
+\begin{itemize*}
+ \item The serial interface to ADC 1 is not usable - CSB and PDWN are input-only on the FPGA
+ \item LVDS_INP_2 is the only LVDS port that is terminated by an external resistor. Do not switch on corresponding LVDS termiantion in FPGA
+\end{itemize*}
\ No newline at end of file
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