--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="fifo_16x512_dualclock" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 04 27 17:40:53.149" version="5.4" type="Module" synthesis="" source_format="VHDL">
+ <Package>
+ <File name="fifo_16x512_dualclock.lpc" type="lpc" modified="2011 04 27 17:40:50.000"/>
+ <File name="fifo_16x512_dualclock.vhd" type="top_level_vhdl" modified="2011 04 27 17:40:50.000"/>
+ <File name="fifo_16x512_dualclock_tmpl.vhd" type="template_vhdl" modified="2011 04 27 17:40:50.000"/>
+ <File name="tb_fifo_16x512_dualclock_tmpl.vhd" type="testbench_vhdl" modified="2011 04 27 17:40:50.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA40EP1
+PartName=LFSCM3GA40EP1-6FF1020C
+SpeedGrade=6
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.4
+ModuleName=fifo_16x512_dualclock
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/27/2011
+Time=17:40:50
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=512
+RWidth=16
+WDepth=512
+WWidth=16
+regout=0
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=2
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=484
+PfDeassert=506
+Reset=Async
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517)
+-- Module Version: 5.4
+--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_16x512_dualclock -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 16 -rwidth 16 -no_enable -pe 2 -pf 484 -e
+
+-- Wed Apr 27 17:40:50 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_16x512_dualclock is
+ port (
+ Data: in std_logic_vector(15 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(15 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_16x512_dualclock;
+
+architecture Structure of fifo_16x512_dualclock is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of fifo_16x512_dualclock_0_0 : label is "0b011111111000001";
+ attribute FULLPOINTER of fifo_16x512_dualclock_0_0 : label is "0b011111111100001";
+ attribute AFPOINTER1 of fifo_16x512_dualclock_0_0 : label is "0b011110001000001";
+ attribute AFPOINTER of fifo_16x512_dualclock_0_0 : label is "0b011110001100001";
+ attribute AEPOINTER1 of fifo_16x512_dualclock_0_0 : label is "0b000000001111111";
+ attribute AEPOINTER of fifo_16x512_dualclock_0_0 : label is "0b000000001011111";
+ attribute RESETMODE of fifo_16x512_dualclock_0_0 : label is "ASYNC";
+ attribute REGMODE of fifo_16x512_dualclock_0_0 : label is "NOREG";
+ attribute CSDECODE_R of fifo_16x512_dualclock_0_0 : label is "0b11";
+ attribute CSDECODE_W of fifo_16x512_dualclock_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of fifo_16x512_dualclock_0_0 : label is "36";
+ attribute DATA_WIDTH_W of fifo_16x512_dualclock_0_0 : label is "36";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ fifo_16x512_dualclock_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001",
+ AFPOINTER1=> "011110001000001", AFPOINTER=> "011110001100001",
+ AEPOINTER1=> "000000001111111", AEPOINTER=> "000000001011111",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>scuba_vlo, DI17=>scuba_vlo,
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
+ EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi,
+ WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset,
+ RPRST=>RPReset, DO0=>open, DO1=>open, DO2=>open, DO3=>open,
+ DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0),
+ DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
+ DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
+ DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
+ DO33=>Q(15), DO34=>open, DO35=>open, EF=>Empty_int,
+ AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_16x512_dualclock is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="fifo_8x16_dualclock" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 02 03 09:34:01.845" version="5.4" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="fifo_8x16_dualclock.lpc" type="lpc" modified="2011 02 03 09:33:59.000"/>
+ <File name="fifo_8x16_dualclock.vhd" type="top_level_vhdl" modified="2011 02 03 09:33:59.000"/>
+ <File name="fifo_8x16_dualclock_tmpl.vhd" type="template_vhdl" modified="2011 02 03 09:33:59.000"/>
+ <File name="tb_fifo_8x16_dualclock_tmpl.vhd" type="testbench_vhdl" modified="2011 02 03 09:33:59.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA40EP1
+PartName=LFSCM3GA40EP1-6FF1020C
+SpeedGrade=6
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.4
+ModuleName=fifo_8x16_dualclock
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=02/03/2011
+Time=09:33:59
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=16
+RWidth=8
+WDepth=16
+WWidth=8
+regout=0
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=1
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=12
+PfDeassert=506
+Reset=Async
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517)
+-- Module Version: 5.4
+--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_8x16_dualclock -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 16 -width 8 -rwidth 8 -no_enable -pe 1 -pf 12 -e
+
+-- Thu Feb 3 09:33:59 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_8x16_dualclock is
+ port (
+ Data: in std_logic_vector(7 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(7 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_8x16_dualclock;
+
+architecture Structure of fifo_8x16_dualclock is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of fifo_8x16_dualclock_0_0 : label is "0b000000111000001";
+ attribute FULLPOINTER of fifo_8x16_dualclock_0_0 : label is "0b000000111100001";
+ attribute AFPOINTER1 of fifo_8x16_dualclock_0_0 : label is "0b000000101000001";
+ attribute AFPOINTER of fifo_8x16_dualclock_0_0 : label is "0b000000101100001";
+ attribute AEPOINTER1 of fifo_8x16_dualclock_0_0 : label is "0b000000001011111";
+ attribute AEPOINTER of fifo_8x16_dualclock_0_0 : label is "0b000000000111111";
+ attribute RESETMODE of fifo_8x16_dualclock_0_0 : label is "ASYNC";
+ attribute REGMODE of fifo_8x16_dualclock_0_0 : label is "NOREG";
+ attribute CSDECODE_R of fifo_8x16_dualclock_0_0 : label is "0b11";
+ attribute CSDECODE_W of fifo_8x16_dualclock_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of fifo_8x16_dualclock_0_0 : label is "36";
+ attribute DATA_WIDTH_W of fifo_8x16_dualclock_0_0 : label is "36";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ fifo_8x16_dualclock_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "000000111000001", FULLPOINTER=> "000000111100001",
+ AFPOINTER1=> "000000101000001", AFPOINTER=> "000000101100001",
+ AEPOINTER1=> "000000001011111", AEPOINTER=> "000000000111111",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>scuba_vlo, DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi,
+ CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi,
+ CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock,
+ CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>open,
+ DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open,
+ DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
+ DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open,
+ EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull,
+ FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_8x16_dualclock is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="fifo_9x512_dualclock" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 04 27 17:56:05.186" version="5.4" type="Module" synthesis="" source_format="VHDL">
+ <Package>
+ <File name="fifo_9x512_dualclock.lpc" type="lpc" modified="2011 04 27 17:56:03.000"/>
+ <File name="fifo_9x512_dualclock.vhd" type="top_level_vhdl" modified="2011 04 27 17:56:03.000"/>
+ <File name="fifo_9x512_dualclock_tmpl.vhd" type="template_vhdl" modified="2011 04 27 17:56:03.000"/>
+ <File name="tb_fifo_9x512_dualclock_tmpl.vhd" type="testbench_vhdl" modified="2011 04 27 17:56:03.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA40EP1
+PartName=LFSCM3GA40EP1-6FF1020C
+SpeedGrade=6
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.4
+ModuleName=fifo_9x512_dualclock
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/27/2011
+Time=17:56:03
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=512
+RWidth=9
+WDepth=512
+WWidth=9
+regout=0
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=1
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=484
+PfDeassert=506
+Reset=Async
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517)
+-- Module Version: 5.4
+--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_9x512_dualclock -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 9 -rwidth 9 -no_enable -pe 1 -pf 484 -e
+
+-- Wed Apr 27 17:56:03 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_9x512_dualclock is
+ port (
+ Data: in std_logic_vector(8 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(8 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_9x512_dualclock;
+
+architecture Structure of fifo_9x512_dualclock is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of fifo_9x512_dualclock_0_0 : label is "0b011111111000001";
+ attribute FULLPOINTER of fifo_9x512_dualclock_0_0 : label is "0b011111111100001";
+ attribute AFPOINTER1 of fifo_9x512_dualclock_0_0 : label is "0b011110001000001";
+ attribute AFPOINTER of fifo_9x512_dualclock_0_0 : label is "0b011110001100001";
+ attribute AEPOINTER1 of fifo_9x512_dualclock_0_0 : label is "0b000000001011111";
+ attribute AEPOINTER of fifo_9x512_dualclock_0_0 : label is "0b000000000111111";
+ attribute RESETMODE of fifo_9x512_dualclock_0_0 : label is "ASYNC";
+ attribute REGMODE of fifo_9x512_dualclock_0_0 : label is "NOREG";
+ attribute CSDECODE_R of fifo_9x512_dualclock_0_0 : label is "0b11";
+ attribute CSDECODE_W of fifo_9x512_dualclock_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of fifo_9x512_dualclock_0_0 : label is "36";
+ attribute DATA_WIDTH_W of fifo_9x512_dualclock_0_0 : label is "36";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ fifo_9x512_dualclock_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001",
+ AFPOINTER1=> "011110001000001", AFPOINTER=> "011110001100001",
+ AEPOINTER1=> "000000001011111", AEPOINTER=> "000000000111111",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi,
+ CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi,
+ CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock,
+ CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>open,
+ DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open,
+ DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
+ DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
+ DO26=>Q(8), DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open,
+ EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull,
+ FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_9x512_dualclock is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
CLK_IN : in std_logic;
CLK_125_IN : in std_logic;
- DMA_START_ADDR_IN : in std_logic_vector(31 downto 0); --0x700
- DMA_LENGTH_IN : in std_logic_vector(31 downto 0); --0x701
+ DMA_DATA_IN : in std_logic_vector(31 downto 0);
+ DMA_LENGTH_WR_IN : in std_logic;
+ DMA_ADDR_WR_IN : in std_logic;
DMA_CONTROL_IN : in std_logic_vector(31 downto 0); --0x702 write
--0: activate
--1: reset dma handler (not implemented)
RX_DWEN_IN : in std_logic;
RX_DATA_IN : in std_logic_vector(63 downto 0);
- STATUS_REG_OUT : out std_logic_vector(127 downto 0);
+ STATUS_REG_OUT : out std_logic_vector(159 downto 0);
DEBUG_OUT : out std_logic_vector(31 downto 0)
);
signal tx_length_full : std_logic := '0';
signal tx_length_almost_empty : std_logic := '0';
signal tx_length_almost_full : std_logic := '0';
- signal tx_length_data_in : std_logic_vector(7 downto 0) := (others => '0');
- signal tx_length_data_out : std_logic_vector(7 downto 0) := (others => '0');
+ signal tx_length_data_in : std_logic_vector(8 downto 0) := (others => '0');
+ signal tx_length_data_out : std_logic_vector(8 downto 0) := (others => '0');
- type copy_state_t is (IDLE, RUNNING, LAST_WORD, BUFFER_FULL_WAIT, WAIT_ONE);
+ type copy_state_t is (IDLE, RUNNING, LAST_WORD, BUFFER_FULL_WAIT, WAIT_ONE, WAIT_BUFFER);
signal copy_state : copy_state_t;
- signal copy_length : unsigned(6 downto 0) := (others => '0');
+ signal copy_length : unsigned(7 downto 0) := (others => '0');
signal current_address : unsigned(31 downto 0) := (others => '0');
signal buf_API_READ_OUT : std_logic := '0';
type send_state_t is (SEND_IDLE, SEND_CREDIT_WAIT, SEND_START, SEND_DATA);
signal send_state : send_state_t;
- signal tx_length : unsigned(6 downto 0) := (others => '0');
+ signal tx_length : unsigned(7 downto 0) := (others => '0');
signal last_words : std_logic := '0';
signal finished : std_logic := '0';
signal finished_sys : std_logic := '0';
signal tx_req_i : std_logic;
signal tx_end_i : std_logic;
+ signal tx_st_i : std_logic;
signal send_state_bits : std_logic_vector(3 downto 0);
signal copy_state_bits : std_logic_vector(1 downto 0);
- signal total_length : unsigned(23 downto 0);
+ signal total_length : unsigned(23 downto 0) := (others => '0');
signal current_buffer : unsigned(23 downto 0) := (others => '0');
- signal tx_fifo_padding : std_logic_vector(3 downto 0);
+ signal tx_fifo_padding : std_logic_vector(3 downto 0) := (others => '0');
signal api_running_rising : std_logic;
signal api_running_falling : std_logic;
signal api_starts : std_logic;
signal last_api_running : std_logic;
- signal buf_TX_DATA_OUT : std_logic_vector(63 downto 0);
+ signal buf_TX_DATA_OUT : std_logic_vector(63 downto 0) := (others => '0');
signal buffer_full_strobe : std_logic;
signal buffer_full : std_logic;
- signal current_burst_length : unsigned(6 downto 0);
+ signal current_burst_length : unsigned(7 downto 0);
signal buffer_space_available : std_logic;
-
+ signal buffer_space_end : unsigned(31 downto 0);
+ signal buffer_space_afull : unsigned(31 downto 0);
+ signal credits_sys : std_logic_vector(12 downto 0);
+
+ signal rden_dma_fifo : std_logic := '0';
+ signal reset_dma_fifo : std_logic := '0';
+ signal empty_addr_fifo : std_logic := '0';
+ signal empty_length_fifo : std_logic := '0';
+ signal next_dma_length_i : std_logic_vector(31 downto 0);
+ signal next_dma_start_address_i : std_logic_vector(31 downto 0);
+ signal dma_length_i : std_logic_vector(31 downto 0);
+ signal dma_start_address_i : std_logic_vector(31 downto 0);
+ signal new_buffer_available : std_logic := '0';
+ signal dma_fifo_state : std_logic_vector(3 downto 0);
+
+ type dma_state_t is (INACTIVE, ACTIVE, WAIT_1, WAIT_2, WAIT_3, ENABLE, WORKING, DMA_RESET);
+ signal current_dma_state : dma_state_t;
+
+ signal dummy : std_logic_vector(2 downto 0);
+
begin
+
-----------------------------------------------------------------------
-- I/O
-----------------------------------------------------------------------
API_READ_OUT <= buf_API_READ_OUT;
-PROC_COPY_DATA : process(CLK_IN)
- begin
- if rising_edge(CLK_IN) then
- buffer_space_available <= '1';
- current_burst_length <= unsigned(DMA_CONFIG_IN(6 downto 0));
-
--- if current_address + unsigned(DMA_CONFIG_IN(7 downto 0)) * to_unsigned(4,32)
--- < unsigned(DMA_START_ADDR_IN) + unsigned(DMA_LENGTH_IN) * to_unsigned(4,32) then
--- end if;
+-----------------------------------------------------------------------
+-- Buffer Slice Fifo & Control
+-----------------------------------------------------------------------
+ THE_DMA_ADDR_FIFO : fifo_32x512
+ port map(
+ Data => DMA_DATA_IN,
+ Clock => CLK_IN,
+ WrEn => DMA_ADDR_WR_IN,
+ RdEn => rden_dma_fifo,
+ Reset => reset_dma_fifo,
+ Q => next_dma_start_address_i,
+ Empty => empty_addr_fifo,
+ Full => open
+ );
+
+ THE_DMA_LENGTH_FIFO : fifo_32x512
+ port map(
+ Data => DMA_DATA_IN,
+ Clock => CLK_IN,
+ WrEn => DMA_LENGTH_WR_IN,
+ RdEn => rden_dma_fifo,
+ Reset => reset_dma_fifo,
+ Q => next_dma_length_i,
+ Empty => empty_length_fifo,
+ Full => open
+ );
+
+ THE_DMA_STATE : process(CLK_IN)
+ begin --reset at bottom
+ if rising_edge(CLK_IN) then
+ rden_dma_fifo <= '0';
+ reset_dma_fifo <= '0';
+ new_buffer_available <= '0';
+ case current_dma_state is
+ when INACTIVE =>
+ DMA_STATUS_OUT(1) <= '0';
+ if API_RUNNING_IN = '1' then
+ reset_dma_fifo <= '1';
+ current_dma_state <= ACTIVE;
+ end if;
+ when ACTIVE =>
+ if (empty_addr_fifo or empty_length_fifo) = '0' then
+ rden_dma_fifo <= '1';
+ DMA_STATUS_OUT(1) <= '0';
+ current_dma_state <= WAIT_1;
+ end if;
+ if API_RUNNING_IN = '0' then
+ current_dma_state <= INACTIVE;
+ end if;
+ when WAIT_1 => --wait for buffer size calculations
+ current_dma_state <= WAIT_2;
+ when WAIT_2 =>
+ current_dma_state <= WAIT_3;
+ when WAIT_3 =>
+ current_dma_state <= ENABLE;
+ when ENABLE =>
+ new_buffer_available <= '1';
+ current_dma_state <= WORKING;
+ when WORKING =>
+ if buffer_full = '1' and new_buffer_available = '0' then
+ if (empty_addr_fifo or empty_length_fifo) = '1' then
+ DMA_STATUS_OUT(1) <= '1';
+ current_dma_state <= ACTIVE;
+ else
+ current_dma_state <= WAIT_1;
+ rden_dma_fifo <= '1';
+ end if;
+ end if;
+ if API_RUNNING_IN = '0' then
+ current_dma_state <= INACTIVE;
+ end if;
+ when DMA_RESET =>
+ reset_dma_fifo <= '1';
+ DMA_STATUS_OUT(1) <= '1';
+ current_dma_state <= INACTIVE;
+ end case;
+
+ if RESET_IN = '1' then
+ current_dma_state <= INACTIVE;
+ end if;
+
+ if DMA_CONTROL_IN(1) = '1' then
+ current_dma_state <= DMA_RESET;
+ end if;
+ end if;
+ end process;
+
+
+ process(CLK_IN)
+ begin
+ if rising_edge(CLK_IN) then
+ dma_length_i <= next_dma_length_i;
+ dma_start_address_i <= next_dma_start_address_i;
+
+ end if;
+ end process;
+
+
+
+-----------------------------------------------------------------------
+-- Burst Length & Buffer Space calculation
+-----------------------------------------------------------------------
+PROC_BUFFER_SPACE : process(CLK_IN)
+
+ begin
+ buffer_space_end <= unsigned(dma_start_address_i) + unsigned(dma_length_i(28 downto 0)) * to_unsigned(4,3);
+ buffer_space_afull <= buffer_space_end - (unsigned(DMA_CONFIG_IN(7 downto 0)) * to_unsigned(4,24));
+
+ --Enough space for full burst
+ if rising_edge(CLK_IN) then
+ if (copy_state = IDLE or copy_state = LAST_WORD or copy_state = BUFFER_FULL_WAIT or copy_state = WAIT_BUFFER) then
+ if busy = '0' then
+ buffer_space_available <= '1';
+ current_burst_length <= unsigned(DMA_CONFIG_IN(7 downto 0));
+ elsif current_address < buffer_space_afull then
+ if unsigned(DMA_CONFIG_IN(7 downto 0)) < unsigned(credits_sys(8 downto 1)) then
+ current_burst_length <= unsigned(DMA_CONFIG_IN(7 downto 0));
+ else
+ current_burst_length <= unsigned(credits_sys(8 downto 1));
+ end if;
+ buffer_space_available <= '1';
+ elsif current_address < buffer_space_end then
+ current_burst_length <= buffer_space_end(9 downto 2) - current_address(9 downto 2);
+ buffer_space_available <= '1';
+ else
+ buffer_space_available <= '0';
+ end if;
+ end if;
end if;
end process;
buf_API_READ_OUT <= '0';
copy_length <= (others => '0'); --length counter while copying
buffer_full_strobe <= '0';
+ total_length <= (others => '0');
else
tx_wr_en <= '0';
tx_length_wr_en <= '0';
case copy_state is
when IDLE =>
copy_state_bits <= "00";
- if DMA_CONTROL_IN(0) = '1' then
- total_length <= (others => '0');
- current_address <= unsigned(DMA_START_ADDR_IN);
+ if new_buffer_available = '1' then
+ current_address <= unsigned(dma_start_address_i);
end if;
if busy = '1' and (API_RUNNING_IN = '1' or API_DATAREADY_IN = '1') and tx_almost_full = '0' then --DMA enable and API running
- if --Enough space in buffer for one burst
- current_address + unsigned(DMA_CONFIG_IN(7 downto 0)) * to_unsigned(4,32)
- < unsigned(DMA_START_ADDR_IN) + unsigned(DMA_LENGTH_IN) * to_unsigned(4,32) then
+ if buffer_space_available = '1' then --Enough space in buffer for one burst
+-- current_address + unsigned(DMA_CONFIG_IN(7 downto 0)) * to_unsigned(4,32)
+-- < unsigned(DMA_START_ADDR_IN) + unsigned(DMA_LENGTH_IN) * to_unsigned(4,32) then
tx_data_in( 7 downto 0) <= std_logic_vector(current_address(31 downto 24));
tx_data_in(15 downto 8) <= std_logic_vector(current_address(23 downto 16));
tx_data_in(23 downto 16) <= std_logic_vector(current_address(15 downto 8));
tx_data_in(31 downto 24) <= std_logic_vector(current_address( 7 downto 0));
tx_data_in(35 downto 32) <= x"0";
buf_API_READ_OUT <= '1';
- copy_length <= (others => '0');
+ copy_length <= (0 => '1', others => '0');
copy_state <= RUNNING;
tx_wr_en <= '1';
tx_fifo_padding <= x"8";
when LAST_WORD =>
copy_state_bits <= "10";
tx_data_in <= (others => '0');
- tx_wr_en <= not copy_length(0); --write padding
+ tx_wr_en <= copy_length(0); --write padding
tx_fifo_padding <= x"8";
tx_length_wr_en <= '1';
copy_state <= IDLE;
when BUFFER_FULL_WAIT =>
copy_state_bits <= "11";
- if DMA_CONTROL_IN(0) = '1' then
- copy_state <= IDLE;
- total_length <= (others => '0');
- current_address <= unsigned(DMA_START_ADDR_IN);
+ if new_buffer_available = '1' then
+ copy_state <= WAIT_BUFFER;
+ current_address <= unsigned(dma_start_address_i);
end if;
+
+ when WAIT_BUFFER =>
+ copy_state <= IDLE;
end case;
+ if reset_dma_fifo = '1' and finished_sys = '0' then
+ total_length <= (others => '0');
+ end if;
+
end if;
end if;
end process;
- tx_length_data_in <= last_words & std_logic_vector(copy_length);
+ tx_length_data_in <= last_words & std_logic_vector(copy_length-to_unsigned(1,8));
AlmostFull => tx_almost_full --at 464 words
);
-THE_TX_LENGTH_FIFO : fifo_8x512_dualclock
+THE_TX_LENGTH_FIFO : fifo_9x512_dualclock
port map (
Data => tx_length_data_in,
WrClock => CLK_IN,
AlmostFull => tx_length_almost_full
);
-
-----------------------------------------------------------------------
-- Send Data State Machine
-----------------------------------------------------------------------
tx_rd_en <= '0';
finished <= '0';
send_state <= SEND_IDLE;
- TX_ST_OUT <= '0';
+ tx_st_i <= '0';
tx_end_i <= '0';
TX_DWEN_OUT <= '0';
buf_TX_DATA_OUT <= (others => '0');
finished <= tx_length_data_out(7);
send_state <= SEND_IDLE;
elsif (TX_CA_PH_IN(8) = '1' or (unsigned(TX_CA_PH_IN(7 downto 0)) > to_unsigned(1,8)))
- and (TX_CA_PD_IN(12) = '1' or (unsigned(TX_CA_PD_IN(8 downto 2)) >= unsigned(tx_length_data_out(6 downto 0))))
+ and ((TX_CA_PD_IN(12 downto 8) /= "00000") or (unsigned(TX_CA_PD_IN(7 downto 0)) >= unsigned(tx_length_data_out(7 downto 0))))
then
- TX_ST_OUT <= '0';
+ tx_st_i <= '0';
tx_end_i <= '0';
TX_DWEN_OUT <= '0';
buf_TX_DATA_OUT <= '0' & --R
'0' & --EP
"10" & --Attr
"00" & --R
- "000" & tx_length_data_out(6 downto 0) & --Length
+ "00" & tx_length_data_out(7 downto 0) & --Length
REQUESTOR_ID_IN & --Requestor ID
x"00" & -- Tag
x"FF"; --Byte Enables
tx_rd_en <= '1'; --
tx_req_i <= '1';
- tx_length <= unsigned(tx_length_data_out(6 downto 0));
+ tx_length <= unsigned(tx_length_data_out(7 downto 0));
send_state <= SEND_START;
end if;
send_state_bits <= x"2";
if TX_RDY_IN = '1' then
if TX_VAL_IN = '1' then
- TX_ST_OUT <= '1';
+ tx_st_i <= '1';
if tx_length > to_unsigned(1,3) then
tx_rd_en <= '1';
end if;
when SEND_DATA =>
send_state_bits <= x"7";
- TX_ST_OUT <= '0';
+ tx_st_i <= '0';
TX_DWEN_OUT <= tx_fifo_data_out(71);
buf_TX_DATA_OUT <= tx_fifo_data_out(31 downto 0) & tx_fifo_data_out(67 downto 36);
tx_length <= tx_length - to_unsigned(1,3);
else
tx_end_i <= '1';
- finished <= tx_length_data_out(7);
+ finished <= tx_length_data_out(8);
send_state <= SEND_IDLE;
end if;
end if;
end if;
end process;
+TX_ST_OUT <= tx_st_i;
TX_END_OUT <= tx_end_i;
TX_REQ_OUT <= tx_req_i;
TX_DATA_OUT <= buf_TX_DATA_OUT;
PULSE_B_OUT => finished_sys
);
+--sync credits to sys clock
+THE_Credit_FIFO : fifo_16x512_dualclock
+ port map (
+ Data => "000" & TX_CA_PD_IN(12 downto 0),
+ WrClock => CLK_125_IN,
+ RdClock => CLK_IN,
+ WrEn => '1',
+ RdEn => '1',
+ Reset => reset_i,
+ RPReset => reset_i,
+ Q(12 downto 0) => credits_sys,
+ Q(15 downto 13) => dummy,
+ Empty => open,
+ Full => open,
+ AlmostEmpty => open,
+ AlmostFull => open
+ );
+
-----------------------------------------------------------------------
-- Status Flags
if rising_edge(CLK_IN) then
if reset_i = '1' then
busy <= '0';
- elsif DMA_CONTROL_IN(0) = '1' then
+ elsif new_buffer_available = '1' then
busy <= '1';
elsif finished_sys = '1' then
busy <= '0';
PROC_BUFFER_FULL : process(CLK_IN)
begin
if rising_edge(CLK_IN) then
- if reset_i = '1' or DMA_CONTROL_IN(0) = '1' then
+ if reset_i = '1' or new_buffer_available = '1' then
buffer_full <= '0';
elsif buffer_full_strobe = '1' then
buffer_full <= '1';
end if;
end process;
+
+DMA_STATUS_OUT(0) <= busy;
+DMA_STATUS_OUT(7 downto 2) <= (others => '0');
PROC_STATUS_OUT : process(CLK_IN)
begin
if rising_edge(CLK_IN) then
- DMA_STATUS_OUT(0) <= busy;
- DMA_STATUS_OUT(1) <= buffer_full;
- DMA_STATUS_OUT(7 downto 2) <= (others => '0');
DMA_STATUS_OUT(31 downto 8) <= std_logic_vector(total_length);
end if;
end process;
STATUS_REG_OUT(13) <= tx_length_empty;
STATUS_REG_OUT(14) <= tx_almost_full;
STATUS_REG_OUT(15) <= tx_end_i;
-STATUS_REG_OUT(22 downto 16) <= std_logic_vector(copy_length);
-STATUS_REG_OUT(23) <= buffer_full;
-STATUS_REG_OUT(31 downto 24) <= (others => '0');
+STATUS_REG_OUT(23 downto 16) <= std_logic_vector(copy_length);
+STATUS_REG_OUT(24) <= buffer_full;
+STATUS_REG_OUT(31 downto 25) <= (others => '0');
STATUS_REG_OUT(40 downto 32) <= TX_CA_PH_IN;
-STATUS_REG_OUT(53 downto 41) <= TX_CA_PD_IN;
+STATUS_REG_OUT(53 downto 41) <= credits_sys(12 downto 0); --TX_CA_PD_IN;
STATUS_REG_OUT(62 downto 54) <= TX_CA_NPH_IN;
STATUS_REG_OUT(63) <= '0';
-STATUS_REG_OUT(95 downto 64) <= x"000" & tx_length_data_in & "00" & tx_length_rd_en & tx_rd_en & tx_length_data_out;
+STATUS_REG_OUT(95 downto 64) <= std_logic_vector(current_burst_length) & "000" & tx_length_data_in & "0" & tx_length_rd_en & tx_rd_en & tx_length_data_out;
STATUS_REG_OUT(127 downto 96)<= std_logic_vector(current_address);
+
+STATUS_REG_OUT(131 downto 128) <= dma_fifo_state;
+STATUS_REG_OUT(132) <= '0';
+STATUS_REG_OUT(133) <= buffer_full;
+STATUS_REG_OUT(134) <= reset_dma_fifo;
+STATUS_REG_OUT(135) <= rden_dma_fifo;
+STATUS_REG_OUT(136) <= empty_addr_fifo;
+STATUS_REG_OUT(137) <= empty_length_fifo;
+STATUS_REG_OUT(139 downto 138) <= "00";
+STATUS_REG_OUT(147 downto 140) <= dma_length_i(11 downto 4);
+STATUS_REG_OUT(159 downto 148) <= dma_start_address_i(15 downto 4);
+
+dma_fifo_state <= x"0" when current_dma_state = INACTIVE else
+ x"1" when current_dma_state = ACTIVE else
+ x"2" when current_dma_state = WAIT_1 or current_dma_state = WAIT_2 or current_dma_state = WAIT_3 else
+ x"2" when current_dma_state = ENABLE else
+ x"3" when current_dma_state = WORKING else
+ x"5" when current_dma_state = DMA_RESET else
+ x"F";
+
+
-----------------------------------------------------------------------
-- Debug
-----------------------------------------------------------------------
begin
if rising_edge(CLK_IN) then
DEBUG_OUT(0) <= busy;
- DEBUG_OUT(1) <= DMA_CONTROL_IN(0);
+ DEBUG_OUT(1) <= new_buffer_available;
DEBUG_OUT(2) <= API_DATAREADY_IN;
DEBUG_OUT(3) <= buf_API_READ_OUT;
- DEBUG_OUT(4) <= tx_rd_en;
- DEBUG_OUT(5) <= tx_empty;
- DEBUG_OUT(6) <= tx_length_empty;
- DEBUG_OUT(7) <= tx_length_data_out(7);
- DEBUG_OUT(8) <= tx_req_i;
- DEBUG_OUT(9) <= TX_RDY_IN;
- DEBUG_OUT(10)<= tx_length_data_out(7);
- DEBUG_OUT(11)<= tx_end_i;
+ DEBUG_OUT(4) <= API_RUNNING_IN;
+ DEBUG_OUT(5) <= rden_dma_fifo;
+ DEBUG_OUT(6) <= reset_dma_fifo;
+ DEBUG_OUT(7) <= tx_length_data_out(8);
+ DEBUG_OUT(8) <= tx_st_i;
+ DEBUG_OUT(9) <= tx_end_i;
+ DEBUG_OUT(11 downto 10)<= dma_fifo_state(1 downto 0);
DEBUG_OUT(13 downto 12) <= copy_state_bits;
DEBUG_OUT(15 downto 14) <= send_state_bits(1 downto 0);
- DEBUG_OUT(23 downto 16) <= API_DATA_IN(7 downto 0);
- DEBUG_OUT(31 downto 24) <= buf_TX_DATA_OUT(7 downto 0);
+ DEBUG_OUT(23 downto 16) <= credits_sys(7 downto 0);
+ DEBUG_OUT(31 downto 24) <= tx_length(7 downto 0);
end if;
end process;
CLK_IN : in std_logic;
CLK_125_IN : in std_logic;
- DMA_START_ADDR_IN : in std_logic_vector(31 downto 0); --0x700
- DMA_LENGTH_IN : in std_logic_vector(31 downto 0); --0x701
+ DMA_DATA_IN : in std_logic_vector(31 downto 0);
+ DMA_LENGTH_WR_IN : in std_logic;
+ DMA_ADDR_WR_IN : in std_logic;
DMA_CONTROL_IN : in std_logic_vector(31 downto 0); --0x702 write
--0: activate
--31..24: max burst size, 32 bit words
RX_DWEN_IN : in std_logic;
RX_DATA_IN : in std_logic_vector(63 downto 0);
- STATUS_REG_OUT : out std_logic_vector(127 downto 0);
+ STATUS_REG_OUT : out std_logic_vector(159 downto 0);
DEBUG_OUT : out std_logic_vector(31 downto 0)
);
);
end component;
+component fifo_32x512 is
+ port (
+ Data: in std_logic_vector(31 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end component;
+
component fifo_72x512 is
port (
Data: in std_logic_vector(71 downto 0);
AlmostEmpty: out std_logic; AlmostFull: out std_logic);
end component;
+ component fifo_9x512_dualclock
+ port (Data: in std_logic_vector(8 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ RPReset: in std_logic; Q: out std_logic_vector(8 downto 0);
+ Empty: out std_logic; Full: out std_logic;
+ AlmostEmpty: out std_logic; AlmostFull: out std_logic);
+ end component;
+
+ component fifo_16x512_dualclock
+ port (Data: in std_logic_vector(15 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ RPReset: in std_logic; Q: out std_logic_vector(15 downto 0);
+ Empty: out std_logic; Full: out std_logic;
+ AlmostEmpty: out std_logic; AlmostFull: out std_logic);
+ end component;
+
end package;
-n 1
-y
-s 12
--t 7
+-t 8
-c 1
-e 2
-m nodelist.txt
add_file -vhdl -lib work "design/wb_tlc_cpld.vhd"
add_file -vhdl -lib work "design/cores/cpld_fifo.vhd"
add_file -vhdl -lib work "../trbnet/lattice/scm/fifo_72x512.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/scm/fifo_32x512.vhd"
add_file -vhdl -lib work "design/dma_core.vhd"
add_file -verilog "/d/sugar/lattice/diamond/1.1/cae_library/synthesis/verilog/scm.v"
add_file -vhdl -lib work "design/cores/fifo_32to64x512_dualclock.vhd"
+add_file -vhdl -lib work "design/cores/fifo_16x512_dualclock.vhd"
+add_file -vhdl -lib work "design/cores/fifo_9x512_dualclock.vhd"
add_file -vhdl -lib work "design/cores/fifo_8x512_dualclock.vhd"
add_file -vhdl -lib work "design/pci_core.vhd"
add_file -verilog "vcode/pci_exp_ddefines.v"
-- test(9) <= bus_dout(15);\r
-- test(15 downto 10) <= debug_pci_core(21 downto 16);\r
\r
- test(15 downto 0) <= debug_endpoint(15 downto 0);\r
+ test(31 downto 0) <= debug_endpoint(31 downto 0);\r
\r
-- test(3 downto 0) <= med_stat_op(7 downto 4); --fsm state\r
-- test(5 downto 4) <= med_stat_debug(46 downto 45); --tx_k\r
jspc29 / pexor.git / commitdiff